]> git.proxmox.com Git - mirror_edk2.git/blob - MdeModulePkg/Include/Library/PciHostBridgeLib.h
UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm
[mirror_edk2.git] / MdeModulePkg / Include / Library / PciHostBridgeLib.h
1 /** @file
2 PCI Host Bridge Library consumed by PciHostBridgeDxe driver returning
3 the platform specific information about the PCI Host Bridge.
4
5 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 #ifndef __PCI_HOST_BRIDGE_LIB_H__
11 #define __PCI_HOST_BRIDGE_LIB_H__
12
13 //
14 // (Base > Limit) indicates an aperture is not available.
15 //
16 typedef struct {
17 //
18 // Base and Limit are the device address instead of host address when
19 // Translation is not zero
20 //
21 UINT64 Base;
22 UINT64 Limit;
23 //
24 // According to UEFI 2.7, Device Address = Host Address + Translation,
25 // so Translation = Device Address - Host Address.
26 // On platforms where Translation is not zero, the subtraction is probably to
27 // be performed with UINT64 wrap-around semantics, for we may translate an
28 // above-4G host address into a below-4G device address for legacy PCIe device
29 // compatibility.
30 //
31 // NOTE: The alignment of Translation is required to be larger than any BAR
32 // alignment in the same root bridge, so that the same alignment can be
33 // applied to both device address and host address, which simplifies the
34 // situation and makes the current resource allocation code in generic PCI
35 // host bridge driver still work.
36 //
37 UINT64 Translation;
38 } PCI_ROOT_BRIDGE_APERTURE;
39
40 typedef struct {
41 UINT32 Segment; ///< Segment number.
42 UINT64 Supports; ///< Supported attributes.
43 ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
44 ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
45 UINT64 Attributes; ///< Initial attributes.
46 ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
47 ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
48 BOOLEAN DmaAbove4G; ///< DMA above 4GB memory.
49 ///< Set to TRUE when root bridge supports DMA above 4GB memory.
50 BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the root bridge supports
51 ///< Extended (4096-byte) Configuration Space.
52 ///< When TRUE, the root bridge supports
53 ///< 256-byte Configuration Space only.
54 BOOLEAN ResourceAssigned; ///< Resource assignment status of the root bridge.
55 ///< Set to TRUE if Bus/IO/MMIO resources for root bridge have been assigned.
56 UINT64 AllocationAttributes; ///< Allocation attributes.
57 ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and
58 ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()
59 ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
60 PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which can be used by the root bridge.
61 PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which can be used by the root bridge.
62 PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below 4GB which can be used by the root bridge.
63 PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture above 4GB which can be used by the root bridge.
64 PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
65 PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
66 EFI_DEVICE_PATH_PROTOCOL *DevicePath; ///< Device path.
67 } PCI_ROOT_BRIDGE;
68
69 /**
70 Return all the root bridge instances in an array.
71
72 @param Count Return the count of root bridge instances.
73
74 @return All the root bridge instances in an array.
75 The array should be passed into PciHostBridgeFreeRootBridges()
76 when it's not used.
77 **/
78 PCI_ROOT_BRIDGE *
79 EFIAPI
80 PciHostBridgeGetRootBridges (
81 UINTN *Count
82 );
83
84 /**
85 Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
86
87 @param Bridges The root bridge instances array.
88 @param Count The count of the array.
89 **/
90 VOID
91 EFIAPI
92 PciHostBridgeFreeRootBridges (
93 PCI_ROOT_BRIDGE *Bridges,
94 UINTN Count
95 );
96
97 /**
98 Inform the platform that the resource conflict happens.
99
100 @param HostBridgeHandle Handle of the Host Bridge.
101 @param Configuration Pointer to PCI I/O and PCI memory resource descriptors.
102 The Configuration contains the resources for all the
103 root bridges. The resource for each root bridge is
104 terminated with END descriptor and an additional END
105 is appended indicating the end of the entire resources.
106 The resource descriptor field values follow the description
107 in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SubmitResources().
108 **/
109 VOID
110 EFIAPI
111 PciHostBridgeResourceConflict (
112 EFI_HANDLE HostBridgeHandle,
113 VOID *Configuration
114 );
115
116 #endif