MdeModulePkg/Include/UniversalPayload/PciRootBridges.h

   1 /** @file
   2   This file defines the structure for the PCI Root Bridges.
   3
   4   Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7   @par Revision Reference:
   8     - Universal Payload Specification 0.75 (https://universalpayload.github.io/documentation/)
   9 **/
  10
  11 #ifndef UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_
  12 #define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_
  13
  14 #include <UniversalPayload/UniversalPayload.h>
  15
  16 #pragma pack(1)
  17
  18 //
  19 // (Base > Limit) indicates an aperture is not available.
  20 //
  21 typedef struct {
  22   //
  23   // Base and Limit are the device address instead of host address when
  24   // Translation is not zero
  25   //
  26   UINT64 Base;
  27   UINT64 Limit;
  28   //
  29   // According to UEFI 2.7, Device Address = Host Address + Translation,
  30   // so Translation = Device Address - Host Address.
  31   // On platforms where Translation is not zero, the subtraction is probably to
  32   // be performed with UINT64 wrap-around semantics, for we may translate an
  33   // above-4G host address into a below-4G device address for legacy PCIe device
  34   // compatibility.
  35   //
  36   // NOTE: The alignment of Translation is required to be larger than any BAR
  37   // alignment in the same root bridge, so that the same alignment can be
  38   // applied to both device address and host address, which simplifies the
  39   // situation and makes the current resource allocation code in generic PCI
  40   // host bridge driver still work.
  41   //
  42   UINT64 Translation;
  43 } UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE;
  44
  45 ///
  46 /// Payload PCI Root Bridge Information HOB
  47 ///
  48 typedef struct {
  49   UINT32                                     Segment;               ///< Segment number.
  50   UINT64                                     Supports;              ///< Supported attributes.
  51                                                                     ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
  52                                                                     ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  53   UINT64                                     Attributes;            ///< Initial attributes.
  54                                                                     ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()
  55                                                                     ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  56   BOOLEAN                                    DmaAbove4G;            ///< DMA above 4GB memory.
  57                                                                     ///< Set to TRUE when root bridge supports DMA above 4GB memory.
  58   BOOLEAN                                    NoExtendedConfigSpace; ///< When FALSE, the root bridge supports
  59                                                                     ///< Extended (4096-byte) Configuration Space.
  60                                                                     ///< When TRUE, the root bridge supports
  61                                                                     ///< 256-byte Configuration Space only.
  62   UINT64                                     AllocationAttributes;  ///< Allocation attributes.
  63                                                                     ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and
  64                                                                     ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()
  65                                                                     ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
  66   UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Bus;                   ///< Bus aperture which can be used by the root bridge.
  67   UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Io;                    ///< IO aperture which can be used by the root bridge.
  68   UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Mem;                   ///< MMIO aperture below 4GB which can be used by the root bridge.
  69   UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G;            ///< MMIO aperture above 4GB which can be used by the root bridge.
  70   UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMem;                  ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.
  71   UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;           ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.
  72   UINT32                                     HID;                   ///< PnP hardware ID of the root bridge. This value must match the corresponding
  73                                                                     ///< _HID in the ACPI name space.
  74   UINT32                                     UID;                   ///< Unique ID that is required by ACPI if two devices have the same _HID.
  75                                                                     ///< This value must also match the corresponding _UID/_HID pair in the ACPI name space.
  76 } UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE;
  77
  78 typedef struct {
  79   UNIVERSAL_PAYLOAD_GENERIC_HEADER   Header;
  80   BOOLEAN                            ResourceAssigned;
  81   UINT8                              Count;
  82   UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE  RootBridge[0];
  83 } UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES;
  84
  85 #pragma pack()
  86
  87 #define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION 1
  88
  89 extern GUID gUniversalPayloadPciRootBridgeInfoGuid;
  90
  91 #endif // UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_