2 16550 UART Serial Port library functions
4 (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
5 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
6 Copyright (c) 2018, AMD Incorporated. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
13 #include <IndustryStandard/Pci.h>
14 #include <Library/SerialPortLib.h>
15 #include <Library/PcdLib.h>
16 #include <Library/IoLib.h>
17 #include <Library/PciLib.h>
18 #include <Library/PlatformHookLib.h>
19 #include <Library/BaseLib.h>
24 #define PCI_BRIDGE_32_BIT_IO_SPACE 0x01
27 // 16550 UART register offsets and bitfields
29 #define R_UART_RXBUF 0 // LCR_DLAB = 0
30 #define R_UART_TXBUF 0 // LCR_DLAB = 0
31 #define R_UART_BAUD_LOW 0 // LCR_DLAB = 1
32 #define R_UART_BAUD_HIGH 1 // LCR_DLAB = 1
33 #define R_UART_IER 1 // LCR_DLAB = 0
35 #define B_UART_FCR_FIFOE BIT0
36 #define B_UART_FCR_FIFO64 BIT5
38 #define B_UART_LCR_DLAB BIT7
40 #define B_UART_MCR_DTRC BIT0
41 #define B_UART_MCR_RTS BIT1
43 #define B_UART_LSR_RXRDY BIT0
44 #define B_UART_LSR_TXRDY BIT5
45 #define B_UART_LSR_TEMT BIT6
47 #define B_UART_MSR_CTS BIT4
48 #define B_UART_MSR_DSR BIT5
49 #define B_UART_MSR_RI BIT6
50 #define B_UART_MSR_DCD BIT7
53 // 4-byte structure for each PCI node in PcdSerialPciDeviceInfo
58 UINT16 PowerManagementStatusAndControlRegister
;
59 } PCI_UART_DEVICE_INFO
;
62 Read an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is read from
63 MMIO space. If PcdSerialUseMmio is FALSE, then the value is read from I/O space. The
64 parameter Offset is added to the base address of the 16550 registers that is specified
65 by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO space access
66 width and defaults to 8 bit access, and supports 8 or 32 bit access.
68 @param Base The base address register of UART device.
69 @param Offset The offset of the 16550 register to read.
71 @return The value read from the 16550 register.
75 SerialPortReadRegister (
80 if (PcdGetBool (PcdSerialUseMmio
)) {
81 if (PcdGet8 (PcdSerialRegisterAccessWidth
) == 32) {
82 return (UINT8
) MmioRead32 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
));
84 return MmioRead8 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
));
86 return IoRead8 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
));
91 Write an 8-bit 16550 register. If PcdSerialUseMmio is TRUE, then the value is written to
92 MMIO space. If PcdSerialUseMmio is FALSE, then the value is written to I/O space. The
93 parameter Offset is added to the base address of the 16550 registers that is specified
94 by PcdSerialRegisterBase. PcdSerialRegisterAccessWidth specifies the MMIO space access
95 width and defaults to 8 bit access, and supports 8 or 32 bit access.
97 @param Base The base address register of UART device.
98 @param Offset The offset of the 16550 register to write.
99 @param Value The value to write to the 16550 register specified by Offset.
101 @return The value written to the 16550 register.
105 SerialPortWriteRegister (
111 if (PcdGetBool (PcdSerialUseMmio
)) {
112 if (PcdGet8 (PcdSerialRegisterAccessWidth
) == 32) {
113 return (UINT8
) MmioWrite32 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
), (UINT8
)Value
);
115 return MmioWrite8 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
), Value
);
117 return IoWrite8 (Base
+ Offset
* PcdGet32 (PcdSerialRegisterStride
), Value
);
122 Update the value of an 16-bit PCI configuration register in a PCI device. If the
123 PCI Configuration register specified by PciAddress is already programmed with a
124 non-zero value, then return the current value. Otherwise update the PCI configuration
125 register specified by PciAddress with the value specified by Value and return the
126 value programmed into the PCI configuration register. All values must be masked
127 using the bitmask specified by Mask.
129 @param PciAddress PCI Library address of the PCI Configuration register to update.
130 @param Value The value to program into the PCI Configuration Register.
131 @param Mask Bitmask of the bits to check and update in the PCI configuration register.
135 SerialPortLibUpdatePciRegister16 (
143 CurrentValue
= PciRead16 (PciAddress
) & Mask
;
144 if (CurrentValue
!= 0) {
147 return PciWrite16 (PciAddress
, Value
& Mask
);
151 Update the value of an 32-bit PCI configuration register in a PCI device. If the
152 PCI Configuration register specified by PciAddress is already programmed with a
153 non-zero value, then return the current value. Otherwise update the PCI configuration
154 register specified by PciAddress with the value specified by Value and return the
155 value programmed into the PCI configuration register. All values must be masked
156 using the bitmask specified by Mask.
158 @param PciAddress PCI Library address of the PCI Configuration register to update.
159 @param Value The value to program into the PCI Configuration Register.
160 @param Mask Bitmask of the bits to check and update in the PCI configuration register.
162 @return The Secondary bus number that is actually programed into the PCI to PCI Bridge device.
166 SerialPortLibUpdatePciRegister32 (
174 CurrentValue
= PciRead32 (PciAddress
) & Mask
;
175 if (CurrentValue
!= 0) {
178 return PciWrite32 (PciAddress
, Value
& Mask
);
182 Retrieve the I/O or MMIO base address register for the PCI UART device.
184 This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART
185 Device if they are not already enabled.
187 @return The base address register of the UART device.
191 GetSerialRegisterBase (
197 UINTN SubordinateBusNumber
;
199 UINT32 ParentIoLimit
;
200 UINT16 ParentMemoryBase
;
201 UINT16 ParentMemoryLimit
;
206 UINTN SerialRegisterBase
;
208 UINT32 RegisterBaseMask
;
209 PCI_UART_DEVICE_INFO
*DeviceInfo
;
212 // Get PCI Device Info
214 DeviceInfo
= (PCI_UART_DEVICE_INFO
*) PcdGetPtr (PcdSerialPciDeviceInfo
);
217 // If PCI Device Info is empty, then assume fixed address UART and return PcdSerialRegisterBase
219 if (DeviceInfo
->Device
== 0xff) {
220 return (UINTN
)PcdGet64 (PcdSerialRegisterBase
);
224 // Assume PCI Bus 0 I/O window is 0-64KB and MMIO windows is 0-4GB
226 ParentMemoryBase
= 0 >> 16;
227 ParentMemoryLimit
= 0xfff00000 >> 16;
228 ParentIoBase
= 0 >> 12;
229 ParentIoLimit
= 0xf000 >> 12;
232 // Enable I/O and MMIO in PCI Bridge
233 // Assume Root Bus Numer is Zero.
235 for (BusNumber
= 0; (DeviceInfo
+ 1)->Device
!= 0xff; DeviceInfo
++) {
237 // Compute PCI Lib Address to PCI to PCI Bridge
239 PciLibAddress
= PCI_LIB_ADDRESS (BusNumber
, DeviceInfo
->Device
, DeviceInfo
->Function
, 0);
242 // Retrieve and verify the bus numbers in the PCI to PCI Bridge
244 BusNumber
= PciRead8 (PciLibAddress
+ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
);
245 SubordinateBusNumber
= PciRead8 (PciLibAddress
+ PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET
);
246 if (BusNumber
== 0 || BusNumber
> SubordinateBusNumber
) {
251 // Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge
253 if (PcdGetBool (PcdSerialUseMmio
)) {
254 MemoryLimit
= PciRead16 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.MemoryLimit
)) & 0xfff0;
255 MemoryBase
= PciRead16 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.MemoryBase
)) & 0xfff0;
258 // If PCI Bridge MMIO window is disabled, then return 0
260 if (MemoryLimit
< MemoryBase
) {
265 // If PCI Bridge MMIO window is not in the address range decoded by the parent PCI Bridge, then return 0
267 if (MemoryBase
< ParentMemoryBase
|| MemoryBase
> ParentMemoryLimit
|| MemoryLimit
> ParentMemoryLimit
) {
270 ParentMemoryBase
= MemoryBase
;
271 ParentMemoryLimit
= MemoryLimit
;
273 IoLimit
= PciRead8 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.IoLimit
));
274 if ((IoLimit
& PCI_BRIDGE_32_BIT_IO_SPACE
) == 0) {
275 IoLimit
= IoLimit
>> 4;
277 IoLimit
= (PciRead16 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.IoLimitUpper16
)) << 4) | (IoLimit
>> 4);
279 IoBase
= PciRead8 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.IoBase
));
280 if ((IoBase
& PCI_BRIDGE_32_BIT_IO_SPACE
) == 0) {
281 IoBase
= IoBase
>> 4;
283 IoBase
= (PciRead16 (PciLibAddress
+ OFFSET_OF (PCI_TYPE01
, Bridge
.IoBaseUpper16
)) << 4) | (IoBase
>> 4);
287 // If PCI Bridge I/O window is disabled, then return 0
289 if (IoLimit
< IoBase
) {
294 // If PCI Bridge I/O window is not in the address range decoded by the parent PCI Bridge, then return 0
296 if (IoBase
< ParentIoBase
|| IoBase
> ParentIoLimit
|| IoLimit
> ParentIoLimit
) {
299 ParentIoBase
= IoBase
;
300 ParentIoLimit
= IoLimit
;
305 // Compute PCI Lib Address to PCI UART
307 PciLibAddress
= PCI_LIB_ADDRESS (BusNumber
, DeviceInfo
->Device
, DeviceInfo
->Function
, 0);
310 // Find the first IO or MMIO BAR
312 RegisterBaseMask
= 0xFFFFFFF0;
313 for (BarIndex
= 0; BarIndex
< PCI_MAX_BAR
; BarIndex
++) {
314 SerialRegisterBase
= PciRead32 (PciLibAddress
+ PCI_BASE_ADDRESSREG_OFFSET
+ BarIndex
* 4);
315 if (PcdGetBool (PcdSerialUseMmio
) && ((SerialRegisterBase
& BIT0
) == 0)) {
319 RegisterBaseMask
= 0xFFFFFFF0;
323 if ((!PcdGetBool (PcdSerialUseMmio
)) && ((SerialRegisterBase
& BIT0
) != 0)) {
327 RegisterBaseMask
= 0xFFFFFFF8;
333 // MMIO or IO BAR is not found.
335 if (BarIndex
== PCI_MAX_BAR
) {
342 SerialRegisterBase
= SerialPortLibUpdatePciRegister32 (
343 PciLibAddress
+ PCI_BASE_ADDRESSREG_OFFSET
+ BarIndex
* 4,
344 (UINT32
)PcdGet64 (PcdSerialRegisterBase
),
349 // Verify that the UART BAR is in the address range decoded by the parent PCI Bridge
351 if (PcdGetBool (PcdSerialUseMmio
)) {
352 if (((SerialRegisterBase
>> 16) & 0xfff0) < ParentMemoryBase
|| ((SerialRegisterBase
>> 16) & 0xfff0) > ParentMemoryLimit
) {
356 if ((SerialRegisterBase
>> 12) < ParentIoBase
|| (SerialRegisterBase
>> 12) > ParentIoLimit
) {
362 // Enable I/O and MMIO in PCI UART Device if they are not already enabled
365 PciLibAddress
+ PCI_COMMAND_OFFSET
,
366 PcdGetBool (PcdSerialUseMmio
) ? EFI_PCI_COMMAND_MEMORY_SPACE
: EFI_PCI_COMMAND_IO_SPACE
370 // Force D0 state if a Power Management and Status Register is specified
372 if (DeviceInfo
->PowerManagementStatusAndControlRegister
!= 0x00) {
373 if ((PciRead16 (PciLibAddress
+ DeviceInfo
->PowerManagementStatusAndControlRegister
) & (BIT0
| BIT1
)) != 0x00) {
374 PciAnd16 (PciLibAddress
+ DeviceInfo
->PowerManagementStatusAndControlRegister
, (UINT16
)~(BIT0
| BIT1
));
376 // If PCI UART was not in D0, then make sure FIFOs are enabled, but do not reset FIFOs
378 SerialPortWriteRegister (SerialRegisterBase
, R_UART_FCR
, (UINT8
)(PcdGet8 (PcdSerialFifoControl
) & (B_UART_FCR_FIFOE
| B_UART_FCR_FIFO64
)));
383 // Get PCI Device Info
385 DeviceInfo
= (PCI_UART_DEVICE_INFO
*) PcdGetPtr (PcdSerialPciDeviceInfo
);
388 // Enable I/O or MMIO in PCI Bridge
389 // Assume Root Bus Numer is Zero.
391 for (BusNumber
= 0; (DeviceInfo
+ 1)->Device
!= 0xff; DeviceInfo
++) {
393 // Compute PCI Lib Address to PCI to PCI Bridge
395 PciLibAddress
= PCI_LIB_ADDRESS (BusNumber
, DeviceInfo
->Device
, DeviceInfo
->Function
, 0);
398 // Enable the I/O or MMIO decode windows in the PCI to PCI Bridge
401 PciLibAddress
+ PCI_COMMAND_OFFSET
,
402 PcdGetBool (PcdSerialUseMmio
) ? EFI_PCI_COMMAND_MEMORY_SPACE
: EFI_PCI_COMMAND_IO_SPACE
406 // Force D0 state if a Power Management and Status Register is specified
408 if (DeviceInfo
->PowerManagementStatusAndControlRegister
!= 0x00) {
409 if ((PciRead16 (PciLibAddress
+ DeviceInfo
->PowerManagementStatusAndControlRegister
) & (BIT0
| BIT1
)) != 0x00) {
410 PciAnd16 (PciLibAddress
+ DeviceInfo
->PowerManagementStatusAndControlRegister
, (UINT16
)~(BIT0
| BIT1
));
414 BusNumber
= PciRead8 (PciLibAddress
+ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET
);
417 return SerialRegisterBase
;
421 Return whether the hardware flow control signal allows writing.
423 @param SerialRegisterBase The base address register of UART device.
425 @retval TRUE The serial port is writable.
426 @retval FALSE The serial port is not writable.
430 UINTN SerialRegisterBase
433 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
434 if (PcdGetBool (PcdSerialDetectCable
)) {
436 // Wait for both DSR and CTS to be set
437 // DSR is set if a cable is connected.
438 // CTS is set if it is ok to transmit data
440 // DSR CTS Description Action
441 // === === ======================================== ========
442 // 0 0 No cable connected. Wait
443 // 0 1 No cable connected. Wait
444 // 1 0 Cable connected, but not clear to send. Wait
445 // 1 1 Cable connected, and clear to send. Transmit
447 return (BOOLEAN
) ((SerialPortReadRegister (SerialRegisterBase
, R_UART_MSR
) & (B_UART_MSR_DSR
| B_UART_MSR_CTS
)) == (B_UART_MSR_DSR
| B_UART_MSR_CTS
));
450 // Wait for both DSR and CTS to be set OR for DSR to be clear.
451 // DSR is set if a cable is connected.
452 // CTS is set if it is ok to transmit data
454 // DSR CTS Description Action
455 // === === ======================================== ========
456 // 0 0 No cable connected. Transmit
457 // 0 1 No cable connected. Transmit
458 // 1 0 Cable connected, but not clear to send. Wait
459 // 1 1 Cable connected, and clar to send. Transmit
461 return (BOOLEAN
) ((SerialPortReadRegister (SerialRegisterBase
, R_UART_MSR
) & (B_UART_MSR_DSR
| B_UART_MSR_CTS
)) != (B_UART_MSR_DSR
));
469 Initialize the serial device hardware.
471 If no initialization is required, then return RETURN_SUCCESS.
472 If the serial device was successfully initialized, then return RETURN_SUCCESS.
473 If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
475 @retval RETURN_SUCCESS The serial device was initialized.
476 @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
481 SerialPortInitialize (
485 RETURN_STATUS Status
;
486 UINTN SerialRegisterBase
;
488 UINT32 CurrentDivisor
;
492 // Perform platform specific initialization required to enable use of the 16550 device
493 // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.
495 Status
= PlatformHookSerialPortInitialize ();
496 if (RETURN_ERROR (Status
)) {
501 // Calculate divisor for baud generator
502 // Ref_Clk_Rate / Baud_Rate / 16
504 Divisor
= PcdGet32 (PcdSerialClockRate
) / (PcdGet32 (PcdSerialBaudRate
) * 16);
505 if ((PcdGet32 (PcdSerialClockRate
) % (PcdGet32 (PcdSerialBaudRate
) * 16)) >= PcdGet32 (PcdSerialBaudRate
) * 8) {
510 // Get the base address of the serial port in either I/O or MMIO space
512 SerialRegisterBase
= GetSerialRegisterBase ();
513 if (SerialRegisterBase
==0) {
514 return RETURN_DEVICE_ERROR
;
518 // See if the serial port is already initialized
521 if ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LCR
) & 0x3F) != (PcdGet8 (PcdSerialLineControl
) & 0x3F)) {
524 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_LCR
) | B_UART_LCR_DLAB
));
525 CurrentDivisor
= SerialPortReadRegister (SerialRegisterBase
, R_UART_BAUD_HIGH
) << 8;
526 CurrentDivisor
|= (UINT32
) SerialPortReadRegister (SerialRegisterBase
, R_UART_BAUD_LOW
);
527 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_LCR
) & ~B_UART_LCR_DLAB
));
528 if (CurrentDivisor
!= Divisor
) {
532 return RETURN_SUCCESS
;
536 // Wait for the serial port to be ready.
537 // Verify that both the transmit FIFO and the shift register are empty.
539 while ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
)) != (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
));
542 // Configure baud rate
544 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, B_UART_LCR_DLAB
);
545 SerialPortWriteRegister (SerialRegisterBase
, R_UART_BAUD_HIGH
, (UINT8
) (Divisor
>> 8));
546 SerialPortWriteRegister (SerialRegisterBase
, R_UART_BAUD_LOW
, (UINT8
) (Divisor
& 0xff));
549 // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
550 // Strip reserved bits from PcdSerialLineControl
552 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, (UINT8
)(PcdGet8 (PcdSerialLineControl
) & 0x3F));
555 // Enable and reset FIFOs
556 // Strip reserved bits from PcdSerialFifoControl
558 SerialPortWriteRegister (SerialRegisterBase
, R_UART_FCR
, 0x00);
559 SerialPortWriteRegister (SerialRegisterBase
, R_UART_FCR
, (UINT8
)(PcdGet8 (PcdSerialFifoControl
) & (B_UART_FCR_FIFOE
| B_UART_FCR_FIFO64
)));
562 // Set FIFO Polled Mode by clearing IER after setting FCR
564 SerialPortWriteRegister (SerialRegisterBase
, R_UART_IER
, 0x00);
567 // Put Modem Control Register(MCR) into its reset state of 0x00.
569 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, 0x00);
571 return RETURN_SUCCESS
;
575 Write data from buffer to serial device.
577 Writes NumberOfBytes data bytes from Buffer to the serial device.
578 The number of bytes actually written to the serial device is returned.
579 If the return value is less than NumberOfBytes, then the write operation failed.
581 If Buffer is NULL, then ASSERT().
583 If NumberOfBytes is zero, then return 0.
585 @param Buffer Pointer to the data buffer to be written.
586 @param NumberOfBytes Number of bytes to written to the serial device.
588 @retval 0 NumberOfBytes is 0.
589 @retval >0 The number of bytes written to the serial device.
590 If this value is less than NumberOfBytes, then the write operation failed.
597 IN UINTN NumberOfBytes
600 UINTN SerialRegisterBase
;
605 if (Buffer
== NULL
) {
609 SerialRegisterBase
= GetSerialRegisterBase ();
610 if (SerialRegisterBase
==0) {
614 if (NumberOfBytes
== 0) {
616 // Flush the hardware
620 // Wait for both the transmit FIFO and shift register empty.
622 while ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
)) != (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
));
625 // Wait for the hardware flow control signal
627 while (!SerialPortWritable (SerialRegisterBase
));
632 // Compute the maximum size of the Tx FIFO
635 if ((PcdGet8 (PcdSerialFifoControl
) & B_UART_FCR_FIFOE
) != 0) {
636 if ((PcdGet8 (PcdSerialFifoControl
) & B_UART_FCR_FIFO64
) == 0) {
639 FifoSize
= PcdGet32 (PcdSerialExtendedTxFifoSize
);
643 Result
= NumberOfBytes
;
644 while (NumberOfBytes
!= 0) {
646 // Wait for the serial port to be ready, to make sure both the transmit FIFO
647 // and shift register empty.
649 while ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
)) != (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
));
652 // Fill then entire Tx FIFO
654 for (Index
= 0; Index
< FifoSize
&& NumberOfBytes
!= 0; Index
++, NumberOfBytes
--, Buffer
++) {
656 // Wait for the hardware flow control signal
658 while (!SerialPortWritable (SerialRegisterBase
));
661 // Write byte to the transmit buffer.
663 SerialPortWriteRegister (SerialRegisterBase
, R_UART_TXBUF
, *Buffer
);
670 Reads data from a serial device into a buffer.
672 @param Buffer Pointer to the data buffer to store the data read from the serial device.
673 @param NumberOfBytes Number of bytes to read from the serial device.
675 @retval 0 NumberOfBytes is 0.
676 @retval >0 The number of bytes read from the serial device.
677 If this value is less than NumberOfBytes, then the read operation failed.
684 IN UINTN NumberOfBytes
687 UINTN SerialRegisterBase
;
691 if (NULL
== Buffer
) {
695 SerialRegisterBase
= GetSerialRegisterBase ();
696 if (SerialRegisterBase
==0) {
700 Mcr
= (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
) & ~B_UART_MCR_RTS
);
702 for (Result
= 0; NumberOfBytes
-- != 0; Result
++, Buffer
++) {
704 // Wait for the serial port to have some data.
706 while ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & B_UART_LSR_RXRDY
) == 0) {
707 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
709 // Set RTS to let the peer send some data
711 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, (UINT8
)(Mcr
| B_UART_MCR_RTS
));
714 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
716 // Clear RTS to prevent peer from sending data
718 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, Mcr
);
722 // Read byte from the receive buffer.
724 *Buffer
= SerialPortReadRegister (SerialRegisterBase
, R_UART_RXBUF
);
732 Polls a serial device to see if there is any data waiting to be read.
734 Polls aserial device to see if there is any data waiting to be read.
735 If there is data waiting to be read from the serial device, then TRUE is returned.
736 If there is no data waiting to be read from the serial device, then FALSE is returned.
738 @retval TRUE Data is waiting to be read from the serial device.
739 @retval FALSE There is no data waiting to be read from the serial device.
748 UINTN SerialRegisterBase
;
750 SerialRegisterBase
= GetSerialRegisterBase ();
751 if (SerialRegisterBase
==0) {
756 // Read the serial port status
758 if ((SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
) & B_UART_LSR_RXRDY
) != 0) {
759 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
761 // Clear RTS to prevent peer from sending data
763 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
) & ~B_UART_MCR_RTS
));
768 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
770 // Set RTS to let the peer send some data
772 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, (UINT8
)(SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
) | B_UART_MCR_RTS
));
779 Sets the control bits on a serial device.
781 @param Control Sets the bits of Control that are settable.
783 @retval RETURN_SUCCESS The new control bits were set on the serial device.
784 @retval RETURN_UNSUPPORTED The serial device does not support this operation.
785 @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
790 SerialPortSetControl (
794 UINTN SerialRegisterBase
;
798 // First determine the parameter is invalid.
800 if ((Control
& (~(EFI_SERIAL_REQUEST_TO_SEND
| EFI_SERIAL_DATA_TERMINAL_READY
|
801 EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE
))) != 0) {
802 return RETURN_UNSUPPORTED
;
805 SerialRegisterBase
= GetSerialRegisterBase ();
806 if (SerialRegisterBase
==0) {
807 return RETURN_UNSUPPORTED
;
811 // Read the Modem Control Register.
813 Mcr
= SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
);
814 Mcr
&= (~(B_UART_MCR_DTRC
| B_UART_MCR_RTS
));
816 if ((Control
& EFI_SERIAL_DATA_TERMINAL_READY
) == EFI_SERIAL_DATA_TERMINAL_READY
) {
817 Mcr
|= B_UART_MCR_DTRC
;
820 if ((Control
& EFI_SERIAL_REQUEST_TO_SEND
) == EFI_SERIAL_REQUEST_TO_SEND
) {
821 Mcr
|= B_UART_MCR_RTS
;
825 // Write the Modem Control Register.
827 SerialPortWriteRegister (SerialRegisterBase
, R_UART_MCR
, Mcr
);
829 return RETURN_SUCCESS
;
833 Retrieve the status of the control bits on a serial device.
835 @param Control A pointer to return the current control signals from the serial device.
837 @retval RETURN_SUCCESS The control bits were read from the serial device.
838 @retval RETURN_UNSUPPORTED The serial device does not support this operation.
839 @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
844 SerialPortGetControl (
848 UINTN SerialRegisterBase
;
853 SerialRegisterBase
= GetSerialRegisterBase ();
854 if (SerialRegisterBase
==0) {
855 return RETURN_UNSUPPORTED
;
861 // Read the Modem Status Register.
863 Msr
= SerialPortReadRegister (SerialRegisterBase
, R_UART_MSR
);
865 if ((Msr
& B_UART_MSR_CTS
) == B_UART_MSR_CTS
) {
866 *Control
|= EFI_SERIAL_CLEAR_TO_SEND
;
869 if ((Msr
& B_UART_MSR_DSR
) == B_UART_MSR_DSR
) {
870 *Control
|= EFI_SERIAL_DATA_SET_READY
;
873 if ((Msr
& B_UART_MSR_RI
) == B_UART_MSR_RI
) {
874 *Control
|= EFI_SERIAL_RING_INDICATE
;
877 if ((Msr
& B_UART_MSR_DCD
) == B_UART_MSR_DCD
) {
878 *Control
|= EFI_SERIAL_CARRIER_DETECT
;
882 // Read the Modem Control Register.
884 Mcr
= SerialPortReadRegister (SerialRegisterBase
, R_UART_MCR
);
886 if ((Mcr
& B_UART_MCR_DTRC
) == B_UART_MCR_DTRC
) {
887 *Control
|= EFI_SERIAL_DATA_TERMINAL_READY
;
890 if ((Mcr
& B_UART_MCR_RTS
) == B_UART_MCR_RTS
) {
891 *Control
|= EFI_SERIAL_REQUEST_TO_SEND
;
894 if (PcdGetBool (PcdSerialUseHardwareFlowControl
)) {
895 *Control
|= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE
;
899 // Read the Line Status Register.
901 Lsr
= SerialPortReadRegister (SerialRegisterBase
, R_UART_LSR
);
903 if ((Lsr
& (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
)) == (B_UART_LSR_TEMT
| B_UART_LSR_TXRDY
)) {
904 *Control
|= EFI_SERIAL_OUTPUT_BUFFER_EMPTY
;
907 if ((Lsr
& B_UART_LSR_RXRDY
) == 0) {
908 *Control
|= EFI_SERIAL_INPUT_BUFFER_EMPTY
;
911 return RETURN_SUCCESS
;
915 Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
916 data bits, and stop bits on a serial device.
918 @param BaudRate The requested baud rate. A BaudRate value of 0 will use the
919 device's default interface speed.
920 On output, the value actually set.
921 @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the
922 serial interface. A ReceiveFifoDepth value of 0 will use
923 the device's default FIFO depth.
924 On output, the value actually set.
925 @param Timeout The requested time out for a single character in microseconds.
926 This timeout applies to both the transmit and receive side of the
927 interface. A Timeout value of 0 will use the device's default time
929 On output, the value actually set.
930 @param Parity The type of parity to use on this serial device. A Parity value of
931 DefaultParity will use the device's default parity value.
932 On output, the value actually set.
933 @param DataBits The number of data bits to use on the serial device. A DataBits
934 vaule of 0 will use the device's default data bit setting.
935 On output, the value actually set.
936 @param StopBits The number of stop bits to use on this serial device. A StopBits
937 value of DefaultStopBits will use the device's default number of
939 On output, the value actually set.
941 @retval RETURN_SUCCESS The new attributes were set on the serial device.
942 @retval RETURN_UNSUPPORTED The serial device does not support this operation.
943 @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value.
944 @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly.
949 SerialPortSetAttributes (
950 IN OUT UINT64
*BaudRate
,
951 IN OUT UINT32
*ReceiveFifoDepth
,
952 IN OUT UINT32
*Timeout
,
953 IN OUT EFI_PARITY_TYPE
*Parity
,
954 IN OUT UINT8
*DataBits
,
955 IN OUT EFI_STOP_BITS_TYPE
*StopBits
958 UINTN SerialRegisterBase
;
959 UINT32 SerialBaudRate
;
966 SerialRegisterBase
= GetSerialRegisterBase ();
967 if (SerialRegisterBase
==0) {
968 return RETURN_UNSUPPORTED
;
972 // Check for default settings and fill in actual values.
974 if (*BaudRate
== 0) {
975 *BaudRate
= PcdGet32 (PcdSerialBaudRate
);
977 SerialBaudRate
= (UINT32
) *BaudRate
;
979 if (*DataBits
== 0) {
980 LcrData
= (UINT8
) (PcdGet8 (PcdSerialLineControl
) & 0x3);
981 *DataBits
= LcrData
+ 5;
983 if ((*DataBits
< 5) || (*DataBits
> 8)) {
984 return RETURN_INVALID_PARAMETER
;
989 LcrData
= (UINT8
) (*DataBits
- (UINT8
) 5);
992 if (*Parity
== DefaultParity
) {
993 LcrParity
= (UINT8
) ((PcdGet8 (PcdSerialLineControl
) >> 3) & 0x7);
1000 *Parity
= EvenParity
;
1004 *Parity
= OddParity
;
1008 *Parity
= SpaceParity
;
1012 *Parity
= MarkParity
;
1041 return RETURN_INVALID_PARAMETER
;
1045 if (*StopBits
== DefaultStopBits
) {
1046 LcrStop
= (UINT8
) ((PcdGet8 (PcdSerialLineControl
) >> 2) & 0x1);
1049 *StopBits
= OneStopBit
;
1053 if (*DataBits
== 5) {
1054 *StopBits
= OneFiveStopBits
;
1056 *StopBits
= TwoStopBits
;
1064 switch (*StopBits
) {
1069 case OneFiveStopBits
:
1075 return RETURN_INVALID_PARAMETER
;
1080 // Calculate divisor for baud generator
1081 // Ref_Clk_Rate / Baud_Rate / 16
1083 Divisor
= PcdGet32 (PcdSerialClockRate
) / (SerialBaudRate
* 16);
1084 if ((PcdGet32 (PcdSerialClockRate
) % (SerialBaudRate
* 16)) >= SerialBaudRate
* 8) {
1089 // Configure baud rate
1091 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, B_UART_LCR_DLAB
);
1092 SerialPortWriteRegister (SerialRegisterBase
, R_UART_BAUD_HIGH
, (UINT8
) (Divisor
>> 8));
1093 SerialPortWriteRegister (SerialRegisterBase
, R_UART_BAUD_LOW
, (UINT8
) (Divisor
& 0xff));
1096 // Clear DLAB and configure Data Bits, Parity, and Stop Bits.
1097 // Strip reserved bits from line control value
1099 Lcr
= (UINT8
) ((LcrParity
<< 3) | (LcrStop
<< 2) | LcrData
);
1100 SerialPortWriteRegister (SerialRegisterBase
, R_UART_LCR
, (UINT8
) (Lcr
& 0x3F));
1102 return RETURN_SUCCESS
;