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1 /// @file
2 /// Low level IPF routines used by the debug support driver
3 ///
4 /// Copyright (c) 2006 - 2008, Intel Corporation
5 /// All rights reserved. This program and the accompanying materials
6 /// are licensed and made available under the terms and conditions of the BSD License
7 /// which accompanies this distribution. The full text of the license may be found at
8 /// http://opensource.org/licenses/bsd-license.php
9 ///
10 /// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 /// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 ///
13 /// Module Name: AsmFuncs.s
14 ///
15 ///
16
17
18 #include "Common.i"
19 #include "Ds64Macros.i"
20
21 .globl PatchSaveBuffer
22 .globl IpfContextBuf
23 .globl CommonHandler
24 .globl ExternalInterruptCount
25
26
27 /////////////////////////////////////////////
28 //
29 // Name:
30 // InstructionCacheFlush
31 //
32 // Description:
33 // Flushes instruction cache for specified number of bytes
34 //
35 .globl InstructionCacheFlush
36 .proc InstructionCacheFlush
37 .align 32
38 InstructionCacheFlush::
39 { .mii
40 alloc r3=2, 0, 0, 0
41 cmp4.leu p0,p6=32, r33;;
42 (p6) mov r33=32;;
43 }
44 { .mii
45 nop.m 0
46 zxt4 r29=r33;;
47 dep.z r30=r29, 0, 5;;
48 }
49 { .mii
50 cmp4.eq p0,p7=r0, r30
51 shr.u r28=r29, 5;;
52 (p7) adds r28=1, r28;;
53 }
54 { .mii
55 nop.m 0
56 shl r27=r28, 5;;
57 zxt4 r26=r27;;
58 }
59 { .mfb
60 add r31=r26, r32
61 nop.f 0
62 nop.b 0
63 }
64 LoopBack: // $L143:
65 { .mii
66 fc r32
67 adds r32=32, r32;;
68 cmp.ltu p14,p15=r32, r31
69 }
70 { .mfb
71 nop.m 0
72 nop.f 0
73 //(p14) br.cond.dptk.few $L143#;;
74 (p14) br.cond.dptk.few LoopBack;;
75 }
76 { .mmi
77 sync.i;;
78 srlz.i
79 nop.i 0;;
80 }
81 { .mfb
82 nop.m 0
83 nop.f 0
84 br.ret.sptk.few b0;;
85 }
86 .endp InstructionCacheFlush
87
88
89 /////////////////////////////////////////////
90 //
91 // Name:
92 // ChainHandler
93 //
94 // Description:
95 // Chains an interrupt handler
96 //
97 // The purpose of this function is to enable chaining of the external interrupt.
98 // Since there's no clean SAL abstraction for doing this, we must do it
99 // surreptitiously.
100 //
101 // The reserved IVT entry at offset 0x3400 is coopted for use by this handler.
102 // According to Itanium architecture, it is reserved. Strictly speaking, this is
103 // not safe, as we're cheating and violating the Itanium architecture. However,
104 // as long as we're the only ones cheating, we should be OK. Without hooks in
105 // the SAL to enable IVT management, there aren't many good options.
106 //
107 // The strategy is to replace the first bundle of the external interrupt handler
108 // with our own that will branch into a piece of code we've supplied and located
109 // in the reserved IVT entry. Only the first bundle of the external interrupt
110 // IVT entry is modified.
111 //
112 // The original bundle is moved and relocated to space
113 // allocated within the reserved IVT entry. The next bundle following is
114 // is generated to go a hard coded branch back to the second bundle of the
115 // external interrupt IVT entry just in case the first bundle had no branch.
116 //
117 // Our new code will execute our handler, and then fall through to the
118 // original bundle after restoring all context appropriately.
119 //
120 // The following is a representation of what the IVT memory map looks like with
121 // our chained handler installed:
122 //
123 //
124 //
125 //
126 //
127 // This IVT entry is Failsafe bundle
128 // reserved by the
129 // Itanium architecture Original bundle 0
130 // and is used for
131 // for locating our
132 // handler and the
133 // original bundle Patch code...
134 // zero of the ext
135 // interrupt handler
136 //
137 // RSVD (3400) Unused
138 //
139 //
140 //
141 //
142 //
143 //
144 //
145 //
146 //
147 //
148 //
149 //
150 // EXT_INT (3000) Bundle 0 Bundle zero - This one is
151 // modified, all other bundles
152 // in the EXT_INT entry are
153 // untouched.
154 //
155 //
156 // Arguments:
157 //
158 // Returns:
159 //
160 // Notes:
161 //
162 //
163 .globl ChainHandler
164 .proc ChainHandler
165 ChainHandler:
166
167 NESTED_SETUP( 0,2+3,3,0 )
168
169 mov r8=1 // r8 = success
170 mov r2=cr.iva;;
171 //
172 // NOTE: There's a potential hazard here in that we're simply stealing a bunch of
173 // bundles (memory) from the IVT and assuming there's no catastrophic side effect.
174 //
175 // First, save IVT area we're taking over with the patch so we can restore it later
176 //
177 addl out0=PATCH_ENTRY_OFFSET, r2 // out0 = source buffer
178 movl out1=PatchSaveBuffer // out1 = destination buffer
179 mov out2=0x40;; // out2 = number of bundles to copy... save entire IDT entry
180 br.call.sptk.few b0 = CopyBundles
181
182 // Next, copy the patch code into the IVT
183 movl out0=PatchCode // out0 = source buffer of patch code
184 addl out1=PATCH_OFFSET, r2 // out1 = destination buffer - in IVT
185 mov out2=PATCH_CODE_SIZE;;
186 shr out2=out2, 4;; // out2 = number of bundles to copy
187 br.call.sptk.few b0 = CopyBundles
188
189
190 // copy original bundle 0 from the external interrupt handler to the
191 // appropriate place in the reserved IVT interrupt slot
192 addl out0=EXT_INT_ENTRY_OFFSET, r2 // out0 = source buffer
193 addl out1=RELOCATED_EXT_INT, r2 // out1 = destination buffer - in reserved IVT
194 mov out2=1;; // out2 = copy 1 bundle
195 br.call.sptk.few b0 = CopyBundles
196
197 // Now relocate it there because it very likely had a branch instruction that
198 // that must now be fixed up.
199 addl out0=RELOCATED_EXT_INT, r2 // out0 = new runtime address of bundle - in reserved IVT
200 addl out1=EXT_INT_ENTRY_OFFSET, r2;;// out1 = IP address of previous location
201 mov out2=out0;; // out2 = IP address of new location
202 br.call.sptk.few b0 = RelocateBundle
203
204 // Now copy into the failsafe branch into the next bundle just in case
205 // the original ext int bundle 0 bundle did not contain a branch instruction
206 movl out0=FailsafeBranch // out0 = source buffer
207 addl out1=FAILSAFE_BRANCH_OFFSET, r2 // out1 = destination buffer - in reserved IVT
208 mov out2=1;; // out2 = copy 1 bundle
209 br.call.sptk.few b0 = CopyBundles
210
211 // Last, copy in our replacement for the external interrupt IVT entry bundle 0
212 movl out0=PatchCodeNewBun0 // out0 = source buffer - our replacement bundle 0
213 addl out1=EXT_INT_ENTRY_OFFSET, r2 // out1 = destination buffer - bundle 0 of External interrupt entry
214 mov out2=1;; // out2 = copy 1 bundle
215 br.call.sptk.few b0 = CopyBundles
216
217 ChainHandlerDone:
218 NESTED_RETURN
219
220 .endp ChainHandler
221
222
223 /////////////////////////////////////////////
224 //
225 // Name:
226 // UnchainHandler
227 //
228 // Description:
229 // Unchains an interrupt handler
230 //
231 // Arguments:
232 //
233 // Returns:
234 //
235 // Notes:
236 //
237 //
238 .globl UnchainHandler
239 .proc UnchainHandler
240
241 UnchainHandler:
242
243 NESTED_SETUP( 0,2+3,3,0 )
244
245 mov r8=1 // r8 = success
246 mov r2=cr.iva;; // r2 = interrupt vector address
247
248 // First copy original Ext Int bundle 0 back to it's proper home...
249 addl out0=RELOCATED_EXT_INT, r2 // out0 = source - in reserved IVT
250 addl out1=EXT_INT_ENTRY_OFFSET, r2 // out1 = destination buffer - first bundle of Ext Int entry
251 mov out2=1;; // out2 = copy 1 bundle
252 br.call.sptk.few b0 = CopyBundles
253
254 // Now, relocate it again...
255 addl out0=EXT_INT_ENTRY_OFFSET, r2 // out1 = New runtime address
256 addl out1=RELOCATED_EXT_INT, r2;; // out0 = IP address of previous location
257 mov out2=out0;; // out2 = IP address of new location
258 br.call.sptk.few b0 = RelocateBundle
259
260 // Last, restore the patch area
261 movl out0=PatchSaveBuffer // out0 = source buffer
262 addl out1=PATCH_ENTRY_OFFSET, r2 // out1 = destination buffer
263 mov out2=0x40;; // out2 = number of bundles to copy... save entire IDT entry
264 br.call.sptk.few b0 = CopyBundles
265
266 UnchainHandlerDone:
267 NESTED_RETURN
268
269 .endp UnchainHandler
270
271
272 /////////////////////////////////////////////
273 //
274 // Name:
275 // CopyBundles
276 //
277 // Description:
278 // Copies instruction bundles - flushes icache as necessary
279 //
280 // Arguments:
281 // in0 - Bundle source
282 // in1 - Bundle destination
283 // in2 - Bundle count
284 //
285 // Returns:
286 //
287 // Notes:
288 // This procedure is a leaf routine
289 //
290 .proc CopyBundles
291
292 CopyBundles:
293
294 NESTED_SETUP(3,2+1,0,0)
295
296 shl in2=in2, 1;; // in2 = count of 8 byte blocks to copy
297
298 CopyBundlesLoop:
299
300 cmp.eq p14, p15 = 0, in2;; // Check if done
301 (p14) br.sptk.few CopyBundlesDone;;
302
303 ld8 loc2=[in0], 0x8;; // loc2 = source bytes
304 st8 [in1]=loc2;; // [in1] = destination bytes
305 fc in1;; // Flush instruction cache
306 sync.i;; // Ensure local and remote data/inst caches in sync
307 srlz.i;; // Ensure sync has been observed
308 add in1=0x8, in1;; // in1 = next destination
309 add in2=-1, in2;; // in2 = decrement 8 bytes blocks to copy
310 br.sptk.few CopyBundlesLoop;;
311
312 CopyBundlesDone:
313 NESTED_RETURN
314
315 .endp CopyBundles
316
317
318 /////////////////////////////////////////////
319 //
320 // Name:
321 // RelocateBundle
322 //
323 // Description:
324 // Relocates an instruction bundle by updating any ip-relative branch instructions.
325 //
326 // Arguments:
327 // in0 - Runtime address of bundle
328 // in1 - IP address of previous location of bundle
329 // in2 - IP address of new location of bundle
330 //
331 // Returns:
332 // in0 - 1 if successful or 0 if unsuccessful
333 //
334 // Notes:
335 // This routine examines all slots in the given bundle that are destined for the
336 // branch execution unit. If any of these slots contain an IP-relative branch
337 // namely instructions B1, B2, B3, or B6, the slot is fixed-up with a new relative
338 // address. Errors can occur if a branch cannot be reached.
339 //
340 .proc RelocateBundle
341
342 RelocateBundle:
343
344 NESTED_SETUP(3,2+4,3,0)
345
346 mov loc2=SLOT0 // loc2 = slot index
347 mov loc5=in0;; // loc5 = runtime address of bundle
348 mov in0=1;; // in0 = success
349
350 RelocateBundleNextSlot:
351
352 cmp.ge p14, p15 = SLOT2, loc2;; // Check if maximum slot
353 (p15) br.sptk.few RelocateBundleDone
354
355 mov out0=loc5;; // out0 = runtime address of bundle
356 br.call.sptk.few b0 = GetTemplate
357 mov loc3=out0;; // loc3 = instruction template
358 mov out0=loc5 // out0 = runtime address of bundle
359 mov out1=loc2;; // out1 = instruction slot number
360 br.call.sptk.few b0 = GetSlot
361 mov loc4=out0;; // loc4 = instruction encoding
362 mov out0=loc4 // out0 = instuction encoding
363 mov out1=loc2 // out1 = instruction slot number
364 mov out2=loc3;; // out2 = instruction template
365 br.call.sptk.few b0 = IsSlotBranch
366 cmp.eq p14, p15 = 1, out0;; // Check if branch slot
367 (p15) add loc2=1,loc2 // Increment slot
368 (p15) br.sptk.few RelocateBundleNextSlot
369 mov out0=loc4 // out0 = instuction encoding
370 mov out1=in1 // out1 = IP address of previous location
371 mov out2=in2;; // out2 = IP address of new location
372 br.call.sptk.few b0 = RelocateSlot
373 cmp.eq p14, p15 = 1, out1;; // Check if relocated slot
374 (p15) mov in0=0 // in0 = failure
375 (p15) br.sptk.few RelocateBundleDone
376 mov out2=out0;; // out2 = instruction encoding
377 mov out0=loc5 // out0 = runtime address of bundle
378 mov out1=loc2;; // out1 = instruction slot number
379 br.call.sptk.few b0 = SetSlot
380 add loc2=1,loc2;; // Increment slot
381 br.sptk.few RelocateBundleNextSlot
382
383 RelocateBundleDone:
384 NESTED_RETURN
385
386 .endp RelocateBundle
387
388
389 /////////////////////////////////////////////
390 //
391 // Name:
392 // RelocateSlot
393 //
394 // Description:
395 // Relocates an instruction bundle by updating any ip-relative branch instructions.
396 //
397 // Arguments:
398 // in0 - Instruction encoding (41-bits, right justified)
399 // in1 - IP address of previous location of bundle
400 // in2 - IP address of new location of bundle
401 //
402 // Returns:
403 // in0 - Instruction encoding (41-bits, right justified)
404 // in1 - 1 if successful otherwise 0
405 //
406 // Notes:
407 // This procedure is a leaf routine
408 //
409 .proc RelocateSlot
410
411 RelocateSlot:
412 NESTED_SETUP(3,2+5,0,0)
413 extr.u loc2=in0, 37, 4;; // loc2 = instruction opcode
414 cmp.eq p14, p15 = 4, loc2;; // IP-relative branch (B1) or
415 // IP-relative counted branch (B2)
416 (p15) cmp.eq p14, p15 = 5, loc2;; // IP-relative call (B3)
417 (p15) cmp.eq p14, p15 = 7, loc2;; // IP-relative predict (B6)
418 (p15) mov in1=1 // Instruction did not need to be reencoded
419 (p15) br.sptk.few RelocateSlotDone
420 tbit.nz p14, p15 = in0, 36;; // put relative offset sign bit in p14
421 extr.u loc2=in0, 13, 20;; // loc2 = relative offset in instruction
422 (p14) movl loc3=0xfffffffffff00000;; // extend sign
423 (p14) or loc2=loc2, loc3;;
424 shl loc2=loc2,4;; // convert to byte offset instead of bundle offset
425 add loc3=loc2, in1;; // loc3 = physical address of branch target
426 (p14) sub loc2=r0,loc2;; // flip sign in loc2 if offset is negative
427 sub loc4=loc3,in2;; // loc4 = relative offset from new ip to branch target
428 cmp.lt p15, p14 = 0, loc4;; // get new sign bit
429 (p14) sub loc5=r0,loc4 // get absolute value of offset
430 (p15) mov loc5=loc4;;
431 movl loc6=0x0FFFFFF;; // maximum offset in bytes for ip-rel branch
432 cmp.gt p14, p15 = loc5, loc6;; // check to see we're not out of range for an ip-relative branch
433 (p14) br.sptk.few RelocateSlotError
434 cmp.lt p15, p14 = 0, loc4;; // store sign in p14 again
435 (p14) dep in0=-1,in0,36,1 // store sign bit in instruction
436 (p15) dep in0=0,in0,36,1
437 shr loc4=loc4, 4;; // convert back to bundle offset
438 dep in0=loc4,in0,13,16;; // put first 16 bits of new offset into instruction
439 shr loc4=loc4,16;;
440 dep in0=loc4,in0,13+16,4 // put last 4 bits of new offset into instruction
441 mov in1=1;; // in1 = success
442 br.sptk.few RelocateSlotDone;;
443
444 RelocateSlotError:
445 mov in1=0;; // in1 = failure
446
447 RelocateSlotDone:
448 NESTED_RETURN
449
450 .endp RelocateSlot
451
452
453 /////////////////////////////////////////////
454 //
455 // Name:
456 // IsSlotBranch
457 //
458 // Description:
459 // Determines if the given instruction is a branch instruction.
460 //
461 // Arguments:
462 // in0 - Instruction encoding (41-bits, right justified)
463 // in1 - Instruction slot number
464 // in2 - Bundle template
465 //
466 // Returns:
467 // in0 - 1 if branch or 0 if not branch
468 //
469 // Notes:
470 // This procedure is a leaf routine
471 //
472 // IsSlotBranch recognizes all branch instructions by looking at the provided template.
473 // The instruction encoding is only passed to this routine for future expansion.
474 //
475 .proc IsSlotBranch
476
477 IsSlotBranch:
478
479 NESTED_SETUP (3,2+0,0,0)
480
481 mov in0=1;; // in0 = 1 which destroys the instruction
482 andcm in2=in2,in0;; // in2 = even template to reduce compares
483 mov in0=0;; // in0 = not a branch
484 cmp.eq p14, p15 = 0x16, in2;; // Template 0x16 is BBB
485 (p14) br.sptk.few IsSlotBranchTrue
486 cmp.eq p14, p15 = SLOT0, in1;; // Slot 0 has no other possiblities
487 (p14) br.sptk.few IsSlotBranchDone
488 cmp.eq p14, p15 = 0x12, in2;; // Template 0x12 is MBB
489 (p14) br.sptk.few IsSlotBranchTrue
490 cmp.eq p14, p15 = SLOT1, in1;; // Slot 1 has no other possiblities
491 (p14) br.sptk.few IsSlotBranchDone
492 cmp.eq p14, p15 = 0x10, in2;; // Template 0x10 is MIB
493 (p14) br.sptk.few IsSlotBranchTrue
494 cmp.eq p14, p15 = 0x18, in2;; // Template 0x18 is MMB
495 (p14) br.sptk.few IsSlotBranchTrue
496 cmp.eq p14, p15 = 0x1C, in2;; // Template 0x1C is MFB
497 (p14) br.sptk.few IsSlotBranchTrue
498 br.sptk.few IsSlotBranchDone
499
500 IsSlotBranchTrue:
501 mov in0=1;; // in0 = branch
502
503 IsSlotBranchDone:
504 NESTED_RETURN
505
506 .endp IsSlotBranch
507
508
509 /////////////////////////////////////////////
510 //
511 // Name:
512 // GetTemplate
513 //
514 // Description:
515 // Retrieves the instruction template for an instruction bundle
516 //
517 // Arguments:
518 // in0 - Runtime address of bundle
519 //
520 // Returns:
521 // in0 - Instruction template (5-bits, right-justified)
522 //
523 // Notes:
524 // This procedure is a leaf routine
525 //
526 .proc GetTemplate
527
528 GetTemplate:
529
530 NESTED_SETUP (1,2+2,0,0)
531
532 ld8 loc2=[in0], 0x8 // loc2 = first 8 bytes of branch bundle
533 movl loc3=MASK_0_4;; // loc3 = template mask
534 and loc2=loc2,loc3;; // loc2 = template, right justified
535 mov in0=loc2;; // in0 = template, right justified
536
537 NESTED_RETURN
538
539 .endp GetTemplate
540
541
542 /////////////////////////////////////////////
543 //
544 // Name:
545 // GetSlot
546 //
547 // Description:
548 // Gets the instruction encoding for an instruction slot and bundle
549 //
550 // Arguments:
551 // in0 - Runtime address of bundle
552 // in1 - Instruction slot (either 0, 1, or 2)
553 //
554 // Returns:
555 // in0 - Instruction encoding (41-bits, right justified)
556 //
557 // Notes:
558 // This procedure is a leaf routine
559 //
560 // Slot0 - [in0 + 0x8] Bits 45-5
561 // Slot1 - [in0 + 0x8] Bits 63-46 and [in0] Bits 22-0
562 // Slot2 - [in0] Bits 63-23
563 //
564 .proc GetSlot
565
566 GetSlot:
567 NESTED_SETUP (2,2+3,0,0)
568
569 ld8 loc2=[in0], 0x8;; // loc2 = first 8 bytes of branch bundle
570 ld8 loc3=[in0];; // loc3 = second 8 bytes of branch bundle
571 cmp.eq p14, p15 = 2, in1;; // check if slot 2 specified
572 (p14) br.cond.sptk.few GetSlot2;; // get slot 2
573 cmp.eq p14, p15 = 1, in1;; // check if slot 1 specified
574 (p14) br.cond.sptk.few GetSlot1;; // get slot 1
575
576 GetSlot0:
577 extr.u in0=loc2, 5, 45 // in0 = extracted slot 0
578 br.sptk.few GetSlotDone;;
579
580 GetSlot1:
581 extr.u in0=loc2, 46, 18 // in0 = bits 63-46 of loc2 right-justified
582 extr.u loc4=loc3, 0, 23;; // loc4 = bits 22-0 of loc3 right-justified
583 dep in0=loc4, in0, 18, 15;;
584 shr.u loc4=loc4,15;;
585 dep in0=loc4, in0, 33, 8;; // in0 = extracted slot 1
586 br.sptk.few GetSlotDone;;
587
588 GetSlot2:
589 extr.u in0=loc3, 23, 41;; // in0 = extracted slot 2
590
591 GetSlotDone:
592 NESTED_RETURN
593
594 .endp GetSlot
595
596
597 /////////////////////////////////////////////
598 //
599 // Name:
600 // SetSlot
601 //
602 // Description:
603 // Sets the instruction encoding for an instruction slot and bundle
604 //
605 // Arguments:
606 // in0 - Runtime address of bundle
607 // in1 - Instruction slot (either 0, 1, or 2)
608 // in2 - Instruction encoding (41-bits, right justified)
609 //
610 // Returns:
611 //
612 // Notes:
613 // This procedure is a leaf routine
614 //
615 .proc SetSlot
616
617 SetSlot:
618 NESTED_SETUP (3,2+3,0,0)
619
620 ld8 loc2=[in0], 0x8;; // loc2 = first 8 bytes of bundle
621 ld8 loc3=[in0];; // loc3 = second 8 bytes of bundle
622 cmp.eq p14, p15 = 2, in1;; // check if slot 2 specified
623 (p14) br.cond.sptk.few SetSlot2;; // set slot 2
624 cmp.eq p14, p15 = 1, in1;; // check if slot 1 specified
625 (p14) br.cond.sptk.few SetSlot1;; // set slot 1
626
627 SetSlot0:
628 dep loc2=0, loc2, 5, 41;; // remove old instruction from slot 0
629 shl loc4=in2, 5;; // loc4 = new instruction ready to be inserted
630 or loc2=loc2, loc4;; // loc2 = updated first 8 bytes of bundle
631 add loc4=0x8,in0;; // loc4 = address to store first 8 bytes of bundle
632 st8 [loc4]=loc2 // [loc4] = updated bundle
633 br.sptk.few SetSlotDone;;
634 ;;
635
636 SetSlot1:
637 dep loc2=0, loc2, 46, 18 // remove old instruction from slot 1
638 dep loc3=0, loc3, 0, 23;;
639 shl loc4=in2, 46;; // loc4 = partial instruction ready to be inserted
640 or loc2=loc2, loc4;; // loc2 = updated first 8 bytes of bundle
641 add loc4=0x8,in0;; // loc4 = address to store first 8 bytes of bundle
642 st8 [loc4]=loc2;; // [loc4] = updated bundle
643 shr.u loc4=in2, 18;; // loc4 = partial instruction ready to be inserted
644 or loc3=loc3, loc4;; // loc3 = updated second 8 bytes of bundle
645 st8 [in0]=loc3;; // [in0] = updated bundle
646 br.sptk.few SetSlotDone;;
647
648 SetSlot2:
649 dep loc3=0, loc3, 23, 41;; // remove old instruction from slot 2
650 shl loc4=in2, 23;; // loc4 = instruction ready to be inserted
651 or loc3=loc3, loc4;; // loc3 = updated second 8 bytes of bundle
652 st8 [in0]=loc3;; // [in0] = updated bundle
653
654 SetSlotDone:
655
656 NESTED_RETURN
657 .endp SetSlot
658
659
660 /////////////////////////////////////////////
661 //
662 // Name:
663 // GetIva
664 //
665 // Description:
666 // C callable function to obtain the current value of IVA
667 //
668 // Returns:
669 // Current value if IVA
670
671 .globl GetIva
672 .proc GetIva
673 GetIva:
674 mov r8=cr2;;
675 br.ret.sptk.many b0
676
677 .endp GetIva
678
679
680 /////////////////////////////////////////////
681 //
682 // Name:
683 // ProgramInterruptFlags
684 //
685 // Description:
686 // C callable function to enable/disable interrupts
687 //
688 // Returns:
689 // Previous state of psr.ic
690 //
691 .globl ProgramInterruptFlags
692 .proc ProgramInterruptFlags
693 ProgramInterruptFlags:
694 alloc loc0=1,2,0,0;;
695 mov loc0=psr
696 mov loc1=0x6000;;
697 and r8=loc0, loc1 // obtain current psr.ic and psr.i state
698 and in0=in0, loc1 // insure no extra bits set in input
699 andcm loc0=loc0,loc1;; // clear original psr.i and psr.ic
700 or loc0=loc0,in0;; // OR in new psr.ic value
701 mov psr.l=loc0;; // write new psr
702 srlz.d
703 br.ret.sptk.many b0 // return
704
705 .endp ProgramInterruptFlags
706
707
708 /////////////////////////////////////////////
709 //
710 // Name:
711 // SpillContext
712 //
713 // Description:
714 // Saves system context to context record.
715 //
716 // Arguments:
717 // in0 = 512 byte aligned context record address
718 // in1 = original B0
719 // in2 = original ar.bsp
720 // in3 = original ar.bspstore
721 // in4 = original ar.rnat
722 // in5 = original ar.pfs
723 //
724 // Notes:
725 // loc0 - scratch
726 // loc1 - scratch
727 // loc2 - temporary application unat storage
728 // loc3 - temporary exception handler unat storage
729
730 .proc SpillContext
731
732 SpillContext:
733 alloc loc0=6,4,0,0;; // alloc 6 input, 4 locals, 0 outs
734 mov loc2=ar.unat;; // save application context unat (spilled later)
735 mov ar.unat=r0;; // set UNAT=0
736 st8.spill [in0]=r0,8;;
737 st8.spill [in0]=r1,8;; // save R1 - R31
738 st8.spill [in0]=r2,8;;
739 st8.spill [in0]=r3,8;;
740 st8.spill [in0]=r4,8;;
741 st8.spill [in0]=r5,8;;
742 st8.spill [in0]=r6,8;;
743 st8.spill [in0]=r7,8;;
744 st8.spill [in0]=r8,8;;
745 st8.spill [in0]=r9,8;;
746 st8.spill [in0]=r10,8;;
747 st8.spill [in0]=r11,8;;
748 st8.spill [in0]=r12,8;;
749 st8.spill [in0]=r13,8;;
750 st8.spill [in0]=r14,8;;
751 st8.spill [in0]=r15,8;;
752 st8.spill [in0]=r16,8;;
753 st8.spill [in0]=r17,8;;
754 st8.spill [in0]=r18,8;;
755 st8.spill [in0]=r19,8;;
756 st8.spill [in0]=r20,8;;
757 st8.spill [in0]=r21,8;;
758 st8.spill [in0]=r22,8;;
759 st8.spill [in0]=r23,8;;
760 st8.spill [in0]=r24,8;;
761 st8.spill [in0]=r25,8;;
762 st8.spill [in0]=r26,8;;
763 st8.spill [in0]=r27,8;;
764 st8.spill [in0]=r28,8;;
765 st8.spill [in0]=r29,8;;
766 st8.spill [in0]=r30,8;;
767 st8.spill [in0]=r31,8;;
768 mov loc3=ar.unat;; // save debugger context unat (spilled later)
769 stf.spill [in0]=f2,16;; // save f2 - f31
770 stf.spill [in0]=f3,16;;
771 stf.spill [in0]=f4,16;;
772 stf.spill [in0]=f5,16;;
773 stf.spill [in0]=f6,16;;
774 stf.spill [in0]=f7,16;;
775 stf.spill [in0]=f8,16;;
776 stf.spill [in0]=f9,16;;
777 stf.spill [in0]=f10,16;;
778 stf.spill [in0]=f11,16;;
779 stf.spill [in0]=f12,16;;
780 stf.spill [in0]=f13,16;;
781 stf.spill [in0]=f14,16;;
782 stf.spill [in0]=f15,16;;
783 stf.spill [in0]=f16,16;;
784 stf.spill [in0]=f17,16;;
785 stf.spill [in0]=f18,16;;
786 stf.spill [in0]=f19,16;;
787 stf.spill [in0]=f20,16;;
788 stf.spill [in0]=f21,16;;
789 stf.spill [in0]=f22,16;;
790 stf.spill [in0]=f23,16;;
791 stf.spill [in0]=f24,16;;
792 stf.spill [in0]=f25,16;;
793 stf.spill [in0]=f26,16;;
794 stf.spill [in0]=f27,16;;
795 stf.spill [in0]=f28,16;;
796 stf.spill [in0]=f29,16;;
797 stf.spill [in0]=f30,16;;
798 stf.spill [in0]=f31,16;;
799 mov loc0=pr;; // save predicates
800 st8.spill [in0]=loc0,8;;
801 st8.spill [in0]=in1,8;; // save b0 - b7... in1 already equals saved b0
802 mov loc0=b1;;
803 st8.spill [in0]=loc0,8;;
804 mov loc0=b2;;
805 st8.spill [in0]=loc0,8;;
806 mov loc0=b3;;
807 st8.spill [in0]=loc0,8;;
808 mov loc0=b4;;
809 st8.spill [in0]=loc0,8;;
810 mov loc0=b5;;
811 st8.spill [in0]=loc0,8;;
812 mov loc0=b6;;
813 st8.spill [in0]=loc0,8;;
814 mov loc0=b7;;
815 st8.spill [in0]=loc0,8;;
816 mov loc0=ar.rsc;; // save ar.rsc
817 st8.spill [in0]=loc0,8;;
818 st8.spill [in0]=in2,8;; // save ar.bsp (in2)
819 st8.spill [in0]=in3,8;; // save ar.bspstore (in3)
820 st8.spill [in0]=in4,8;; // save ar.rnat (in4)
821 mov loc0=ar.fcr;; // save ar.fcr (ar21 - IA32 floating-point control register)
822 st8.spill [in0]=loc0,8;;
823 mov loc0=ar.eflag;; // save ar.eflag (ar24)
824 st8.spill [in0]=loc0,8;;
825 mov loc0=ar.csd;; // save ar.csd (ar25 - ia32 CS descriptor)
826 st8.spill [in0]=loc0,8;;
827 mov loc0=ar.ssd;; // save ar.ssd (ar26 - ia32 ss descriptor)
828 st8.spill [in0]=loc0,8;;
829 mov loc0=ar.cflg;; // save ar.cflg (ar27 - ia32 cr0 and cr4)
830 st8.spill [in0]=loc0,8;;
831 mov loc0=ar.fsr;; // save ar.fsr (ar28 - ia32 floating-point status register)
832 st8.spill [in0]=loc0,8;;
833 mov loc0=ar.fir;; // save ar.fir (ar29 - ia32 floating-point instruction register)
834 st8.spill [in0]=loc0,8;;
835 mov loc0=ar.fdr;; // save ar.fdr (ar30 - ia32 floating-point data register)
836 st8.spill [in0]=loc0,8;;
837 mov loc0=ar.ccv;; // save ar.ccv
838 st8.spill [in0]=loc0,8;;
839 st8.spill [in0]=loc2,8;; // save ar.unat (saved to loc2 earlier)
840 mov loc0=ar.fpsr;; // save floating point status register
841 st8.spill [in0]=loc0,8;;
842 st8.spill [in0]=in5,8;; // save ar.pfs
843 mov loc0=ar.lc;; // save ar.lc
844 st8.spill [in0]=loc0,8;;
845 mov loc0=ar.ec;; // save ar.ec
846 st8.spill [in0]=loc0,8;;
847
848 // save control registers
849 mov loc0=cr.dcr;; // save dcr
850 st8.spill [in0]=loc0,8;;
851 mov loc0=cr.itm;; // save itm
852 st8.spill [in0]=loc0,8;;
853 mov loc0=cr.iva;; // save iva
854 st8.spill [in0]=loc0,8;;
855 mov loc0=cr.pta;; // save pta
856 st8.spill [in0]=loc0,8;;
857 mov loc0=cr.ipsr;; // save ipsr
858 st8.spill [in0]=loc0,8;;
859 mov loc0=cr.isr;; // save isr
860 st8.spill [in0]=loc0,8;;
861 mov loc0=cr.iip;; // save iip
862 st8.spill [in0]=loc0,8;;
863 mov loc0=cr.ifa;; // save ifa
864 st8.spill [in0]=loc0,8;;
865 mov loc0=cr.itir;; // save itir
866 st8.spill [in0]=loc0,8;;
867 mov loc0=cr.iipa;; // save iipa
868 st8.spill [in0]=loc0,8;;
869 mov loc0=cr.ifs;; // save ifs
870 st8.spill [in0]=loc0,8;;
871 mov loc0=cr.iim;; // save iim
872 st8.spill [in0]=loc0,8;;
873 mov loc0=cr.iha;; // save iha
874 st8.spill [in0]=loc0,8;;
875
876 // save debug registers
877 mov loc0=dbr[r0];; // save dbr0 - dbr7
878 st8.spill [in0]=loc0,8;;
879 movl loc1=1;;
880 mov loc0=dbr[loc1];;
881 st8.spill [in0]=loc0,8;;
882 movl loc1=2;;
883 mov loc0=dbr[loc1];;
884 st8.spill [in0]=loc0,8;;
885 movl loc1=3;;
886 mov loc0=dbr[loc1];;
887 st8.spill [in0]=loc0,8;;
888 movl loc1=4;;
889 mov loc0=dbr[loc1];;
890 st8.spill [in0]=loc0,8;;
891 movl loc1=5;;
892 mov loc0=dbr[loc1];;
893 st8.spill [in0]=loc0,8;;
894 movl loc1=6;;
895 mov loc0=dbr[loc1];;
896 st8.spill [in0]=loc0,8;;
897 movl loc1=7;;
898 mov loc0=dbr[loc1];;
899 st8.spill [in0]=loc0,8;;
900 mov loc0=ibr[r0];; // save ibr0 - ibr7
901 st8.spill [in0]=loc0,8;;
902 movl loc1=1;;
903 mov loc0=ibr[loc1];;
904 st8.spill [in0]=loc0,8;;
905 movl loc1=2;;
906 mov loc0=ibr[loc1];;
907 st8.spill [in0]=loc0,8;;
908 movl loc1=3;;
909 mov loc0=ibr[loc1];;
910 st8.spill [in0]=loc0,8;;
911 movl loc1=4;;
912 mov loc0=ibr[loc1];;
913 st8.spill [in0]=loc0,8;;
914 movl loc1=5;;
915 mov loc0=ibr[loc1];;
916 st8.spill [in0]=loc0,8;;
917 movl loc1=6;;
918 mov loc0=ibr[loc1];;
919 st8.spill [in0]=loc0,8;;
920 movl loc1=7;;
921 mov loc0=ibr[loc1];;
922 st8.spill [in0]=loc0,8;;
923 st8.spill [in0]=loc3;;
924
925 br.ret.sptk.few b0
926
927 .endp SpillContext
928
929
930 /////////////////////////////////////////////
931 //
932 // Name:
933 // FillContext
934 //
935 // Description:
936 // Restores register context from context record.
937 //
938 // Arguments:
939 // in0 = address of last element 512 byte aligned context record address
940 // in1 = modified B0
941 // in2 = modified ar.bsp
942 // in3 = modified ar.bspstore
943 // in4 = modified ar.rnat
944 // in5 = modified ar.pfs
945 //
946 // Notes:
947 // loc0 - scratch
948 // loc1 - scratch
949 // loc2 - temporary application unat storage
950 // loc3 - temporary exception handler unat storage
951
952 .proc FillContext
953 FillContext:
954 alloc loc0=6,4,0,0;; // alloc 6 inputs, 4 locals, 0 outs
955 ld8.fill loc3=[in0],-8;; // int_nat (nat bits for R1-31)
956 movl loc1=7;; // ibr7
957 ld8.fill loc0=[in0],-8;;
958 mov ibr[loc1]=loc0;;
959 movl loc1=6;; // ibr6
960 ld8.fill loc0=[in0],-8;;
961 mov ibr[loc1]=loc0;;
962 movl loc1=5;; // ibr5
963 ld8.fill loc0=[in0],-8;;
964 mov ibr[loc1]=loc0;;
965 movl loc1=4;; // ibr4
966 ld8.fill loc0=[in0],-8;;
967 mov ibr[loc1]=loc0;;
968 movl loc1=3;; // ibr3
969 ld8.fill loc0=[in0],-8;;
970 mov ibr[loc1]=loc0;;
971 movl loc1=2;; // ibr2
972 ld8.fill loc0=[in0],-8;;
973 mov ibr[loc1]=loc0;;
974 movl loc1=1;; // ibr1
975 ld8.fill loc0=[in0],-8;;
976 mov ibr[loc1]=loc0;;
977 ld8.fill loc0=[in0],-8;; // ibr0
978 mov ibr[r0]=loc0;;
979 movl loc1=7;; // dbr7
980 ld8.fill loc0=[in0],-8;;
981 mov dbr[loc1]=loc0;;
982 movl loc1=6;; // dbr6
983 ld8.fill loc0=[in0],-8;;
984 mov dbr[loc1]=loc0;;
985 movl loc1=5;; // dbr5
986 ld8.fill loc0=[in0],-8;;
987 mov dbr[loc1]=loc0;;
988 movl loc1=4;; // dbr4
989 ld8.fill loc0=[in0],-8;;
990 mov dbr[loc1]=loc0;;
991 movl loc1=3;; // dbr3
992 ld8.fill loc0=[in0],-8;;
993 mov dbr[loc1]=loc0;;
994 movl loc1=2;; // dbr2
995 ld8.fill loc0=[in0],-8;;
996 mov dbr[loc1]=loc0;;
997 movl loc1=1;; // dbr1
998 ld8.fill loc0=[in0],-8;;
999 mov dbr[loc1]=loc0;;
1000 ld8.fill loc0=[in0],-8;; // dbr0
1001 mov dbr[r0]=loc0;;
1002 ld8.fill loc0=[in0],-8;; // iha
1003 mov cr.iha=loc0;;
1004 ld8.fill loc0=[in0],-8;; // iim
1005 mov cr.iim=loc0;;
1006 ld8.fill loc0=[in0],-8;; // ifs
1007 mov cr.ifs=loc0;;
1008 ld8.fill loc0=[in0],-8;; // iipa
1009 mov cr.iipa=loc0;;
1010 ld8.fill loc0=[in0],-8;; // itir
1011 mov cr.itir=loc0;;
1012 ld8.fill loc0=[in0],-8;; // ifa
1013 mov cr.ifa=loc0;;
1014 ld8.fill loc0=[in0],-8;; // iip
1015 mov cr.iip=loc0;;
1016 ld8.fill loc0=[in0],-8;; // isr
1017 mov cr.isr=loc0;;
1018 ld8.fill loc0=[in0],-8;; // ipsr
1019 mov cr.ipsr=loc0;;
1020 ld8.fill loc0=[in0],-8;; // pta
1021 mov cr.pta=loc0;;
1022 ld8.fill loc0=[in0],-8;; // iva
1023 mov cr.iva=loc0;;
1024 ld8.fill loc0=[in0],-8;; // itm
1025 mov cr.itm=loc0;;
1026 ld8.fill loc0=[in0],-8;; // dcr
1027 mov cr.dcr=loc0;;
1028 ld8.fill loc0=[in0],-8;; // ec
1029 mov ar.ec=loc0;;
1030 ld8.fill loc0=[in0],-8;; // lc
1031 mov ar.lc=loc0;;
1032 ld8.fill in5=[in0],-8;; // ar.pfs
1033 ld8.fill loc0=[in0],-8;; // ar.fpsr
1034 mov ar.fpsr=loc0;;
1035 ld8.fill loc2=[in0],-8;; // ar.unat - restored later...
1036 ld8.fill loc0=[in0],-8;; // ar.ccv
1037 mov ar.ccv=loc0;;
1038 ld8.fill loc0=[in0],-8;; // ar.fdr
1039 mov ar.fdr=loc0;;
1040 ld8.fill loc0=[in0],-8;; // ar.fir
1041 mov ar.fir=loc0;;
1042 ld8.fill loc0=[in0],-8;; // ar.fsr
1043 mov ar.fsr=loc0;;
1044 ld8.fill loc0=[in0],-8;; // ar.cflg
1045 mov ar.cflg=loc0;;
1046 ld8.fill loc0=[in0],-8;; // ar.ssd
1047 mov ar.ssd=loc0;;
1048 ld8.fill loc0=[in0],-8;; // ar.csd
1049 mov ar.csd=loc0;;
1050 ld8.fill loc0=[in0],-8;; // ar.eflag
1051 mov ar.eflag=loc0;;
1052 ld8.fill loc0=[in0],-8;; // ar.fcr
1053 mov ar.fcr=loc0;;
1054 ld8.fill in4=[in0],-8;; // ar.rnat
1055 ld8.fill in3=[in0],-8;; // bspstore
1056 ld8.fill in2=[in0],-8;; // bsp
1057 ld8.fill loc0=[in0],-8;; // ar.rsc
1058 mov ar.rsc=loc0;;
1059 ld8.fill loc0=[in0],-8;; // B7 - B0
1060 mov b7=loc0;;
1061 ld8.fill loc0=[in0],-8;;
1062 mov b6=loc0;;
1063 ld8.fill loc0=[in0],-8;;
1064 mov b5=loc0;;
1065 ld8.fill loc0=[in0],-8;;
1066 mov b4=loc0;;
1067 ld8.fill loc0=[in0],-8;;
1068 mov b3=loc0;;
1069 ld8.fill loc0=[in0],-8;;
1070 mov b2=loc0;;
1071 ld8.fill loc0=[in0],-8;;
1072 mov b1=loc0;;
1073 ld8.fill in1=[in0],-8;; // b0 is temporarily stored in in1
1074 ld8.fill loc0=[in0],-16;; // predicates
1075 mov pr=loc0;;
1076 ldf.fill f31=[in0],-16;;
1077 ldf.fill f30=[in0],-16;;
1078 ldf.fill f29=[in0],-16;;
1079 ldf.fill f28=[in0],-16;;
1080 ldf.fill f27=[in0],-16;;
1081 ldf.fill f26=[in0],-16;;
1082 ldf.fill f25=[in0],-16;;
1083 ldf.fill f24=[in0],-16;;
1084 ldf.fill f23=[in0],-16;;
1085 ldf.fill f22=[in0],-16;;
1086 ldf.fill f21=[in0],-16;;
1087 ldf.fill f20=[in0],-16;;
1088 ldf.fill f19=[in0],-16;;
1089 ldf.fill f18=[in0],-16;;
1090 ldf.fill f17=[in0],-16;;
1091 ldf.fill f16=[in0],-16;;
1092 ldf.fill f15=[in0],-16;;
1093 ldf.fill f14=[in0],-16;;
1094 ldf.fill f13=[in0],-16;;
1095 ldf.fill f12=[in0],-16;;
1096 ldf.fill f11=[in0],-16;;
1097 ldf.fill f10=[in0],-16;;
1098 ldf.fill f9=[in0],-16;;
1099 ldf.fill f8=[in0],-16;;
1100 ldf.fill f7=[in0],-16;;
1101 ldf.fill f6=[in0],-16;;
1102 ldf.fill f5=[in0],-16;;
1103 ldf.fill f4=[in0],-16;;
1104 ldf.fill f3=[in0],-16;;
1105 ldf.fill f2=[in0],-8;;
1106 mov ar.unat=loc3;; // restore unat (int_nat) before fill of general registers
1107 ld8.fill r31=[in0],-8;;
1108 ld8.fill r30=[in0],-8;;
1109 ld8.fill r29=[in0],-8;;
1110 ld8.fill r28=[in0],-8;;
1111 ld8.fill r27=[in0],-8;;
1112 ld8.fill r26=[in0],-8;;
1113 ld8.fill r25=[in0],-8;;
1114 ld8.fill r24=[in0],-8;;
1115 ld8.fill r23=[in0],-8;;
1116 ld8.fill r22=[in0],-8;;
1117 ld8.fill r21=[in0],-8;;
1118 ld8.fill r20=[in0],-8;;
1119 ld8.fill r19=[in0],-8;;
1120 ld8.fill r18=[in0],-8;;
1121 ld8.fill r17=[in0],-8;;
1122 ld8.fill r16=[in0],-8;;
1123 ld8.fill r15=[in0],-8;;
1124 ld8.fill r14=[in0],-8;;
1125 ld8.fill r13=[in0],-8;;
1126 ld8.fill r12=[in0],-8;;
1127 ld8.fill r11=[in0],-8;;
1128 ld8.fill r10=[in0],-8;;
1129 ld8.fill r9=[in0],-8;;
1130 ld8.fill r8=[in0],-8;;
1131 ld8.fill r7=[in0],-8;;
1132 ld8.fill r6=[in0],-8;;
1133 ld8.fill r5=[in0],-8;;
1134 ld8.fill r4=[in0],-8;;
1135 ld8.fill r3=[in0],-8;;
1136 ld8.fill r2=[in0],-8;;
1137 ld8.fill r1=[in0],-8;;
1138 mov ar.unat=loc2;; // restore application context unat
1139
1140 br.ret.sptk.many b0
1141
1142 .endp FillContext
1143
1144
1145 /////////////////////////////////////////////
1146 //
1147 // Name:
1148 // HookHandler
1149 //
1150 // Description:
1151 // Common branch target from hooked IVT entries. Runs in interrupt context.
1152 // Responsible for saving and restoring context and calling common C
1153 // handler. Banked registers running on bank 0 at entry.
1154 //
1155 // Arguments:
1156 // All arguments are passed in banked registers:
1157 // B0_REG = Original B0
1158 // SCRATCH_REG1 = IVT entry index
1159 //
1160 // Returns:
1161 // Returns via rfi
1162 //
1163 // Notes:
1164 // loc0 - scratch
1165 // loc1 - scratch
1166 // loc2 - vector number / mask
1167 // loc3 - 16 byte aligned context record address
1168 // loc4 - temporary storage of last address in context record
1169
1170 HookHandler:
1171 flushrs;; // Synch RSE with backing store
1172 mov SCRATCH_REG2=ar.bsp // save interrupted context bsp
1173 mov SCRATCH_REG3=ar.bspstore // save interrupted context bspstore
1174 mov SCRATCH_REG4=ar.rnat // save interrupted context rnat
1175 mov SCRATCH_REG6=cr.ifs;; // save IFS in case we need to chain...
1176 cover;; // creates new frame, moves old
1177 // CFM to IFS.
1178 alloc SCRATCH_REG5=0,5,6,0 // alloc 5 locals, 6 outs
1179 ;;
1180 // save banked registers to locals
1181 mov out1=B0_REG // out1 = Original B0
1182 mov out2=SCRATCH_REG2 // out2 = original ar.bsp
1183 mov out3=SCRATCH_REG3 // out3 = original ar.bspstore
1184 mov out4=SCRATCH_REG4 // out4 = original ar.rnat
1185 mov out5=SCRATCH_REG5 // out5 = original ar.pfs
1186 mov loc2=SCRATCH_REG1;; // loc2 = vector number + chain flag
1187 bsw.1;; // switch banked registers to bank 1
1188 srlz.d // explicit serialize required
1189 // now fill in context record structure
1190 movl loc3=IpfContextBuf // Insure context record is aligned
1191 add loc0=-0x200,r0;; // mask the lower 9 bits (align on 512 byte boundary)
1192 and loc3=loc3,loc0;;
1193 add loc3=0x200,loc3;; // move to next 512 byte boundary
1194 // loc3 now contains the 512 byte aligned context record
1195 // spill register context into context record
1196 mov out0=loc3;; // Context record base in out0
1197 // original B0 in out1 already
1198 // original ar.bsp in out2 already
1199 // original ar.bspstore in out3 already
1200 br.call.sptk.few b0=SpillContext;; // spill context
1201 mov loc4=out0 // save modified address
1202
1203 // At this point, the context has been saved to the context record and we're
1204 // ready to call the C part of the handler...
1205
1206 movl loc0=CommonHandler;; // obtain address of plabel
1207 ld8 loc1=[loc0];; // get entry point of CommonHandler
1208 mov b6=loc1;; // put it in a branch register
1209 adds loc1= 8, loc0;; // index to GP in plabel
1210 ld8 r1=[loc1];; // set up gp for C call
1211 mov loc1=0xfffff;; // mask off so only vector bits are present
1212 and out0=loc2,loc1;; // pass vector number (exception type)
1213 mov out1=loc3;; // pass context record address
1214 br.call.sptk.few b0=b6;; // call C handler
1215
1216 // We've returned from the C call, so restore the context and either rfi
1217 // back to interrupted thread, or chain into the SAL if this was an external interrupt
1218 mov out0=loc4;; // pass address of last element in context record
1219 br.call.sptk.few b0=FillContext;; // Fill context
1220 mov b0=out1 // fill in b0
1221 mov ar.rnat=out4
1222 mov ar.pfs=out5
1223
1224 // Loadrs is necessary because the debugger may have changed some values in
1225 // the backing store. The processor, however may not be aware that the
1226 // stacked registers need to be reloaded from the backing store. Therefore,
1227 // we explicitly cause the RSE to refresh the stacked register's contents
1228 // from the backing store.
1229 mov loc0=ar.rsc // get RSC value
1230 mov loc1=ar.rsc // save it so we can restore it
1231 movl loc3=0xffffffffc000ffff;; // create mask for clearing RSC.loadrs
1232 and loc0=loc0,loc3;; // create value for RSC with RSC.loadrs==0
1233 mov ar.rsc=loc0;; // modify RSC
1234 loadrs;; // invalidate register stack
1235 mov ar.rsc=loc1;; // restore original RSC
1236
1237 bsw.0;; // switch banked registers back to bank 0
1238 srlz.d;; // explicit serialize required
1239 mov PR_REG=pr // save predicates - to be restored after chaining decision
1240 mov B0_REG=b0 // save b0 - required by chain code
1241 mov loc2=EXCPT_EXTERNAL_INTERRUPT;;
1242 cmp.eq p7,p0=SCRATCH_REG1,loc2;; // check to see if this is the timer tick
1243 (p7) br.cond.dpnt.few DO_CHAIN;;
1244
1245 NO_CHAIN:
1246 mov pr=PR_REG;;
1247 rfi;; // we're outa here.
1248
1249 DO_CHAIN:
1250 mov pr=PR_REG
1251 mov SCRATCH_REG1=cr.iva
1252 mov SCRATCH_REG2=PATCH_RETURN_OFFSET;;
1253 add SCRATCH_REG1=SCRATCH_REG1, SCRATCH_REG2;;
1254 mov b0=SCRATCH_REG1;;
1255 br.cond.sptk.few b0;;
1256
1257 EndHookHandler:
1258
1259
1260 /////////////////////////////////////////////
1261 //
1262 // Name:
1263 // HookStub
1264 //
1265 // Description:
1266 // HookStub will be copied from it's loaded location into the IVT when
1267 // an IVT entry is hooked. The IVT entry does an indirect jump via B0 to
1268 // HookHandler, which in turn calls into the default C handler, which calls
1269 // the user-installed C handler. The calls return and HookHandler executes
1270 // an rfi.
1271 //
1272 // Notes:
1273 // Saves B0 to B0_REG
1274 // Saves IVT index to SCRATCH_REG1 (immediate value is fixed up when code is copied
1275 // to the IVT entry.
1276
1277 .globl HookStub
1278 .proc HookStub
1279 HookStub:
1280
1281 mov B0_REG=b0
1282 movl SCRATCH_REG1=HookHandler;;
1283 mov b0=SCRATCH_REG1;;
1284 mov SCRATCH_REG1=0;;// immediate value is fixed up during install of handler to be the vector number
1285 br.cond.sptk.few b0
1286
1287 .endp HookStub
1288
1289
1290 /////////////////////////////////////////////
1291 // The following code is moved into IVT entry 14 (offset 3400) which is reserved
1292 // in the Itanium architecture. The patch code is located at the end of the
1293 // IVT entry.
1294
1295 PatchCode:
1296 mov SCRATCH_REG0=psr
1297 mov SCRATCH_REG6=cr.ipsr
1298 mov PR_REG=pr
1299 mov B0_REG=b0;;
1300
1301 // turn off any virtual translations
1302 movl SCRATCH_REG1 = ~( MASK(PSR_DT,1) | MASK(PSR_RT,1));;
1303 and SCRATCH_REG1 = SCRATCH_REG0, SCRATCH_REG1;;
1304 mov psr.l = SCRATCH_REG1;;
1305 srlz.d
1306 tbit.z p14, p15 = SCRATCH_REG6, PSR_IS;; // Check to see if we were
1307 // interrupted from IA32
1308 // context. If so, bail out
1309 // and chain to SAL immediately
1310 (p15) br.cond.sptk.few Stub_IVT_Passthru;;
1311 // we only want to take 1 out of 32 external interrupts to minimize the
1312 // impact to system performance. Check our interrupt count and bail
1313 // out if we're not up to 32
1314 movl SCRATCH_REG1=ExternalInterruptCount;;
1315 ld8 SCRATCH_REG2=[SCRATCH_REG1];; // ExternalInterruptCount
1316 tbit.z p14, p15 = SCRATCH_REG2, 5;; // bit 5 set?
1317 (p14) add SCRATCH_REG2=1, SCRATCH_REG2;; // No? Then increment
1318 // ExternalInterruptCount
1319 // and Chain to SAL
1320 // immediately
1321 (p14) st8 [SCRATCH_REG1]=SCRATCH_REG2;;
1322 (p14) br.cond.sptk.few Stub_IVT_Passthru;;
1323 (p15) mov SCRATCH_REG2=0;; // Yes? Then reset
1324 // ExternalInterruptCount
1325 // and branch to
1326 // HookHandler
1327 (p15) st8 [SCRATCH_REG1]=SCRATCH_REG2;;
1328 mov pr=PR_REG
1329 movl SCRATCH_REG1=HookHandler;; // SCRATCH_REG1 = entrypoint of HookHandler
1330 mov b0=SCRATCH_REG1;; // b0 = entrypoint of HookHandler
1331 mov SCRATCH_REG1=EXCPT_EXTERNAL_INTERRUPT;;
1332 br.sptk.few b0;; // branch to HookHandler
1333
1334 PatchCodeRet:
1335 // fake-up an rfi to get RSE back to being coherent and insure psr has
1336 // original contents when interrupt occured, then exit to SAL
1337 // at this point:
1338 // cr.ifs has been modified by previous "cover"
1339 // SCRATCH_REG6 has original cr.ifs
1340
1341 mov SCRATCH_REG5=cr.ipsr
1342 mov SCRATCH_REG4=cr.iip;;
1343 mov cr.ipsr=SCRATCH_REG0
1344 mov SCRATCH_REG1=ip;;
1345 add SCRATCH_REG1=0x30, SCRATCH_REG1;;
1346 mov cr.iip=SCRATCH_REG1;;
1347 rfi;; // rfi to next instruction
1348
1349 Stub_RfiTarget:
1350 mov cr.ifs=SCRATCH_REG6
1351 mov cr.ipsr=SCRATCH_REG5
1352 mov cr.iip=SCRATCH_REG4;;
1353
1354 Stub_IVT_Passthru:
1355 mov pr=PR_REG // pr = saved predicate registers
1356 mov b0=B0_REG;; // b0 = saved b0
1357 EndPatchCode:
1358
1359
1360 /////////////////////////////////////////////
1361 // The following bundle is moved into IVT entry 14 (offset 0x3400) which is reserved
1362 // in the Itanium architecture. This bundle will be the last bundle and will
1363 // be located at offset 0x37F0 in the IVT.
1364
1365 FailsafeBranch:
1366 {
1367 .mib
1368 nop.m 0
1369 nop.i 0
1370 br.sptk.few -(FAILSAFE_BRANCH_OFFSET - EXT_INT_ENTRY_OFFSET - 0x10)
1371 }
1372
1373
1374 /////////////////////////////////////////////
1375 // The following bundle is moved into IVT entry 13 (offset 0x3000) which is the
1376 // external interrupt. It branches to the patch code.
1377
1378 PatchCodeNewBun0:
1379 {
1380 .mib
1381 nop.m 0
1382 nop.i 0
1383 br.cond.sptk.few PATCH_BRANCH
1384 }
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