MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h

   1 /** @file
   2   Arm Error Source Table as described in the
   3   'ACPI for the Armv8 RAS Extensions 1.1' Specification.
   4
   5   Copyright (c) 2020 Arm Limited.
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8   @par Reference(s):
   9     - ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document,
  10       dated 28 September 2020.
  11       (https://developer.arm.com/documentation/den0085/0101/)
  12
  13   @par Glossary
  14     - Ref : Reference
  15     - Id  : Identifier
  16 **/
  17
  18 #ifndef ARM_ERROR_SOURCE_TABLE_H_
  19 #define ARM_ERROR_SOURCE_TABLE_H_
  20
  21 ///
  22 /// "AEST" Arm Error Source Table
  23 ///
  24 #define EFI_ACPI_6_3_ARM_ERROR_SOURCE_TABLE_SIGNATURE  SIGNATURE_32('A', 'E', 'S', 'T')
  25
  26 #define EFI_ACPI_ARM_ERROR_SOURCE_TABLE_REVISION  1
  27
  28 #pragma pack(1)
  29
  30 ///
  31 /// Arm Error Source Table definition.
  32 ///
  33 typedef struct {
  34   EFI_ACPI_DESCRIPTION_HEADER    Header;
  35 } EFI_ACPI_ARM_ERROR_SOURCE_TABLE;
  36
  37 ///
  38 /// AEST Node structure.
  39 ///
  40 typedef struct {
  41   /// Node type:
  42   ///   0x00 - Processor error node
  43   ///   0x01 - Memory error node
  44   ///   0x02 - SMMU error node
  45   ///   0x03 - Vendor-defined error node
  46   ///   0x04 - GIC error node
  47   UINT8     Type;
  48
  49   /// Length of structure in bytes.
  50   UINT16    Length;
  51
  52   /// Reserved - Must be zero.
  53   UINT8     Reserved;
  54
  55   /// Offset from the start of the node to node-specific data.
  56   UINT32    DataOffset;
  57
  58   /// Offset from the start of the node to the node interface structure.
  59   UINT32    InterfaceOffset;
  60
  61   /// Offset from the start of the node to node interrupt array.
  62   UINT32    InterruptArrayOffset;
  63
  64   /// Number of entries in the interrupt array.
  65   UINT32    InterruptArrayCount;
  66
  67   // Generic node data
  68
  69   /// The timestamp frequency of the counter in Hz.
  70   UINT64    TimestampRate;
  71
  72   /// Reserved - Must be zero.
  73   UINT64    Reserved1;
  74
  75   /// The rate in Hz at which the Error Generation Counter decrements.
  76   UINT64    ErrorInjectionCountdownRate;
  77 } EFI_ACPI_AEST_NODE_STRUCT;
  78
  79 // AEST Node type definitions
  80 #define EFI_ACPI_AEST_NODE_TYPE_PROCESSOR       0x0
  81 #define EFI_ACPI_AEST_NODE_TYPE_MEMORY          0x1
  82 #define EFI_ACPI_AEST_NODE_TYPE_SMMU            0x2
  83 #define EFI_ACPI_AEST_NODE_TYPE_VENDOR_DEFINED  0x3
  84 #define EFI_ACPI_AEST_NODE_TYPE_GIC             0x4
  85
  86 ///
  87 /// AEST Node Interface structure.
  88 ///
  89 typedef struct {
  90   /// Interface type:
  91   ///   0x0 - System register (SR)
  92   ///   0x1 - Memory mapped (MMIO)
  93   UINT8     Type;
  94
  95   /// Reserved - Must be zero.
  96   UINT8     Reserved[3];
  97
  98   /// AEST node interface flags.
  99   UINT32    Flags;
 100
 101   /// Base address of error group that contains the error node.
 102   UINT64    BaseAddress;
 103
 104   /// Zero-based index of the first standard error record that
 105   /// belongs to this node.
 106   UINT32    StartErrorRecordIndex;
 107
 108   /// Number of error records in this node including both
 109   /// implemented and unimplemented records.
 110   UINT32    NumberErrorRecords;
 111
 112   /// A bitmap indicating the error records within this
 113   /// node that are implemented in the current system.
 114   UINT64    ErrorRecordImplemented;
 115
 116   /// A bitmap indicating the error records within this node that
 117   /// support error status reporting through the ERRGSR register.
 118   UINT64    ErrorRecordStatusReportingSupported;
 119
 120   /// A bitmap indicating the addressing mode used by each error
 121   /// record within this node to populate the ERR<n>_ADDR register.
 122   UINT64    AddressingMode;
 123 } EFI_ACPI_AEST_INTERFACE_STRUCT;
 124
 125 // AEST Interface node type definitions.
 126 #define EFI_ACPI_AEST_INTERFACE_TYPE_SR    0x0
 127 #define EFI_ACPI_AEST_INTERFACE_TYPE_MMIO  0x1
 128
 129 // AEST node interface flag definitions.
 130 #define EFI_ACPI_AEST_INTERFACE_FLAG_PRIVATE      0
 131 #define EFI_ACPI_AEST_INTERFACE_FLAG_SHARED       BIT0
 132 #define EFI_ACPI_AEST_INTERFACE_FLAG_CLEAR_MISCX  BIT1
 133
 134 ///
 135 /// AEST Node Interrupt structure.
 136 ///
 137 typedef struct {
 138   /// Interrupt type:
 139   ///   0x0 - Fault Handling Interrupt
 140   ///   0x1 - Error Recovery Interrupt
 141   UINT8     InterruptType;
 142
 143   /// Reserved - Must be zero.
 144   UINT8     Reserved[2];
 145
 146   /// Interrupt flags
 147   /// Bits [31:1]: Must be zero.
 148   /// Bit 0:
 149   ///   0b - Interrupt is edge-triggered
 150   ///   1b - Interrupt is level-triggered
 151   UINT8     InterruptFlags;
 152
 153   /// GSIV of interrupt, if interrupt is an SPI or a PPI.
 154   UINT32    InterruptGsiv;
 155
 156   /// If MSI is supported, then this field must be set to the
 157   /// Identifier field of the IORT ITS Group node.
 158   UINT8     ItsGroupRefId;
 159
 160   /// Reserved - must be zero.
 161   UINT8     Reserved1[3];
 162 } EFI_ACPI_AEST_INTERRUPT_STRUCT;
 163
 164 // AEST Interrupt node - interrupt type defintions.
 165 #define EFI_ACPI_AEST_INTERRUPT_TYPE_FAULT_HANDLING  0x0
 166 #define EFI_ACPI_AEST_INTERRUPT_TYPE_ERROR_RECOVERY  0x1
 167
 168 // AEST Interrupt node - interrupt flag defintions.
 169 #define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_EDGE   0
 170 #define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_LEVEL  BIT0
 171
 172 ///
 173 /// Cache Processor Resource structure.
 174 ///
 175 typedef struct {
 176   /// Reference to the cache structure in the PPTT table.
 177   UINT32    CacheRefId;
 178
 179   /// Reserved
 180   UINT32    Reserved;
 181 } EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT;
 182
 183 ///
 184 /// TLB Processor Resource structure.
 185 ///
 186 typedef struct {
 187   /// TLB level from perspective of current processor.
 188   UINT32    TlbRefId;
 189
 190   /// Reserved
 191   UINT32    Reserved;
 192 } EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT;
 193
 194 ///
 195 /// Processor Generic Resource structure.
 196 ///
 197 typedef struct {
 198   /// Vendor-defined supplementary data.
 199   UINT32    Data;
 200 } EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT;
 201
 202 ///
 203 /// AEST Processor Resource union.
 204 ///
 205 typedef union {
 206   /// Processor Cache resource.
 207   EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT      Cache;
 208
 209   /// Processor TLB resource.
 210   EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT        Tlb;
 211
 212   /// Processor Generic resource.
 213   EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT    Generic;
 214 } EFI_ACPI_AEST_PROCESSOR_RESOURCE;
 215
 216 ///
 217 /// AEST Processor structure.
 218 ///
 219 typedef struct {
 220   /// AEST Node header
 221   EFI_ACPI_AEST_NODE_STRUCT           NodeHeader;
 222
 223   /// Processor ID of node.
 224   UINT32                              AcpiProcessorId;
 225
 226   /// Resource type of the processor node.
 227   ///   0x0 - Cache
 228   ///   0x1 - TLB
 229   ///   0x2 - Generic
 230   UINT8                               ResourceType;
 231
 232   /// Reserved - must be zero.
 233   UINT8                               Reserved;
 234
 235   /// Processor structure flags.
 236   UINT8                               Flags;
 237
 238   /// Processor structure revision.
 239   UINT8                               Revision;
 240
 241   /// Processor affinity descriptor for the resource that this
 242   /// error node pertains to.
 243   UINT64                              ProcessorAffinityLevelIndicator;
 244
 245   /// Processor resource
 246   EFI_ACPI_AEST_PROCESSOR_RESOURCE    Resource;
 247
 248   // Node Interface
 249   // EFI_ACPI_AEST_INTERFACE_STRUCT   NodeInterface;
 250
 251   // Node Interrupt Array
 252   // EFI_ACPI_AEST_INTERRUPT_STRUCT   NodeInterruptArray[n];
 253 } EFI_ACPI_AEST_PROCESSOR_STRUCT;
 254
 255 // AEST Processor resource type definitions.
 256 #define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_CACHE    0x0
 257 #define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_TLB      0x1
 258 #define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_GENERIC  0x2
 259
 260 // AEST Processor flag definitions.
 261 #define EFI_ACPI_AEST_PROCESSOR_FLAG_GLOBAL  BIT0
 262 #define EFI_ACPI_AEST_PROCESSOR_FLAG_SHARED  BIT1
 263
 264 ///
 265 /// Memory Controller structure.
 266 ///
 267 typedef struct {
 268   /// AEST Node header
 269   EFI_ACPI_AEST_NODE_STRUCT    NodeHeader;
 270
 271   /// SRAT proximity domain.
 272   UINT32                       ProximityDomain;
 273
 274   // Node Interface
 275   // EFI_ACPI_AEST_INTERFACE_STRUCT   NodeInterface;
 276
 277   // Node Interrupt Array
 278   // EFI_ACPI_AEST_INTERRUPT_STRUCT   NodeInterruptArray[n];
 279 } EFI_ACPI_AEST_MEMORY_CONTROLLER_STRUCT;
 280
 281 ///
 282 /// SMMU structure.
 283 ///
 284 typedef struct {
 285   /// AEST Node header
 286   EFI_ACPI_AEST_NODE_STRUCT    NodeHeader;
 287
 288   /// Reference to the IORT table node that describes this SMMU.
 289   UINT32                       SmmuRefId;
 290
 291   /// Reference to the IORT table node that is associated with the
 292   /// sub-component within this SMMU.
 293   UINT32                       SubComponentRefId;
 294
 295   // Node Interface
 296   // EFI_ACPI_AEST_INTERFACE_STRUCT   NodeInterface;
 297
 298   // Node Interrupt Array
 299   // EFI_ACPI_AEST_INTERRUPT_STRUCT   NodeInterruptArray[n];
 300 } EFI_ACPI_AEST_SMMU_STRUCT;
 301
 302 ///
 303 /// Vendor-Defined structure.
 304 ///
 305 typedef struct {
 306   /// AEST Node header
 307   EFI_ACPI_AEST_NODE_STRUCT    NodeHeader;
 308
 309   /// ACPI HID of the component.
 310   UINT32                       HardwareId;
 311
 312   /// The ACPI Unique identifier of the component.
 313   UINT32                       UniqueId;
 314
 315   /// Vendor-specific data, for example to identify this error source.
 316   UINT8                        VendorData[16];
 317
 318   // Node Interface
 319   // EFI_ACPI_AEST_INTERFACE_STRUCT   NodeInterface;
 320
 321   // Node Interrupt Array
 322   // EFI_ACPI_AEST_INTERRUPT_STRUCT   NodeInterruptArray[n];
 323 } EFI_ACPI_AEST_VENDOR_DEFINED_STRUCT;
 324
 325 ///
 326 /// GIC structure.
 327 ///
 328 typedef struct {
 329   /// AEST Node header
 330   EFI_ACPI_AEST_NODE_STRUCT    NodeHeader;
 331
 332   /// Type of GIC interface that is associated with this error node.
 333   ///   0x0 - GIC CPU (GICC)
 334   ///   0x1 - GIC Distributor (GICD)
 335   ///   0x2 - GIC Resistributor (GICR)
 336   ///   0x3 - GIC ITS (GITS)
 337   UINT32                       InterfaceType;
 338
 339   /// Identifier for the interface instance.
 340   UINT32                       GicInterfaceRefId;
 341
 342   // Node Interface
 343   // EFI_ACPI_AEST_INTERFACE_STRUCT   NodeInterface;
 344
 345   // Node Interrupt Array
 346   // EFI_ACPI_AEST_INTERRUPT_STRUCT   NodeInterruptArray[n];
 347 } EFI_ACPI_AEST_GIC_STRUCT;
 348
 349 // AEST GIC interface type definitions.
 350 #define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICC  0x0
 351 #define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICD  0x1
 352 #define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICR  0x2
 353 #define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GITS  0x3
 354
 355 #pragma pack()
 356
 357 #endif // ARM_ERROR_SOURCE_TABLE_H_