2 Defives data structures per MultiProcessor Specification Ver 1.4.
4 The MultiProcessor Specification defines an enhancement to the standard
5 to which PC manufacturers design DOS-compatible systems.
7 Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #ifndef _LEGACY_BIOS_MPTABLE_H_
19 #define _LEGACY_BIOS_MPTABLE_H_
21 #define EFI_LEGACY_MP_TABLE_REV_1_4 0x04
24 // Define MP table structures. All are packed.
28 #define EFI_LEGACY_MP_TABLE_FLOATING_POINTER_SIGNATURE SIGNATURE_32 ('_', 'M', 'P', '_')
31 UINT32 PhysicalAddress
;
38 UINT32 MutipleClk
: 1;
40 UINT32 Reserved2
: 24;
42 } EFI_LEGACY_MP_TABLE_FLOATING_POINTER
;
44 #define EFI_LEGACY_MP_TABLE_HEADER_SIGNATURE SIGNATURE_32 ('P', 'C', 'M', 'P')
47 UINT16 BaseTableLength
;
51 CHAR8 OemProductId
[12];
52 UINT32 OemTablePointer
;
55 UINT32 LocalApicAddress
;
56 UINT16 ExtendedTableLength
;
57 UINT8 ExtendedChecksum
;
59 } EFI_LEGACY_MP_TABLE_HEADER
;
63 } EFI_LEGACY_MP_TABLE_ENTRY_TYPE
;
66 // Entry Type 0: Processor.
68 #define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_PROCESSOR 0x00
90 UINT32 Reserved2
: 22;
94 } EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR
;
99 #define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_BUS 0x01
104 } EFI_LEGACY_MP_TABLE_ENTRY_BUS
;
106 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS "CBUS " // Corollary CBus
107 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII" // Corollary CBUS II
108 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA "EISA " // Extended ISA
109 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE" // IEEE FutureBus
110 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN" // Internal bus
111 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA "ISA " // Industry Standard Architecture
112 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI "MBI " // Multibus I
113 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII "MBII " // Multibus II
114 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA "MCA " // Micro Channel Architecture
115 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI "MPI " // MPI
116 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA "MPSA " // MPSA
117 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS "NUBUS " // Apple Macintosh NuBus
118 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI "PCI " // Peripheral Component Interconnect
119 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA" // PC Memory Card International Assoc.
120 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC "TC " // DEC TurboChannel
121 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL "VL " // VESA Local Bus
122 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME "VME " // VMEbus
123 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS" // Express System Bus
125 // Entry Type 2: I/O APIC.
127 #define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02
137 } EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC
;
140 // Entry Type 3: I/O Interrupt Assignment.
142 #define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03
149 UINT16 Reserved
: 12;
162 } EFI_LEGACY_MP_TABLE_ENTRY_IO_INT
;
165 EfiLegacyMpTableEntryIoIntTypeInt
= 0,
166 EfiLegacyMpTableEntryIoIntTypeNmi
= 1,
167 EfiLegacyMpTableEntryIoIntTypeSmi
= 2,
168 EfiLegacyMpTableEntryIoIntTypeExtInt
= 3,
169 } EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_TYPE
;
172 EfiLegacyMpTableEntryIoIntFlagsPolaritySpec
= 0x0,
173 EfiLegacyMpTableEntryIoIntFlagsPolarityActiveHigh
= 0x1,
174 EfiLegacyMpTableEntryIoIntFlagsPolarityReserved
= 0x2,
175 EfiLegacyMpTableEntryIoIntFlagsPolarityActiveLow
= 0x3,
176 } EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_POLARITY
;
179 EfiLegacyMpTableEntryIoIntFlagsTriggerSpec
= 0x0,
180 EfiLegacyMpTableEntryIoIntFlagsTriggerEdge
= 0x1,
181 EfiLegacyMpTableEntryIoIntFlagsTriggerReserved
= 0x2,
182 EfiLegacyMpTableEntryIoIntFlagsTriggerLevel
= 0x3,
183 } EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_TRIGGER
;
186 // Entry Type 4: Local Interrupt Assignment.
188 #define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_LOCAL_INT 0x04
195 UINT16 Reserved
: 12;
208 } EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT
;
211 EfiLegacyMpTableEntryLocalIntTypeInt
= 0,
212 EfiLegacyMpTableEntryLocalIntTypeNmi
= 1,
213 EfiLegacyMpTableEntryLocalIntTypeSmi
= 2,
214 EfiLegacyMpTableEntryLocalIntTypeExtInt
= 3,
215 } EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_TYPE
;
218 EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec
= 0x0,
219 EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh
= 0x1,
220 EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved
= 0x2,
221 EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow
= 0x3,
222 } EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_POLARITY
;
225 EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec
= 0x0,
226 EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge
= 0x1,
227 EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved
= 0x2,
228 EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel
= 0x3,
229 } EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_TRIGGER
;
232 // Entry Type 128: System Address Space Mapping.
234 #define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80
241 UINT64 AddressLength
;
242 } EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING
;
245 EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo
= 0,
246 EfiLegacyMpTableEntryExtSysAddrSpaceMappingMemory
= 1,
247 EfiLegacyMpTableEntryExtSysAddrSpaceMappingPrefetch
= 2,
248 } EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING_TYPE
;
251 // Entry Type 129: Bus Hierarchy.
253 #define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_BUS_HIERARCHY 0x81
259 UINT8 SubtractiveDecode
: 1;
266 } EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY
;
269 // Entry Type 130: Compatibility Bus Address Space Modifier.
271 #define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82
280 UINT32 PredefinedRangeList
;
281 } EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER
;