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1 /** @file
2 Definitions based on NVMe spec. version 1.1.
3
4 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
5 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 @par Specification Reference:
9 NVMe Specification 1.1
10
11 **/
12
13 #ifndef __NVM_E_H__
14 #define __NVM_E_H__
15
16 #pragma pack(1)
17
18 //
19 // controller register offsets
20 //
21 #define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
22 #define NVME_VER_OFFSET 0x0008 // Version
23 #define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
24 #define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
25 #define NVME_CC_OFFSET 0x0014 // Controller Configuration
26 #define NVME_CSTS_OFFSET 0x001c // Controller Status
27 #define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
28 #define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
29 #define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
30 #define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
31 #define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
32 #define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
33
34 //
35 // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
36 // Get the doorbell stride bit shift value from the controller capabilities.
37 //
38 #define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
39 #define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
40
41 #pragma pack(1)
42
43 //
44 // 3.1.1 Offset 00h: CAP - Controller Capabilities
45 //
46 typedef struct {
47 UINT16 Mqes; // Maximum Queue Entries Supported
48 UINT8 Cqr : 1; // Contiguous Queues Required
49 UINT8 Ams : 2; // Arbitration Mechanism Supported
50 UINT8 Rsvd1 : 5;
51 UINT8 To; // Timeout
52 UINT16 Dstrd : 4;
53 UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS
54 UINT16 Css : 4; // Command Sets Supported - Bit 37
55 UINT16 Rsvd3 : 7;
56 UINT8 Mpsmin : 4;
57 UINT8 Mpsmax : 4;
58 UINT8 Rsvd4;
59 } NVME_CAP;
60
61 //
62 // 3.1.2 Offset 08h: VS - Version
63 //
64 typedef struct {
65 UINT16 Mnr; // Minor version number
66 UINT16 Mjr; // Major version number
67 } NVME_VER;
68
69 //
70 // 3.1.5 Offset 14h: CC - Controller Configuration
71 //
72 typedef struct {
73 UINT16 En : 1; // Enable
74 UINT16 Rsvd1 : 3;
75 UINT16 Css : 3; // I/O Command Set Selected
76 UINT16 Mps : 4; // Memory Page Size
77 UINT16 Ams : 3; // Arbitration Mechanism Selected
78 UINT16 Shn : 2; // Shutdown Notification
79 UINT8 Iosqes : 4; // I/O Submission Queue Entry Size
80 UINT8 Iocqes : 4; // I/O Completion Queue Entry Size
81 UINT8 Rsvd2;
82 } NVME_CC;
83 #define NVME_CC_SHN_NORMAL_SHUTDOWN 1
84 #define NVME_CC_SHN_ABRUPT_SHUTDOWN 2
85
86 //
87 // 3.1.6 Offset 1Ch: CSTS - Controller Status
88 //
89 typedef struct {
90 UINT32 Rdy : 1; // Ready
91 UINT32 Cfs : 1; // Controller Fatal Status
92 UINT32 Shst : 2; // Shutdown Status
93 UINT32 Nssro : 1; // NVM Subsystem Reset Occurred
94 UINT32 Rsvd1 : 27;
95 } NVME_CSTS;
96 #define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1
97 #define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2
98 //
99 // 3.1.8 Offset 24h: AQA - Admin Queue Attributes
100 //
101 typedef struct {
102 UINT16 Asqs : 12; // Submission Queue Size
103 UINT16 Rsvd1 : 4;
104 UINT16 Acqs : 12; // Completion Queue Size
105 UINT16 Rsvd2 : 4;
106 } NVME_AQA;
107
108 //
109 // 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
110 //
111 #define NVME_ASQ UINT64
112 //
113 // 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
114 //
115 #define NVME_ACQ UINT64
116
117 //
118 // 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
119 //
120 typedef struct {
121 UINT16 Sqt;
122 UINT16 Rsvd1;
123 } NVME_SQTDBL;
124
125 //
126 // 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
127 //
128 typedef struct {
129 UINT16 Cqh;
130 UINT16 Rsvd1;
131 } NVME_CQHDBL;
132
133 //
134 // NVM command set structures
135 //
136 // Read Command
137 //
138 typedef struct {
139 //
140 // CDW 10, 11
141 //
142 UINT64 Slba; /* Starting Sector Address */
143 //
144 // CDW 12
145 //
146 UINT16 Nlb; /* Number of Sectors */
147 UINT16 Rsvd1 : 10;
148 UINT16 Prinfo : 4; /* Protection Info Check */
149 UINT16 Fua : 1; /* Force Unit Access */
150 UINT16 Lr : 1; /* Limited Retry */
151 //
152 // CDW 13
153 //
154 UINT32 Af : 4; /* Access Frequency */
155 UINT32 Al : 2; /* Access Latency */
156 UINT32 Sr : 1; /* Sequential Request */
157 UINT32 In : 1; /* Incompressible */
158 UINT32 Rsvd2 : 24;
159 //
160 // CDW 14
161 //
162 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
163 //
164 // CDW 15
165 //
166 UINT16 Elbat; /* Expected Logical Block Application Tag */
167 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
168 } NVME_READ;
169
170 //
171 // Write Command
172 //
173 typedef struct {
174 //
175 // CDW 10, 11
176 //
177 UINT64 Slba; /* Starting Sector Address */
178 //
179 // CDW 12
180 //
181 UINT16 Nlb; /* Number of Sectors */
182 UINT16 Rsvd1 : 10;
183 UINT16 Prinfo : 4; /* Protection Info Check */
184 UINT16 Fua : 1; /* Force Unit Access */
185 UINT16 Lr : 1; /* Limited Retry */
186 //
187 // CDW 13
188 //
189 UINT32 Af : 4; /* Access Frequency */
190 UINT32 Al : 2; /* Access Latency */
191 UINT32 Sr : 1; /* Sequential Request */
192 UINT32 In : 1; /* Incompressible */
193 UINT32 Rsvd2 : 24;
194 //
195 // CDW 14
196 //
197 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
198 //
199 // CDW 15
200 //
201 UINT16 Lbat; /* Logical Block Application Tag */
202 UINT16 Lbatm; /* Logical Block Application Tag Mask */
203 } NVME_WRITE;
204
205 //
206 // Flush
207 //
208 typedef struct {
209 //
210 // CDW 10
211 //
212 UINT32 Flush; /* Flush */
213 } NVME_FLUSH;
214
215 //
216 // Write Uncorrectable command
217 //
218 typedef struct {
219 //
220 // CDW 10, 11
221 //
222 UINT64 Slba; /* Starting LBA */
223 //
224 // CDW 12
225 //
226 UINT32 Nlb : 16; /* Number of Logical Blocks */
227 UINT32 Rsvd1 : 16;
228 } NVME_WRITE_UNCORRECTABLE;
229
230 //
231 // Write Zeroes command
232 //
233 typedef struct {
234 //
235 // CDW 10, 11
236 //
237 UINT64 Slba; /* Starting LBA */
238 //
239 // CDW 12
240 //
241 UINT16 Nlb; /* Number of Logical Blocks */
242 UINT16 Rsvd1 : 10;
243 UINT16 Prinfo : 4; /* Protection Info Check */
244 UINT16 Fua : 1; /* Force Unit Access */
245 UINT16 Lr : 1; /* Limited Retry */
246 //
247 // CDW 13
248 //
249 UINT32 Rsvd2;
250 //
251 // CDW 14
252 //
253 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
254 //
255 // CDW 15
256 //
257 UINT16 Lbat; /* Logical Block Application Tag */
258 UINT16 Lbatm; /* Logical Block Application Tag Mask */
259 } NVME_WRITE_ZEROES;
260
261 //
262 // Compare command
263 //
264 typedef struct {
265 //
266 // CDW 10, 11
267 //
268 UINT64 Slba; /* Starting LBA */
269 //
270 // CDW 12
271 //
272 UINT16 Nlb; /* Number of Logical Blocks */
273 UINT16 Rsvd1 : 10;
274 UINT16 Prinfo : 4; /* Protection Info Check */
275 UINT16 Fua : 1; /* Force Unit Access */
276 UINT16 Lr : 1; /* Limited Retry */
277 //
278 // CDW 13
279 //
280 UINT32 Rsvd2;
281 //
282 // CDW 14
283 //
284 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
285 //
286 // CDW 15
287 //
288 UINT16 Elbat; /* Expected Logical Block Application Tag */
289 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
290 } NVME_COMPARE;
291
292 typedef union {
293 NVME_READ Read;
294 NVME_WRITE Write;
295 NVME_FLUSH Flush;
296 NVME_WRITE_UNCORRECTABLE WriteUncorrectable;
297 NVME_WRITE_ZEROES WriteZeros;
298 NVME_COMPARE Compare;
299 } NVME_CMD;
300
301 typedef struct {
302 UINT16 Mp; /* Maximum Power */
303 UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */
304 UINT8 Mps : 1; /* Max Power Scale */
305 UINT8 Nops : 1; /* Non-Operational State */
306 UINT8 Rsvd2 : 6; /* Reserved as of Nvm Express 1.1 Spec */
307 UINT32 Enlat; /* Entry Latency */
308 UINT32 Exlat; /* Exit Latency */
309 UINT8 Rrt : 5; /* Relative Read Throughput */
310 UINT8 Rsvd3 : 3; /* Reserved as of Nvm Express 1.1 Spec */
311 UINT8 Rrl : 5; /* Relative Read Latency */
312 UINT8 Rsvd4 : 3; /* Reserved as of Nvm Express 1.1 Spec */
313 UINT8 Rwt : 5; /* Relative Write Throughput */
314 UINT8 Rsvd5 : 3; /* Reserved as of Nvm Express 1.1 Spec */
315 UINT8 Rwl : 5; /* Relative Write Latency */
316 UINT8 Rsvd6 : 3; /* Reserved as of Nvm Express 1.1 Spec */
317 UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
318 } NVME_PSDESCRIPTOR;
319
320 //
321 // Identify Controller Data
322 //
323 typedef struct {
324 //
325 // Controller Capabilities and Features 0-255
326 //
327 UINT16 Vid; /* PCI Vendor ID */
328 UINT16 Ssvid; /* PCI sub-system vendor ID */
329 UINT8 Sn[20]; /* Product serial number */
330
331 UINT8 Mn[40]; /* Product model number */
332 UINT8 Fr[8]; /* Firmware Revision */
333 UINT8 Rab; /* Recommended Arbitration Burst */
334 UINT8 Ieee_oui[3]; /* Organization Unique Identifier */
335 UINT8 Cmic; /* Multi-interface Capabilities */
336 UINT8 Mdts; /* Maximum Data Transfer Size */
337 UINT8 Cntlid[2]; /* Controller ID */
338 UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
339 //
340 // Admin Command Set Attributes
341 //
342 UINT16 Oacs; /* Optional Admin Command Support */
343 #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3
344 #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2
345 #define FORMAT_NVM_SUPPORTED BIT1
346 #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0
347 UINT8 Acl; /* Abort Command Limit */
348 UINT8 Aerl; /* Async Event Request Limit */
349 UINT8 Frmw; /* Firmware updates */
350 UINT8 Lpa; /* Log Page Attributes */
351 UINT8 Elpe; /* Error Log Page Entries */
352 UINT8 Npss; /* Number of Power States Support */
353 UINT8 Avscc; /* Admin Vendor Specific Command Configuration */
354 UINT8 Apsta; /* Autonomous Power State Transition Attributes */
355 //
356 // Below fields before Rsvd2 are defined in NVM Express 1.3 Spec
357 //
358 UINT16 Wctemp; /* Warning Composite Temperature Threshold */
359 UINT16 Cctemp; /* Critical Composite Temperature Threshold */
360 UINT16 Mtfa; /* Maximum Time for Firmware Activation */
361 UINT32 Hmpre; /* Host Memory Buffer Preferred Size */
362 UINT32 Hmmin; /* Host Memory Buffer Minimum Size */
363 UINT8 Tnvmcap[16]; /* Total NVM Capacity */
364 UINT8 Rsvd2[216]; /* Reserved as of NVM Express */
365 //
366 // NVM Command Set Attributes
367 //
368 UINT8 Sqes; /* Submission Queue Entry Size */
369 UINT8 Cqes; /* Completion Queue Entry Size */
370 UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
371 UINT32 Nn; /* Number of Namespaces */
372 UINT16 Oncs; /* Optional NVM Command Support */
373 UINT16 Fuses; /* Fused Operation Support */
374 UINT8 Fna; /* Format NVM Attributes */
375 UINT8 Vwc; /* Volatile Write Cache */
376 UINT16 Awun; /* Atomic Write Unit Normal */
377 UINT16 Awupf; /* Atomic Write Unit Power Fail */
378 UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
379 UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
380 UINT16 Acwu; /* Atomic Compare & Write Unit */
381 UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
382 UINT32 Sgls; /* SGL Support */
383 UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
384 //
385 // I/O Command set Attributes
386 //
387 UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
388 //
389 // Power State Descriptors
390 //
391 NVME_PSDESCRIPTOR PsDescriptor[32];
392
393 UINT8 VendorData[1024]; /* Vendor specific data */
394 } NVME_ADMIN_CONTROLLER_DATA;
395
396 typedef struct {
397 UINT16 Ms; /* Metadata Size */
398 UINT8 Lbads; /* LBA Data Size */
399 UINT8 Rp : 2; /* Relative Performance */
400 #define LBAF_RP_BEST 00b
401 #define LBAF_RP_BETTER 01b
402 #define LBAF_RP_GOOD 10b
403 #define LBAF_RP_DEGRADED 11b
404 UINT8 Rsvd1 : 6; /* Reserved as of Nvm Express 1.1 Spec */
405 } NVME_LBAFORMAT;
406
407 //
408 // Identify Namespace Data
409 //
410 typedef struct {
411 //
412 // NVM Command Set Specific
413 //
414 UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */
415 UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */
416 UINT64 Nuse; /* Namespace Utilization */
417 UINT8 Nsfeat; /* Namespace Features */
418 UINT8 Nlbaf; /* Number of LBA Formats */
419 UINT8 Flbas; /* Formatted LBA size */
420 UINT8 Mc; /* Metadata Capabilities */
421 UINT8 Dpc; /* End-to-end Data Protection capabilities */
422 UINT8 Dps; /* End-to-end Data Protection Type Settings */
423 UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
424 UINT8 Rescap; /* Reservation Capabilities */
425 UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */
426 UINT64 Eui64; /* IEEE Extended Unique Identifier */
427 //
428 // LBA Format
429 //
430 NVME_LBAFORMAT LbaFormat[16];
431
432 UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */
433 UINT8 VendorData[3712]; /* Vendor specific data */
434 } NVME_ADMIN_NAMESPACE_DATA;
435
436 //
437 // NvmExpress Admin Identify Cmd
438 //
439 typedef struct {
440 //
441 // CDW 10
442 //
443 UINT32 Cns : 2;
444 UINT32 Rsvd1 : 30;
445 } NVME_ADMIN_IDENTIFY;
446
447 //
448 // NvmExpress Admin Create I/O Completion Queue
449 //
450 typedef struct {
451 //
452 // CDW 10
453 //
454 UINT32 Qid : 16; /* Queue Identifier */
455 UINT32 Qsize : 16; /* Queue Size */
456
457 //
458 // CDW 11
459 //
460 UINT32 Pc : 1; /* Physically Contiguous */
461 UINT32 Ien : 1; /* Interrupts Enabled */
462 UINT32 Rsvd1 : 14; /* reserved as of Nvm Express 1.1 Spec */
463 UINT32 Iv : 16; /* Interrupt Vector for MSI-X or MSI*/
464 } NVME_ADMIN_CRIOCQ;
465
466 //
467 // NvmExpress Admin Create I/O Submission Queue
468 //
469 typedef struct {
470 //
471 // CDW 10
472 //
473 UINT32 Qid : 16; /* Queue Identifier */
474 UINT32 Qsize : 16; /* Queue Size */
475
476 //
477 // CDW 11
478 //
479 UINT32 Pc : 1; /* Physically Contiguous */
480 UINT32 Qprio : 2; /* Queue Priority */
481 UINT32 Rsvd1 : 13; /* Reserved as of Nvm Express 1.1 Spec */
482 UINT32 Cqid : 16; /* Completion Queue ID */
483 } NVME_ADMIN_CRIOSQ;
484
485 //
486 // NvmExpress Admin Delete I/O Completion Queue
487 //
488 typedef struct {
489 //
490 // CDW 10
491 //
492 UINT16 Qid;
493 UINT16 Rsvd1;
494 } NVME_ADMIN_DEIOCQ;
495
496 //
497 // NvmExpress Admin Delete I/O Submission Queue
498 //
499 typedef struct {
500 //
501 // CDW 10
502 //
503 UINT16 Qid;
504 UINT16 Rsvd1;
505 } NVME_ADMIN_DEIOSQ;
506
507 //
508 // NvmExpress Admin Abort Command
509 //
510 typedef struct {
511 //
512 // CDW 10
513 //
514 UINT32 Sqid : 16; /* Submission Queue identifier */
515 UINT32 Cid : 16; /* Command Identifier */
516 } NVME_ADMIN_ABORT;
517
518 //
519 // NvmExpress Admin Firmware Activate Command
520 //
521 typedef struct {
522 //
523 // CDW 10
524 //
525 UINT32 Fs : 3; /* Submission Queue identifier */
526 UINT32 Aa : 2; /* Command Identifier */
527 UINT32 Rsvd1 : 27;
528 } NVME_ADMIN_FIRMWARE_ACTIVATE;
529
530 //
531 // NvmExpress Admin Firmware Image Download Command
532 //
533 typedef struct {
534 //
535 // CDW 10
536 //
537 UINT32 Numd; /* Number of Dwords */
538 //
539 // CDW 11
540 //
541 UINT32 Ofst; /* Offset */
542 } NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
543
544 //
545 // NvmExpress Admin Get Features Command
546 //
547 typedef struct {
548 //
549 // CDW 10
550 //
551 UINT32 Fid : 8; /* Feature Identifier */
552 UINT32 Sel : 3; /* Select */
553 UINT32 Rsvd1 : 21;
554 } NVME_ADMIN_GET_FEATURES;
555
556 //
557 // NvmExpress Admin Get Log Page Command
558 //
559 typedef struct {
560 //
561 // CDW 10
562 //
563 UINT32 Lid : 8; /* Log Page Identifier */
564 #define LID_ERROR_INFO 0x1
565 #define LID_SMART_INFO 0x2
566 #define LID_FW_SLOT_INFO 0x3
567 UINT32 Rsvd1 : 8;
568 UINT32 Numd : 12; /* Number of Dwords */
569 UINT32 Rsvd2 : 4; /* Reserved as of Nvm Express 1.1 Spec */
570 } NVME_ADMIN_GET_LOG_PAGE;
571
572 //
573 // NvmExpress Admin Set Features Command
574 //
575 typedef struct {
576 //
577 // CDW 10
578 //
579 UINT32 Fid : 8; /* Feature Identifier */
580 UINT32 Rsvd1 : 23;
581 UINT32 Sv : 1; /* Save */
582 } NVME_ADMIN_SET_FEATURES;
583
584 //
585 // NvmExpress Admin Format NVM Command
586 //
587 typedef struct {
588 //
589 // CDW 10
590 //
591 UINT32 Lbaf : 4; /* LBA Format */
592 UINT32 Ms : 1; /* Metadata Settings */
593 UINT32 Pi : 3; /* Protection Information */
594 UINT32 Pil : 1; /* Protection Information Location */
595 UINT32 Ses : 3; /* Secure Erase Settings */
596 UINT32 Rsvd1 : 20;
597 } NVME_ADMIN_FORMAT_NVM;
598
599 //
600 // NvmExpress Admin Security Receive Command
601 //
602 typedef struct {
603 //
604 // CDW 10
605 //
606 UINT32 Rsvd1 : 8;
607 UINT32 Spsp : 16; /* SP Specific */
608 UINT32 Secp : 8; /* Security Protocol */
609 //
610 // CDW 11
611 //
612 UINT32 Al; /* Allocation Length */
613 } NVME_ADMIN_SECURITY_RECEIVE;
614
615 //
616 // NvmExpress Admin Security Send Command
617 //
618 typedef struct {
619 //
620 // CDW 10
621 //
622 UINT32 Rsvd1 : 8;
623 UINT32 Spsp : 16; /* SP Specific */
624 UINT32 Secp : 8; /* Security Protocol */
625 //
626 // CDW 11
627 //
628 UINT32 Tl; /* Transfer Length */
629 } NVME_ADMIN_SECURITY_SEND;
630
631 typedef union {
632 NVME_ADMIN_IDENTIFY Identify;
633 NVME_ADMIN_CRIOCQ CrIoCq;
634 NVME_ADMIN_CRIOSQ CrIoSq;
635 NVME_ADMIN_DEIOCQ DeIoCq;
636 NVME_ADMIN_DEIOSQ DeIoSq;
637 NVME_ADMIN_ABORT Abort;
638 NVME_ADMIN_FIRMWARE_ACTIVATE Activate;
639 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;
640 NVME_ADMIN_GET_FEATURES GetFeatures;
641 NVME_ADMIN_GET_LOG_PAGE GetLogPage;
642 NVME_ADMIN_SET_FEATURES SetFeatures;
643 NVME_ADMIN_FORMAT_NVM FormatNvm;
644 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;
645 NVME_ADMIN_SECURITY_SEND SecuritySend;
646 } NVME_ADMIN_CMD;
647
648 typedef struct {
649 UINT32 Cdw10;
650 UINT32 Cdw11;
651 UINT32 Cdw12;
652 UINT32 Cdw13;
653 UINT32 Cdw14;
654 UINT32 Cdw15;
655 } NVME_RAW;
656
657 typedef union {
658 NVME_ADMIN_CMD Admin; // Union of Admin commands
659 NVME_CMD Nvm; // Union of Nvm commands
660 NVME_RAW Raw;
661 } NVME_PAYLOAD;
662
663 //
664 // Submission Queue
665 //
666 typedef struct {
667 //
668 // CDW 0, Common to all commands
669 //
670 UINT8 Opc; // Opcode
671 UINT8 Fuse : 2; // Fused Operation
672 UINT8 Rsvd1 : 5;
673 UINT8 Psdt : 1; // PRP or SGL for Data Transfer
674 UINT16 Cid; // Command Identifier
675
676 //
677 // CDW 1
678 //
679 UINT32 Nsid; // Namespace Identifier
680
681 //
682 // CDW 2,3
683 //
684 UINT64 Rsvd2;
685
686 //
687 // CDW 4,5
688 //
689 UINT64 Mptr; // Metadata Pointer
690
691 //
692 // CDW 6-9
693 //
694 UINT64 Prp[2]; // First and second PRP entries
695
696 NVME_PAYLOAD Payload;
697 } NVME_SQ;
698
699 //
700 // Completion Queue
701 //
702 typedef struct {
703 //
704 // CDW 0
705 //
706 UINT32 Dword0;
707 //
708 // CDW 1
709 //
710 UINT32 Rsvd1;
711 //
712 // CDW 2
713 //
714 UINT16 Sqhd; // Submission Queue Head Pointer
715 UINT16 Sqid; // Submission Queue Identifier
716 //
717 // CDW 3
718 //
719 UINT16 Cid; // Command Identifier
720 UINT16 Pt : 1; // Phase Tag
721 UINT16 Sc : 8; // Status Code
722 UINT16 Sct : 3; // Status Code Type
723 UINT16 Rsvd2 : 2;
724 UINT16 Mo : 1; // More
725 UINT16 Dnr : 1; // Do Not Retry
726 } NVME_CQ;
727
728 //
729 // Nvm Express Admin cmd opcodes
730 //
731 #define NVME_ADMIN_DEIOSQ_CMD 0x00
732 #define NVME_ADMIN_CRIOSQ_CMD 0x01
733 #define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02
734 #define NVME_ADMIN_DEIOCQ_CMD 0x04
735 #define NVME_ADMIN_CRIOCQ_CMD 0x05
736 #define NVME_ADMIN_IDENTIFY_CMD 0x06
737 #define NVME_ADMIN_ABORT_CMD 0x08
738 #define NVME_ADMIN_SET_FEATURES_CMD 0x09
739 #define NVME_ADMIN_GET_FEATURES_CMD 0x0A
740 #define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C
741 #define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D
742 #define NVME_ADMIN_FW_COMMIT_CMD 0x10
743 #define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11
744 #define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15
745 #define NVME_ADMIN_FORMAT_NVM_CMD 0x80
746 #define NVME_ADMIN_SECURITY_SEND_CMD 0x81
747 #define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82
748
749 #define NVME_IO_FLUSH_OPC 0
750 #define NVME_IO_WRITE_OPC 1
751 #define NVME_IO_READ_OPC 2
752
753 typedef enum {
754 DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,
755 CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,
756 GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,
757 DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,
758 CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,
759 IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,
760 AbortOpcode = NVME_ADMIN_ABORT_CMD,
761 SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,
762 GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,
763 AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,
764 NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,
765 FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,
766 FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,
767 NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,
768 FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,
769 SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,
770 SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD
771 } NVME_ADMIN_COMMAND_OPCODE;
772
773 //
774 // Controller or Namespace Structure (CNS) field
775 // (ref. spec. v1.1 figure 82).
776 //
777 typedef enum {
778 IdentifyNamespaceCns = 0x0,
779 IdentifyControllerCns = 0x1,
780 IdentifyActiveNsListCns = 0x2
781 } NVME_ADMIN_IDENTIFY_CNS;
782
783 //
784 // Commit Action
785 // (ref. spec. 1.1 figure 60).
786 //
787 typedef enum {
788 ActivateActionReplace = 0x0,
789 ActivateActionReplaceActivate = 0x1,
790 ActivateActionActivate = 0x2
791 } NVME_FW_ACTIVATE_ACTION;
792
793 //
794 // Firmware Slot
795 // (ref. spec. 1.1 Figure 60).
796 //
797 typedef enum {
798 FirmwareSlotCtrlChooses = 0x0,
799 FirmwareSlot1 = 0x1,
800 FirmwareSlot2 = 0x2,
801 FirmwareSlot3 = 0x3,
802 FirmwareSlot4 = 0x4,
803 FirmwareSlot5 = 0x5,
804 FirmwareSlot6 = 0x6,
805 FirmwareSlot7 = 0x7
806 } NVME_FW_ACTIVATE_SLOT;
807
808 //
809 // Get Log Page ? Log Page Identifiers
810 // (ref. spec. v1.1 Figure 73).
811 //
812 typedef enum {
813 ErrorInfoLogID = LID_ERROR_INFO,
814 SmartHealthInfoLogID = LID_SMART_INFO,
815 FirmwareSlotInfoLogID = LID_FW_SLOT_INFO
816 } NVME_LOG_ID;
817
818 //
819 // Get Log Page ? Firmware Slot Information Log
820 // (ref. spec. v1.1 Figure 77).
821 //
822 typedef struct {
823 //
824 // Indicates the firmware slot from which the actively running firmware revision was loaded.
825 //
826 UINT8 ActivelyRunningFwSlot : 3;
827 UINT8 : 1;
828 //
829 // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.
830 //
831 UINT8 NextActiveFwSlot : 3;
832 UINT8 : 1;
833 } NVME_ACTIVE_FW_INFO;
834
835 //
836 // Get Log Page ? Firmware Slot Information Log
837 // (ref. spec. v1.1 Figure 77).
838 //
839 typedef struct {
840 //
841 // Specifies information about the active firmware revision.
842 // s
843 NVME_ACTIVE_FW_INFO ActiveFwInfo;
844 UINT8 Reserved1[7];
845 //
846 // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.
847 //
848 CHAR8 FwRevisionSlot[7][8];
849 UINT8 Reserved2[448];
850 } NVME_FW_SLOT_INFO_LOG;
851
852 //
853 // SMART / Health Information (Log Identifier 02h)
854 // (ref. spec. v1.1 5.10.1.2)
855 //
856 typedef struct {
857 //
858 // This field indicates critical warnings for the state of the controller.
859 //
860 UINT8 CriticalWarningAvailableSpare : 1;
861 UINT8 CriticalWarningTemperature : 1;
862 UINT8 CriticalWarningReliability : 1;
863 UINT8 CriticalWarningMediaReadOnly : 1;
864 UINT8 CriticalWarningVolatileBackup : 1;
865 UINT8 CriticalWarningReserved : 3;
866 //
867 // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.
868 //
869 UINT16 CompositeTemp;
870 //
871 // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.
872 //
873 UINT8 AvailableSpare;
874 //
875 // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).
876 //
877 UINT8 AvailableSpareThreshold;
878 //
879 // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
880 //
881 UINT8 PercentageUsed;
882 UINT8 Reserved1[26];
883 //
884 // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.
885 //
886 UINT8 DataUnitsRead[16];
887 //
888 // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.
889 //
890 UINT8 DataUnitsWritten[16];
891 //
892 // Contains the number of read commands completed by the controller.
893 //
894 UINT8 HostReadCommands[16];
895 //
896 // Contains the number of write commands completed by the controller.
897 //
898 UINT8 HostWriteCommands[16];
899 //
900 // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.
901 //
902 UINT8 ControllerBusyTime[16];
903 //
904 // Contains the number of power cycles.
905 //
906 UINT8 PowerCycles[16];
907 //
908 // Contains the number of power-on hours.
909 //
910 UINT8 PowerOnHours[16];
911 //
912 // Contains the number of unsafe shutdowns.
913 //
914 UINT8 UnsafeShutdowns[16];
915 //
916 // Contains the number of occurrences where the controller detected an unrecovered data integrity error.
917 //
918 UINT8 MediaAndDataIntegrityErrors[16];
919 //
920 // Contains the number of Error Information log entries over the life of the controller.
921 //
922 UINT8 NumberErrorInformationLogEntries[16];
923 //
924 // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
925 //
926 UINT32 WarningCompositeTemperatureTime;
927 //
928 // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
929 //
930 UINT32 CriticalCompositeTemperatureTime;
931 //
932 // Contains the current temperature in degrees Kelvin reported by the temperature sensor. An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.
933 //
934 UINT16 TemperatureSensor[8];
935 UINT8 Reserved2[296];
936 } NVME_SMART_HEALTH_INFO_LOG;
937
938 #pragma pack()
939
940 #endif
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