MdePkg/Include/IndustryStandard/Nvme.h

   1 /** @file
   2   Definitions based on NVMe spec. version 1.1.
   3
   4   (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   @par Specification Reference:
  14   NVMe Specification 1.1
  15
  16 **/
  17
  18 #ifndef __NVM_E_H__
  19 #define __NVM_E_H__
  20
  21 #pragma pack(1)
  22
  23 //
  24 // controller register offsets
  25 //
  26 #define NVME_CAP_OFFSET          0x0000  // Controller Capabilities
  27 #define NVME_VER_OFFSET          0x0008  // Version
  28 #define NVME_INTMS_OFFSET        0x000c  // Interrupt Mask Set
  29 #define NVME_INTMC_OFFSET        0x0010  // Interrupt Mask Clear
  30 #define NVME_CC_OFFSET           0x0014  // Controller Configuration
  31 #define NVME_CSTS_OFFSET         0x001c  // Controller Status
  32 #define NVME_NSSR_OFFSET         0x0020  // NVM Subsystem Reset
  33 #define NVME_AQA_OFFSET          0x0024  // Admin Queue Attributes
  34 #define NVME_ASQ_OFFSET          0x0028  // Admin Submission Queue Base Address
  35 #define NVME_ACQ_OFFSET          0x0030  // Admin Completion Queue Base Address
  36 #define NVME_SQ0_OFFSET          0x1000  // Submission Queue 0 (admin) Tail Doorbell
  37 #define NVME_CQ0_OFFSET          0x1004  // Completion Queue 0 (admin) Head Doorbell
  38
  39 //
  40 // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
  41 // Get the doorbell stride bit shift value from the controller capabilities.
  42 //
  43 #define NVME_SQTDBL_OFFSET(QID, DSTRD)    0x1000 + ((2 * (QID)) * (4 << (DSTRD)))       // Submission Queue y (NVM) Tail Doorbell
  44 #define NVME_CQHDBL_OFFSET(QID, DSTRD)    0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
  45
  46
  47 #pragma pack(1)
  48
  49 //
  50 // 3.1.1 Offset 00h: CAP - Controller Capabilities
  51 //
  52 typedef struct {
  53   UINT16 Mqes;      // Maximum Queue Entries Supported
  54   UINT8  Cqr:1;     // Contiguous Queues Required
  55   UINT8  Ams:2;     // Arbitration Mechanism Supported
  56   UINT8  Rsvd1:5;
  57   UINT8  To;        // Timeout
  58   UINT16 Dstrd:4;
  59   UINT16 Nssrs:1;   // NVM Subsystem Reset Supported NSSRS
  60   UINT16 Css:4;     // Command Sets Supported - Bit 37
  61   UINT16 Rsvd3:7;
  62   UINT8  Mpsmin:4;
  63   UINT8  Mpsmax:4;
  64   UINT8  Rsvd4;
  65 } NVME_CAP;
  66
  67 //
  68 // 3.1.2 Offset 08h: VS - Version
  69 //
  70 typedef struct {
  71   UINT16 Mnr;       // Minor version number
  72   UINT16 Mjr;       // Major version number
  73 } NVME_VER;
  74
  75 //
  76 // 3.1.5 Offset 14h: CC - Controller Configuration
  77 //
  78 typedef struct {
  79   UINT16 En:1;       // Enable
  80   UINT16 Rsvd1:3;
  81   UINT16 Css:3;      // I/O Command Set Selected
  82   UINT16 Mps:4;      // Memory Page Size
  83   UINT16 Ams:3;      // Arbitration Mechanism Selected
  84   UINT16 Shn:2;      // Shutdown Notification
  85   UINT8  Iosqes:4;   // I/O Submission Queue Entry Size
  86   UINT8  Iocqes:4;   // I/O Completion Queue Entry Size
  87   UINT8  Rsvd2;
  88 } NVME_CC;
  89
  90 //
  91 // 3.1.6 Offset 1Ch: CSTS - Controller Status
  92 //
  93 typedef struct {
  94   UINT32 Rdy:1;      // Ready
  95   UINT32 Cfs:1;      // Controller Fatal Status
  96   UINT32 Shst:2;     // Shutdown Status
  97   UINT32 Nssro:1;    // NVM Subsystem Reset Occurred
  98   UINT32 Rsvd1:27;
  99 } NVME_CSTS;
 100
 101 //
 102 // 3.1.8 Offset 24h: AQA - Admin Queue Attributes
 103 //
 104 typedef struct {
 105   UINT16 Asqs:12;    // Submission Queue Size
 106   UINT16 Rsvd1:4;
 107   UINT16 Acqs:12;    // Completion Queue Size
 108   UINT16 Rsvd2:4;
 109 } NVME_AQA;
 110
 111 //
 112 // 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
 113 //
 114 #define NVME_ASQ      UINT64
 115 //
 116 // 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
 117 //
 118 #define NVME_ACQ      UINT64
 119
 120 //
 121 // 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
 122 //
 123 typedef struct {
 124   UINT16 Sqt;
 125   UINT16 Rsvd1;
 126 } NVME_SQTDBL;
 127
 128 //
 129 // 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
 130 //
 131 typedef struct {
 132   UINT16 Cqh;
 133   UINT16 Rsvd1;
 134 } NVME_CQHDBL;
 135
 136 //
 137 // NVM command set structures
 138 //
 139 // Read Command
 140 //
 141 typedef struct {
 142   //
 143   // CDW 10, 11
 144   //
 145   UINT64 Slba;                /* Starting Sector Address */
 146   //
 147   // CDW 12
 148   //
 149   UINT16 Nlb;                 /* Number of Sectors */
 150   UINT16 Rsvd1:10;
 151   UINT16 Prinfo:4;            /* Protection Info Check */
 152   UINT16 Fua:1;               /* Force Unit Access */
 153   UINT16 Lr:1;                /* Limited Retry */
 154   //
 155   // CDW 13
 156   //
 157   UINT32 Af:4;                /* Access Frequency */
 158   UINT32 Al:2;                /* Access Latency */
 159   UINT32 Sr:1;                /* Sequential Request */
 160   UINT32 In:1;                /* Incompressible */
 161   UINT32 Rsvd2:24;
 162   //
 163   // CDW 14
 164   //
 165   UINT32 Eilbrt;              /* Expected Initial Logical Block Reference Tag */
 166   //
 167   // CDW 15
 168   //
 169   UINT16 Elbat;               /* Expected Logical Block Application Tag */
 170   UINT16 Elbatm;              /* Expected Logical Block Application Tag Mask */
 171 } NVME_READ;
 172
 173 //
 174 // Write Command
 175 //
 176 typedef struct {
 177   //
 178   // CDW 10, 11
 179   //
 180   UINT64 Slba;                /* Starting Sector Address */
 181   //
 182   // CDW 12
 183   //
 184   UINT16 Nlb;                 /* Number of Sectors */
 185   UINT16 Rsvd1:10;
 186   UINT16 Prinfo:4;            /* Protection Info Check */
 187   UINT16 Fua:1;               /* Force Unit Access */
 188   UINT16 Lr:1;                /* Limited Retry */
 189   //
 190   // CDW 13
 191   //
 192   UINT32 Af:4;                /* Access Frequency */
 193   UINT32 Al:2;                /* Access Latency */
 194   UINT32 Sr:1;                /* Sequential Request */
 195   UINT32 In:1;                /* Incompressible */
 196   UINT32 Rsvd2:24;
 197   //
 198   // CDW 14
 199   //
 200   UINT32 Ilbrt;               /* Initial Logical Block Reference Tag */
 201   //
 202   // CDW 15
 203   //
 204   UINT16 Lbat;                /* Logical Block Application Tag */
 205   UINT16 Lbatm;               /* Logical Block Application Tag Mask */
 206 } NVME_WRITE;
 207
 208 //
 209 // Flush
 210 //
 211 typedef struct {
 212   //
 213   // CDW 10
 214   //
 215   UINT32 Flush;               /* Flush */
 216 } NVME_FLUSH;
 217
 218 //
 219 // Write Uncorrectable command
 220 //
 221 typedef struct {
 222   //
 223   // CDW 10, 11
 224   //
 225   UINT64 Slba;                /* Starting LBA */
 226   //
 227   // CDW 12
 228   //
 229   UINT32 Nlb:16;              /* Number of  Logical Blocks */
 230   UINT32 Rsvd1:16;
 231 } NVME_WRITE_UNCORRECTABLE;
 232
 233 //
 234 // Write Zeroes command
 235 //
 236 typedef struct {
 237   //
 238   // CDW 10, 11
 239   //
 240   UINT64 Slba;                /* Starting LBA */
 241   //
 242   // CDW 12
 243   //
 244   UINT16 Nlb;                 /* Number of Logical Blocks */
 245   UINT16 Rsvd1:10;
 246   UINT16 Prinfo:4;            /* Protection Info Check */
 247   UINT16 Fua:1;               /* Force Unit Access */
 248   UINT16 Lr:1;                /* Limited Retry */
 249   //
 250   // CDW 13
 251   //
 252   UINT32 Rsvd2;
 253   //
 254   // CDW 14
 255   //
 256   UINT32 Ilbrt;               /* Initial Logical Block Reference Tag */
 257   //
 258   // CDW 15
 259   //
 260   UINT16 Lbat;                /* Logical Block Application Tag */
 261   UINT16 Lbatm;               /* Logical Block Application Tag Mask */
 262 } NVME_WRITE_ZEROES;
 263
 264 //
 265 // Compare command
 266 //
 267 typedef struct {
 268   //
 269   // CDW 10, 11
 270   //
 271   UINT64 Slba;                /* Starting LBA */
 272   //
 273   // CDW 12
 274   //
 275   UINT16 Nlb;                 /* Number of Logical Blocks */
 276   UINT16 Rsvd1:10;
 277   UINT16 Prinfo:4;            /* Protection Info Check */
 278   UINT16 Fua:1;               /* Force Unit Access */
 279   UINT16 Lr:1;                /* Limited Retry */
 280   //
 281   // CDW 13
 282   //
 283   UINT32 Rsvd2;
 284   //
 285   // CDW 14
 286   //
 287   UINT32 Eilbrt;              /* Expected Initial Logical Block Reference Tag */
 288   //
 289   // CDW 15
 290   //
 291   UINT16 Elbat;               /* Expected Logical Block Application Tag */
 292   UINT16 Elbatm;              /* Expected Logical Block Application Tag Mask */
 293 } NVME_COMPARE;
 294
 295 typedef union {
 296   NVME_READ                   Read;
 297   NVME_WRITE                  Write;
 298   NVME_FLUSH                  Flush;
 299   NVME_WRITE_UNCORRECTABLE    WriteUncorrectable;
 300   NVME_WRITE_ZEROES           WriteZeros;
 301   NVME_COMPARE                Compare;
 302 } NVME_CMD;
 303
 304 typedef struct {
 305   UINT16 Mp;                /* Maximum Power */
 306   UINT8  Rsvd1;             /* Reserved as of Nvm Express 1.1 Spec */
 307   UINT8  Mps:1;             /* Max Power Scale */
 308   UINT8  Nops:1;            /* Non-Operational State */
 309   UINT8  Rsvd2:6;           /* Reserved as of Nvm Express 1.1 Spec */
 310   UINT32 Enlat;             /* Entry Latency */
 311   UINT32 Exlat;             /* Exit Latency */
 312   UINT8  Rrt:5;             /* Relative Read Throughput */
 313   UINT8  Rsvd3:3;           /* Reserved as of Nvm Express 1.1 Spec */
 314   UINT8  Rrl:5;             /* Relative Read Leatency */
 315   UINT8  Rsvd4:3;           /* Reserved as of Nvm Express 1.1 Spec */
 316   UINT8  Rwt:5;             /* Relative Write Throughput */
 317   UINT8  Rsvd5:3;           /* Reserved as of Nvm Express 1.1 Spec */
 318   UINT8  Rwl:5;             /* Relative Write Leatency */
 319   UINT8  Rsvd6:3;           /* Reserved as of Nvm Express 1.1 Spec */
 320   UINT8  Rsvd7[16];         /* Reserved as of Nvm Express 1.1 Spec */
 321 } NVME_PSDESCRIPTOR;
 322
 323 //
 324 //  Identify Controller Data
 325 //
 326 typedef struct {
 327   //
 328   // Controller Capabilities and Features 0-255
 329   //
 330   UINT16 Vid;                 /* PCI Vendor ID */
 331   UINT16 Ssvid;               /* PCI sub-system vendor ID */
 332   UINT8  Sn[20];              /* Product serial number */
 333
 334   UINT8  Mn[40];              /* Proeduct model number */
 335   UINT8  Fr[8];               /* Firmware Revision */
 336   UINT8  Rab;                 /* Recommended Arbitration Burst */
 337   UINT8  Ieee_oui[3];         /* Organization Unique Identifier */
 338   UINT8  Cmic;                /* Multi-interface Capabilities */
 339   UINT8  Mdts;                /* Maximum Data Transfer Size */
 340   UINT8  Cntlid[2];           /* Controller ID */
 341   UINT8  Rsvd1[176];          /* Reserved as of Nvm Express 1.1 Spec */
 342   //
 343   // Admin Command Set Attributes
 344   //
 345   UINT16 Oacs;                /* Optional Admin Command Support */
 346     #define NAMESPACE_MANAGEMENT_SUPPORTED  BIT3
 347     #define FW_DOWNLOAD_ACTIVATE_SUPPORTED  BIT2
 348     #define FORMAT_NVM_SUPPORTED            BIT1
 349     #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0
 350   UINT8  Acl;                 /* Abort Command Limit */
 351   UINT8  Aerl;                /* Async Event Request Limit */
 352   UINT8  Frmw;                /* Firmware updates */
 353   UINT8  Lpa;                 /* Log Page Attributes */
 354   UINT8  Elpe;                /* Error Log Page Entries */
 355   UINT8  Npss;                /* Number of Power States Support */
 356   UINT8  Avscc;               /* Admin Vendor Specific Command Configuration */
 357   UINT8  Apsta;               /* Autonomous Power State Transition Attributes */
 358   UINT8  Rsvd2[246];          /* Reserved as of Nvm Express 1.1 Spec */
 359   //
 360   // NVM Command Set Attributes
 361   //
 362   UINT8  Sqes;                /* Submission Queue Entry Size */
 363   UINT8  Cqes;                /* Completion Queue Entry Size */
 364   UINT16 Rsvd3;               /* Reserved as of Nvm Express 1.1 Spec */
 365   UINT32 Nn;                  /* Number of Namespaces */
 366   UINT16 Oncs;                /* Optional NVM Command Support */
 367   UINT16 Fuses;               /* Fused Operation Support */
 368   UINT8  Fna;                 /* Format NVM Attributes */
 369   UINT8  Vwc;                 /* Volatile Write Cache */
 370   UINT16 Awun;                /* Atomic Write Unit Normal */
 371   UINT16 Awupf;               /* Atomic Write Unit Power Fail */
 372   UINT8  Nvscc;               /* NVM Vendor Specific Command Configuration */
 373   UINT8  Rsvd4;               /* Reserved as of Nvm Express 1.1 Spec */
 374   UINT16 Acwu;                /* Atomic Compare & Write Unit */
 375   UINT16 Rsvd5;               /* Reserved as of Nvm Express 1.1 Spec */
 376   UINT32 Sgls;                /* SGL Support  */
 377   UINT8  Rsvd6[164];          /* Reserved as of Nvm Express 1.1 Spec */
 378   //
 379   // I/O Command set Attributes
 380   //
 381   UINT8 Rsvd7[1344];          /* Reserved as of Nvm Express 1.1 Spec */
 382   //
 383   // Power State Descriptors
 384   //
 385   NVME_PSDESCRIPTOR PsDescriptor[32];
 386
 387   UINT8  VendorData[1024];    /* Vendor specific data */
 388 } NVME_ADMIN_CONTROLLER_DATA;
 389
 390 typedef struct {
 391   UINT16 Ms;                /* Metadata Size */
 392   UINT8  Lbads;             /* LBA Data Size */
 393   UINT8  Rp:2;              /* Relative Performance */
 394     #define LBAF_RP_BEST      00b
 395     #define LBAF_RP_BETTER    01b
 396     #define LBAF_RP_GOOD      10b
 397     #define LBAF_RP_DEGRADED  11b
 398   UINT8  Rsvd1:6;           /* Reserved as of Nvm Express 1.1 Spec */
 399 } NVME_LBAFORMAT;
 400
 401 //
 402 // Identify Namespace Data
 403 //
 404 typedef struct {
 405   //
 406   // NVM Command Set Specific
 407   //
 408   UINT64 Nsze;                /* Namespace Size (total number of blocks in formatted namespace) */
 409   UINT64 Ncap;                /* Namespace Capacity (max number of logical blocks) */
 410   UINT64 Nuse;                /* Namespace Utilization */
 411   UINT8  Nsfeat;              /* Namespace Features */
 412   UINT8  Nlbaf;               /* Number of LBA Formats */
 413   UINT8  Flbas;               /* Formatted LBA size */
 414   UINT8  Mc;                  /* Metadata Capabilities */
 415   UINT8  Dpc;                 /* End-to-end Data Protection capabilities */
 416   UINT8  Dps;                 /* End-to-end Data Protection Type Settings */
 417   UINT8  Nmic;                /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
 418   UINT8  Rescap;              /* Reservation Capabilities */
 419   UINT8  Rsvd1[88];           /* Reserved as of Nvm Express 1.1 Spec */
 420   UINT64 Eui64;               /* IEEE Extended Unique Identifier */
 421   //
 422   // LBA Format
 423   //
 424   NVME_LBAFORMAT LbaFormat[16];
 425
 426   UINT8 Rsvd2[192];           /* Reserved as of Nvm Express 1.1 Spec */
 427   UINT8 VendorData[3712];     /* Vendor specific data */
 428 } NVME_ADMIN_NAMESPACE_DATA;
 429
 430 //
 431 // NvmExpress Admin Identify Cmd
 432 //
 433 typedef struct {
 434   //
 435   // CDW 10
 436   //
 437   UINT32 Cns:2;
 438   UINT32 Rsvd1:30;
 439 } NVME_ADMIN_IDENTIFY;
 440
 441 //
 442 // NvmExpress Admin Create I/O Completion Queue
 443 //
 444 typedef struct {
 445   //
 446   // CDW 10
 447   //
 448   UINT32 Qid:16;              /* Queue Identifier */
 449   UINT32 Qsize:16;            /* Queue Size */
 450
 451   //
 452   // CDW 11
 453   //
 454   UINT32 Pc:1;                /* Physically Contiguous */
 455   UINT32 Ien:1;               /* Interrupts Enabled */
 456   UINT32 Rsvd1:14;            /* reserved as of Nvm Express 1.1 Spec */
 457   UINT32 Iv:16;               /* Interrupt Vector for MSI-X or MSI*/
 458 } NVME_ADMIN_CRIOCQ;
 459
 460 //
 461 // NvmExpress Admin Create I/O Submission Queue
 462 //
 463 typedef struct {
 464   //
 465   // CDW 10
 466   //
 467   UINT32 Qid:16;              /* Queue Identifier */
 468   UINT32 Qsize:16;            /* Queue Size */
 469
 470   //
 471   // CDW 11
 472   //
 473   UINT32 Pc:1;                /* Physically Contiguous */
 474   UINT32 Qprio:2;             /* Queue Priority */
 475   UINT32 Rsvd1:13;            /* Reserved as of Nvm Express 1.1 Spec */
 476   UINT32 Cqid:16;             /* Completion Queue ID */
 477 } NVME_ADMIN_CRIOSQ;
 478
 479 //
 480 // NvmExpress Admin Delete I/O Completion Queue
 481 //
 482 typedef struct {
 483   //
 484   // CDW 10
 485   //
 486   UINT16 Qid;
 487   UINT16 Rsvd1;
 488 } NVME_ADMIN_DEIOCQ;
 489
 490 //
 491 // NvmExpress Admin Delete I/O Submission Queue
 492 //
 493 typedef struct {
 494   //
 495   // CDW 10
 496   //
 497   UINT16 Qid;
 498   UINT16 Rsvd1;
 499 } NVME_ADMIN_DEIOSQ;
 500
 501 //
 502 // NvmExpress Admin Abort Command
 503 //
 504 typedef struct {
 505   //
 506   // CDW 10
 507   //
 508   UINT32 Sqid:16;             /* Submission Queue identifier */
 509   UINT32 Cid:16;              /* Command Identifier */
 510 } NVME_ADMIN_ABORT;
 511
 512 //
 513 // NvmExpress Admin Firmware Activate Command
 514 //
 515 typedef struct {
 516   //
 517   // CDW 10
 518   //
 519   UINT32 Fs:3;                /* Submission Queue identifier */
 520   UINT32 Aa:2;                /* Command Identifier */
 521   UINT32 Rsvd1:27;
 522 } NVME_ADMIN_FIRMWARE_ACTIVATE;
 523
 524 //
 525 // NvmExpress Admin Firmware Image Download Command
 526 //
 527 typedef struct {
 528   //
 529   // CDW 10
 530   //
 531   UINT32 Numd;                /* Number of Dwords */
 532   //
 533   // CDW 11
 534   //
 535   UINT32 Ofst;                /* Offset */
 536 } NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
 537
 538 //
 539 // NvmExpress Admin Get Features Command
 540 //
 541 typedef struct {
 542   //
 543   // CDW 10
 544   //
 545   UINT32 Fid:8;                /* Feature Identifier */
 546   UINT32 Sel:3;                /* Select */
 547   UINT32 Rsvd1:21;
 548 } NVME_ADMIN_GET_FEATURES;
 549
 550 //
 551 // NvmExpress Admin Get Log Page Command
 552 //
 553 typedef struct {
 554   //
 555   // CDW 10
 556   //
 557   UINT32 Lid:8;               /* Log Page Identifier */
 558     #define LID_ERROR_INFO   0x1
 559     #define LID_SMART_INFO   0x2
 560     #define LID_FW_SLOT_INFO 0x3
 561   UINT32 Rsvd1:8;
 562   UINT32 Numd:12;             /* Number of Dwords */
 563   UINT32 Rsvd2:4;             /* Reserved as of Nvm Express 1.1 Spec */
 564 } NVME_ADMIN_GET_LOG_PAGE;
 565
 566 //
 567 // NvmExpress Admin Set Features Command
 568 //
 569 typedef struct {
 570   //
 571   // CDW 10
 572   //
 573   UINT32 Fid:8;               /* Feature Identifier */
 574   UINT32 Rsvd1:23;
 575   UINT32 Sv:1;                /* Save */
 576 } NVME_ADMIN_SET_FEATURES;
 577
 578 //
 579 // NvmExpress Admin Format NVM Command
 580 //
 581 typedef struct {
 582   //
 583   // CDW 10
 584   //
 585   UINT32 Lbaf:4;              /* LBA Format */
 586   UINT32 Ms:1;                /* Metadata Settings */
 587   UINT32 Pi:3;                /* Protection Information */
 588   UINT32 Pil:1;               /* Protection Information Location */
 589   UINT32 Ses:3;               /* Secure Erase Settings */
 590   UINT32 Rsvd1:20;
 591 } NVME_ADMIN_FORMAT_NVM;
 592
 593 //
 594 // NvmExpress Admin Security Receive Command
 595 //
 596 typedef struct {
 597   //
 598   // CDW 10
 599   //
 600   UINT32 Rsvd1:8;
 601   UINT32 Spsp:16;             /* SP Specific */
 602   UINT32 Secp:8;              /* Security Protocol */
 603   //
 604   // CDW 11
 605   //
 606   UINT32 Al;                  /* Allocation Length */
 607 } NVME_ADMIN_SECURITY_RECEIVE;
 608
 609 //
 610 // NvmExpress Admin Security Send Command
 611 //
 612 typedef struct {
 613   //
 614   // CDW 10
 615   //
 616   UINT32 Rsvd1:8;
 617   UINT32 Spsp:16;             /* SP Specific */
 618   UINT32 Secp:8;              /* Security Protocol */
 619   //
 620   // CDW 11
 621   //
 622   UINT32 Tl;                  /* Transfer Length */
 623 } NVME_ADMIN_SECURITY_SEND;
 624
 625 typedef union {
 626   NVME_ADMIN_IDENTIFY                   Identify;
 627   NVME_ADMIN_CRIOCQ                     CrIoCq;
 628   NVME_ADMIN_CRIOSQ                     CrIoSq;
 629   NVME_ADMIN_DEIOCQ                     DeIoCq;
 630   NVME_ADMIN_DEIOSQ                     DeIoSq;
 631   NVME_ADMIN_ABORT                      Abort;
 632   NVME_ADMIN_FIRMWARE_ACTIVATE          Activate;
 633   NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD    FirmwareImageDownload;
 634   NVME_ADMIN_GET_FEATURES               GetFeatures;
 635   NVME_ADMIN_GET_LOG_PAGE               GetLogPage;
 636   NVME_ADMIN_SET_FEATURES               SetFeatures;
 637   NVME_ADMIN_FORMAT_NVM                 FormatNvm;
 638   NVME_ADMIN_SECURITY_RECEIVE           SecurityReceive;
 639   NVME_ADMIN_SECURITY_SEND              SecuritySend;
 640 } NVME_ADMIN_CMD;
 641
 642 typedef struct {
 643   UINT32 Cdw10;
 644   UINT32 Cdw11;
 645   UINT32 Cdw12;
 646   UINT32 Cdw13;
 647   UINT32 Cdw14;
 648   UINT32 Cdw15;
 649 } NVME_RAW;
 650
 651 typedef union {
 652   NVME_ADMIN_CMD Admin;   // Union of Admin commands
 653   NVME_CMD       Nvm;     // Union of Nvm commands
 654   NVME_RAW       Raw;
 655 } NVME_PAYLOAD;
 656
 657 //
 658 // Submission Queue
 659 //
 660 typedef struct {
 661   //
 662   // CDW 0, Common to all comnmands
 663   //
 664   UINT8  Opc;               // Opcode
 665   UINT8  Fuse:2;            // Fused Operation
 666   UINT8  Rsvd1:5;
 667   UINT8  Psdt:1;            // PRP or SGL for Data Transfer
 668   UINT16 Cid;               // Command Identifier
 669
 670   //
 671   // CDW 1
 672   //
 673   UINT32 Nsid;              // Namespace Identifier
 674
 675   //
 676   // CDW 2,3
 677   //
 678   UINT64 Rsvd2;
 679
 680   //
 681   // CDW 4,5
 682   //
 683   UINT64 Mptr;              // Metadata Pointer
 684
 685   //
 686   // CDW 6-9
 687   //
 688   UINT64 Prp[2];            // First and second PRP entries
 689
 690   NVME_PAYLOAD Payload;
 691
 692 } NVME_SQ;
 693
 694 //
 695 // Completion Queue
 696 //
 697 typedef struct {
 698   //
 699   // CDW 0
 700   //
 701   UINT32 Dword0;
 702   //
 703   // CDW 1
 704   //
 705   UINT32 Rsvd1;
 706   //
 707   // CDW 2
 708   //
 709   UINT16 Sqhd;              // Submission Queue Head Pointer
 710   UINT16 Sqid;              // Submission Queue Identifier
 711   //
 712   // CDW 3
 713   //
 714   UINT16 Cid;               // Command Identifier
 715   UINT16 Pt:1;              // Phase Tag
 716   UINT16 Sc:8;              // Status Code
 717   UINT16 Sct:3;             // Status Code Type
 718   UINT16 Rsvd2:2;
 719   UINT16 Mo:1;              // More
 720   UINT16 Dnr:1;             // Do Not Retry
 721 } NVME_CQ;
 722
 723 //
 724 // Nvm Express Admin cmd opcodes
 725 //
 726 #define NVME_ADMIN_DEIOSQ_CMD                0x00
 727 #define NVME_ADMIN_CRIOSQ_CMD                0x01
 728 #define NVME_ADMIN_GET_LOG_PAGE_CMD          0x02
 729 #define NVME_ADMIN_DEIOCQ_CMD                0x04
 730 #define NVME_ADMIN_CRIOCQ_CMD                0x05
 731 #define NVME_ADMIN_IDENTIFY_CMD              0x06
 732 #define NVME_ADMIN_ABORT_CMD                 0x08
 733 #define NVME_ADMIN_SET_FEATURES_CMD          0x09
 734 #define NVME_ADMIN_GET_FEATURES_CMD          0x0A
 735 #define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD   0x0C
 736 #define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD   0x0D
 737 #define NVME_ADMIN_FW_COMMIT_CMD             0x10
 738 #define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD     0x11
 739 #define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD   0x15
 740 #define NVME_ADMIN_FORMAT_NVM_CMD            0x80
 741 #define NVME_ADMIN_SECURITY_SEND_CMD         0x81
 742 #define NVME_ADMIN_SECURITY_RECEIVE_CMD      0x82
 743
 744 #define NVME_IO_FLUSH_OPC                    0
 745 #define NVME_IO_WRITE_OPC                    1
 746 #define NVME_IO_READ_OPC                     2
 747
 748 typedef enum {
 749   DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,
 750   CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,
 751   GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,
 752   DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,
 753   CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,
 754   IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,
 755   AbortOpcode = NVME_ADMIN_ABORT_CMD,
 756   SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,
 757   GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,
 758   AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,
 759   NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,
 760   FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,
 761   FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,
 762   NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,
 763   FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,
 764   SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,
 765   SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD
 766 } NVME_ADMIN_COMMAND_OPCODE;
 767
 768 //
 769 // Controller or Namespace Structure (CNS) field
 770 // (ref. spec. v1.1 figure 82).
 771 //
 772 typedef enum {
 773 IdentifyNamespaceCns = 0x0,
 774 IdentifyControllerCns = 0x1,
 775 IdentifyActiveNsListCns = 0x2
 776 } NVME_ADMIN_IDENTIFY_CNS;
 777
 778 //
 779 // Commit Action
 780 // (ref. spec. 1.1 figure 60).
 781 //
 782 typedef enum {
 783   ActivateActionReplace = 0x0,
 784   ActivateActionReplaceActivate = 0x1,
 785   ActivateActionActivate = 0x2
 786 } NVME_FW_ACTIVATE_ACTION;
 787
 788 //
 789 // Firmware Slot
 790 // (ref. spec. 1.1 Figure 60).
 791 //
 792 typedef enum {
 793   FirmwareSlotCtrlChooses = 0x0,
 794   FirmwareSlot1 = 0x1,
 795   FirmwareSlot2 = 0x2,
 796   FirmwareSlot3 = 0x3,
 797   FirmwareSlot4 = 0x4,
 798   FirmwareSlot5 = 0x5,
 799   FirmwareSlot6 = 0x6,
 800   FirmwareSlot7 = 0x7
 801 } NVME_FW_ACTIVATE_SLOT;
 802
 803 //
 804 // Get Log Page ? Log Page Identifiers
 805 // (ref. spec. v1.1 Figure 73).
 806 //
 807 typedef enum {
 808   ErrorInfoLogID = LID_ERROR_INFO,
 809   SmartHealthInfoLogID = LID_SMART_INFO,
 810   FirmwareSlotInfoLogID = LID_FW_SLOT_INFO
 811 } NVME_LOG_ID;
 812
 813 //
 814 // Get Log Page ? Firmware Slot Information Log
 815 // (ref. spec. v1.1 Figure 77).
 816 //
 817 typedef struct {
 818   //
 819   // Indicates the firmware slot from which the actively running firmware revision was loaded.
 820   //
 821   UINT8 ActivelyRunningFwSlot:3;
 822   UINT8 :1;
 823   //
 824   // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.
 825   //
 826   UINT8 NextActiveFwSlot:3;
 827   UINT8 :1;
 828 } NVME_ACTIVE_FW_INFO;
 829
 830 //
 831 // Get Log Page ? Firmware Slot Information Log
 832 // (ref. spec. v1.1 Figure 77).
 833 //
 834 typedef struct {
 835   //
 836   // Specifies information about the active firmware revision.
 837   //s
 838   NVME_ACTIVE_FW_INFO  ActiveFwInfo;
 839   UINT8                Reserved1[7];
 840   //
 841   // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.
 842   //
 843   CHAR8                FwRevisionSlot[7][8];
 844   UINT8                Reserved2[448];
 845 } NVME_FW_SLOT_INFO_LOG;
 846
 847 //
 848 // SMART / Health Information (Log Identifier 02h)
 849 // (ref. spec. v1.1 5.10.1.2)
 850 //
 851 typedef struct {
 852   //
 853   // This field indicates critical warnings for the state of the controller.
 854   //
 855   UINT8  CriticalWarningAvailableSpare:1;
 856   UINT8  CriticalWarningTemperature:1;
 857   UINT8  CriticalWarningReliability:1;
 858   UINT8  CriticalWarningMediaReadOnly:1;
 859   UINT8  CriticalWarningVolatileBackup:1;
 860   UINT8  CriticalWarningReserved:3;
 861   //
 862   // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.
 863   //
 864   UINT16 CompositeTemp;
 865   //
 866   // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.
 867   //
 868   UINT8  AvailableSpare;
 869   //
 870   // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).
 871   //
 872   UINT8  AvailableSpareThreshold;
 873   //
 874   // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer?s prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
 875   //
 876   UINT8  PercentageUsed;
 877   UINT8  Reserved1[26];
 878   //
 879   // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.
 880   //
 881   UINT8  DataUnitsRead[16];
 882   //
 883   // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.
 884   //
 885   UINT8  DataUnitsWritten[16];
 886   //
 887   // Contains the number of read commands completed by the controller.
 888   //
 889   UINT8  HostReadCommands[16];
 890   //
 891   // Contains the number of write commands completed by the controller.
 892   //
 893   UINT8  HostWriteCommands[16];
 894   //
 895   // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.
 896   //
 897   UINT8  ControllerBusyTime[16];
 898   //
 899   // Contains the number of power cycles.
 900   //
 901   UINT8  PowerCycles[16];
 902   //
 903   // Contains the number of power-on hours.
 904   //
 905   UINT8  PowerOnHours[16];
 906   //
 907   // Contains the number of unsafe shutdowns.
 908   //
 909   UINT8  UnsafeShutdowns[16];
 910   //
 911   // Contains the number of occurrences where the controller detected an unrecovered data integrity error.
 912   //
 913   UINT8  MediaAndDataIntegrityErrors[16];
 914   //
 915   // Contains the number of Error Information log entries over the life of the controller.
 916   //
 917   UINT8  NumberErrorInformationLogEntries[16];
 918   //
 919   // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
 920   //
 921   UINT32 WarningCompositeTemperatureTime;
 922   //
 923   // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
 924   //
 925   UINT32 CriticalCompositeTemperatureTime;
 926   //
 927   // Contains the current temperature in degrees Kelvin reported by the temperature sensor.  An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.
 928   //
 929   UINT16 TemperatureSensor[8];
 930   UINT8  Reserved2[296];
 931 } NVME_SMART_HEALTH_INFO_LOG;
 932
 933 #pragma pack()
 934
 935 #endif