MdePkg/Include/IndustryStandard/Nvme.h

   1 /** @file
   2   Definitions based on NVMe spec. version 1.1.
   3
   4   (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
   5   Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR>
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8   @par Specification Reference:
   9   NVMe Specification 1.1
  10   NVMe Specification 1.4
  11   NVMe Specification 2.0
  12
  13 **/
  14
  15 #ifndef __NVM_E_H__
  16 #define __NVM_E_H__
  17
  18 #pragma pack(1)
  19
  20 //
  21 // controller register offsets
  22 //
  23 #define NVME_CAP_OFFSET     0x0000        // Controller Capabilities
  24 #define NVME_VER_OFFSET     0x0008        // Version
  25 #define NVME_INTMS_OFFSET   0x000c        // Interrupt Mask Set
  26 #define NVME_INTMC_OFFSET   0x0010        // Interrupt Mask Clear
  27 #define NVME_CC_OFFSET      0x0014        // Controller Configuration
  28 #define NVME_CSTS_OFFSET    0x001c        // Controller Status
  29 #define NVME_NSSR_OFFSET    0x0020        // NVM Subsystem Reset
  30 #define NVME_AQA_OFFSET     0x0024        // Admin Queue Attributes
  31 #define NVME_ASQ_OFFSET     0x0028        // Admin Submission Queue Base Address
  32 #define NVME_ACQ_OFFSET     0x0030        // Admin Completion Queue Base Address
  33 #define NVME_BPINFO_OFFSET  0x0040        // Boot Partition Information
  34 #define NVME_BPRSEL_OFFSET  0x0044        // Boot Partition Read Select
  35 #define NVME_BPMBL_OFFSET   0x0048        // Boot Partition Memory Buffer Location
  36 #define NVME_SQ0_OFFSET     0x1000        // Submission Queue 0 (admin) Tail Doorbell
  37 #define NVME_CQ0_OFFSET     0x1004        // Completion Queue 0 (admin) Head Doorbell
  38
  39 //
  40 // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
  41 // Get the doorbell stride bit shift value from the controller capabilities.
  42 //
  43 #define NVME_SQTDBL_OFFSET(QID, DSTRD)  0x1000 + ((2 * (QID)) * (4 << (DSTRD)))         // Submission Queue y (NVM) Tail Doorbell
  44 #define NVME_CQHDBL_OFFSET(QID, DSTRD)  0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD)))   // Completion Queue y (NVM) Head Doorbell
  45
  46 #pragma pack(1)
  47
  48 //
  49 // 3.1.1 Offset 00h: CAP - Controller Capabilities
  50 //
  51 typedef struct {
  52   UINT16    Mqes;       // Maximum Queue Entries Supported
  53   UINT8     Cqr    : 1; // Contiguous Queues Required
  54   UINT8     Ams    : 2; // Arbitration Mechanism Supported
  55   UINT8     Rsvd1  : 5;
  56   UINT8     To;     // Timeout
  57   UINT16    Dstrd  : 4;
  58   UINT16    Nssrs  : 1; // NVM Subsystem Reset Supported NSSRS
  59   UINT16    Css    : 8; // Command Sets Supported - Bit 37
  60   UINT16    Bps    : 1; // Boot Partition Support - Bit 45 in NVMe1.4
  61   UINT16    Rsvd3  : 2;
  62   UINT8     Mpsmin : 4;
  63   UINT8     Mpsmax : 4;
  64   UINT8     Pmrs   : 1;
  65   UINT8     Cmbs   : 1;
  66   UINT8     Rsvd4  : 6;
  67 } NVME_CAP;
  68
  69 //
  70 // 3.1.2 Offset 08h: VS - Version
  71 //
  72 typedef struct {
  73   UINT16    Mnr;    // Minor version number
  74   UINT16    Mjr;    // Major version number
  75 } NVME_VER;
  76
  77 //
  78 // 3.1.5 Offset 14h: CC - Controller Configuration
  79 //
  80 typedef struct {
  81   UINT16    En     : 1; // Enable
  82   UINT16    Rsvd1  : 3;
  83   UINT16    Css    : 3; // I/O Command Set Selected
  84   UINT16    Mps    : 4; // Memory Page Size
  85   UINT16    Ams    : 3; // Arbitration Mechanism Selected
  86   UINT16    Shn    : 2; // Shutdown Notification
  87   UINT8     Iosqes : 4; // I/O Submission Queue Entry Size
  88   UINT8     Iocqes : 4; // I/O Completion Queue Entry Size
  89   UINT8     Rsvd2;
  90 } NVME_CC;
  91 #define NVME_CC_SHN_NORMAL_SHUTDOWN  1
  92 #define NVME_CC_SHN_ABRUPT_SHUTDOWN  2
  93
  94 //
  95 // 3.1.6 Offset 1Ch: CSTS - Controller Status
  96 //
  97 typedef struct {
  98   UINT32    Rdy   : 1; // Ready
  99   UINT32    Cfs   : 1; // Controller Fatal Status
 100   UINT32    Shst  : 2; // Shutdown Status
 101   UINT32    Nssro : 1; // NVM Subsystem Reset Occurred
 102   UINT32    Rsvd1 : 27;
 103 } NVME_CSTS;
 104 #define NVME_CSTS_SHST_SHUTDOWN_OCCURRING  1
 105 #define NVME_CSTS_SHST_SHUTDOWN_COMPLETED  2
 106 //
 107 // 3.1.8 Offset 24h: AQA - Admin Queue Attributes
 108 //
 109 typedef struct {
 110   UINT16    Asqs  : 12; // Submission Queue Size
 111   UINT16    Rsvd1 : 4;
 112   UINT16    Acqs  : 12; // Completion Queue Size
 113   UINT16    Rsvd2 : 4;
 114 } NVME_AQA;
 115
 116 //
 117 // 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
 118 //
 119 #define NVME_ASQ  UINT64
 120 //
 121 // 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
 122 //
 123 #define NVME_ACQ  UINT64
 124
 125 //
 126 // 3.1.13 Offset 40h: BPINFO - Boot Partition Information
 127 //
 128 typedef struct {
 129   UINT32    Bpsz  : 15; // Boot Partition Size
 130   UINT32    Rsvd1 : 9;
 131   UINT32    Brs   : 2;  // Boot Read Status
 132   UINT32    Rsvd2 : 5;
 133   UINT32    Abpid : 1;  // Active Boot Partition ID
 134 } NVME_BPINFO;
 135
 136 //
 137 // 3.1.14 Offset 44h: BPRSEL - Boot Partition Read Select
 138 //
 139 typedef struct {
 140   UINT32    Bprsz : 10; // Boot Partition Read Size
 141   UINT32    Bprof : 20; // Boot Partition Read Offset
 142   UINT32    Rsvd1 : 1;
 143   UINT32    Bpid  : 1;  // Boot Partition Identifier
 144 } NVME_BPRSEL;
 145
 146 //
 147 // 3.1.15 Offset 48h: BPMBL - Boot Partition Memory Buffer Location (Optional)
 148 //
 149 typedef struct {
 150   UINT64    Rsvd1 : 12;
 151   UINT64    Bmbba : 52; // Boot Partition Memory Buffer Base Address
 152 } NVME_BPMBL;
 153
 154 //
 155 // 3.1.25 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
 156 //
 157 typedef struct {
 158   UINT16    Sqt;
 159   UINT16    Rsvd1;
 160 } NVME_SQTDBL;
 161
 162 //
 163 // 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
 164 //
 165 typedef struct {
 166   UINT16    Cqh;
 167   UINT16    Rsvd1;
 168 } NVME_CQHDBL;
 169
 170 //
 171 // NVM command set structures
 172 //
 173 // Read Command
 174 //
 175 typedef struct {
 176   //
 177   // CDW 10, 11
 178   //
 179   UINT64    Slba;             /* Starting Sector Address */
 180   //
 181   // CDW 12
 182   //
 183   UINT16    Nlb;              /* Number of Sectors */
 184   UINT16    Rsvd1  : 10;
 185   UINT16    Prinfo : 4;       /* Protection Info Check */
 186   UINT16    Fua    : 1;       /* Force Unit Access */
 187   UINT16    Lr     : 1;       /* Limited Retry */
 188   //
 189   // CDW 13
 190   //
 191   UINT32    Af     : 4;       /* Access Frequency */
 192   UINT32    Al     : 2;       /* Access Latency */
 193   UINT32    Sr     : 1;       /* Sequential Request */
 194   UINT32    In     : 1;       /* Incompressible */
 195   UINT32    Rsvd2  : 24;
 196   //
 197   // CDW 14
 198   //
 199   UINT32    Eilbrt;           /* Expected Initial Logical Block Reference Tag */
 200   //
 201   // CDW 15
 202   //
 203   UINT16    Elbat;            /* Expected Logical Block Application Tag */
 204   UINT16    Elbatm;           /* Expected Logical Block Application Tag Mask */
 205 } NVME_READ;
 206
 207 //
 208 // Write Command
 209 //
 210 typedef struct {
 211   //
 212   // CDW 10, 11
 213   //
 214   UINT64    Slba;             /* Starting Sector Address */
 215   //
 216   // CDW 12
 217   //
 218   UINT16    Nlb;              /* Number of Sectors */
 219   UINT16    Rsvd1  : 10;
 220   UINT16    Prinfo : 4;       /* Protection Info Check */
 221   UINT16    Fua    : 1;       /* Force Unit Access */
 222   UINT16    Lr     : 1;       /* Limited Retry */
 223   //
 224   // CDW 13
 225   //
 226   UINT32    Af     : 4;       /* Access Frequency */
 227   UINT32    Al     : 2;       /* Access Latency */
 228   UINT32    Sr     : 1;       /* Sequential Request */
 229   UINT32    In     : 1;       /* Incompressible */
 230   UINT32    Rsvd2  : 24;
 231   //
 232   // CDW 14
 233   //
 234   UINT32    Ilbrt;            /* Initial Logical Block Reference Tag */
 235   //
 236   // CDW 15
 237   //
 238   UINT16    Lbat;             /* Logical Block Application Tag */
 239   UINT16    Lbatm;            /* Logical Block Application Tag Mask */
 240 } NVME_WRITE;
 241
 242 //
 243 // Flush
 244 //
 245 typedef struct {
 246   //
 247   // CDW 10
 248   //
 249   UINT32    Flush;            /* Flush */
 250 } NVME_FLUSH;
 251
 252 //
 253 // Write Uncorrectable command
 254 //
 255 typedef struct {
 256   //
 257   // CDW 10, 11
 258   //
 259   UINT64    Slba;             /* Starting LBA */
 260   //
 261   // CDW 12
 262   //
 263   UINT32    Nlb   : 16;       /* Number of  Logical Blocks */
 264   UINT32    Rsvd1 : 16;
 265 } NVME_WRITE_UNCORRECTABLE;
 266
 267 //
 268 // Write Zeroes command
 269 //
 270 typedef struct {
 271   //
 272   // CDW 10, 11
 273   //
 274   UINT64    Slba;             /* Starting LBA */
 275   //
 276   // CDW 12
 277   //
 278   UINT16    Nlb;              /* Number of Logical Blocks */
 279   UINT16    Rsvd1  : 10;
 280   UINT16    Prinfo : 4;       /* Protection Info Check */
 281   UINT16    Fua    : 1;       /* Force Unit Access */
 282   UINT16    Lr     : 1;       /* Limited Retry */
 283   //
 284   // CDW 13
 285   //
 286   UINT32    Rsvd2;
 287   //
 288   // CDW 14
 289   //
 290   UINT32    Ilbrt;            /* Initial Logical Block Reference Tag */
 291   //
 292   // CDW 15
 293   //
 294   UINT16    Lbat;             /* Logical Block Application Tag */
 295   UINT16    Lbatm;            /* Logical Block Application Tag Mask */
 296 } NVME_WRITE_ZEROES;
 297
 298 //
 299 // Compare command
 300 //
 301 typedef struct {
 302   //
 303   // CDW 10, 11
 304   //
 305   UINT64    Slba;             /* Starting LBA */
 306   //
 307   // CDW 12
 308   //
 309   UINT16    Nlb;              /* Number of Logical Blocks */
 310   UINT16    Rsvd1  : 10;
 311   UINT16    Prinfo : 4;       /* Protection Info Check */
 312   UINT16    Fua    : 1;       /* Force Unit Access */
 313   UINT16    Lr     : 1;       /* Limited Retry */
 314   //
 315   // CDW 13
 316   //
 317   UINT32    Rsvd2;
 318   //
 319   // CDW 14
 320   //
 321   UINT32    Eilbrt;           /* Expected Initial Logical Block Reference Tag */
 322   //
 323   // CDW 15
 324   //
 325   UINT16    Elbat;            /* Expected Logical Block Application Tag */
 326   UINT16    Elbatm;           /* Expected Logical Block Application Tag Mask */
 327 } NVME_COMPARE;
 328
 329 typedef union {
 330   NVME_READ                   Read;
 331   NVME_WRITE                  Write;
 332   NVME_FLUSH                  Flush;
 333   NVME_WRITE_UNCORRECTABLE    WriteUncorrectable;
 334   NVME_WRITE_ZEROES           WriteZeros;
 335   NVME_COMPARE                Compare;
 336 } NVME_CMD;
 337
 338 typedef struct {
 339   UINT16    Mp;             /* Maximum Power */
 340   UINT8     Rsvd1;          /* Reserved as of Nvm Express 1.1 Spec */
 341   UINT8     Mps   : 1;      /* Max Power Scale */
 342   UINT8     Nops  : 1;      /* Non-Operational State */
 343   UINT8     Rsvd2 : 6;      /* Reserved as of Nvm Express 1.1 Spec */
 344   UINT32    Enlat;          /* Entry Latency */
 345   UINT32    Exlat;          /* Exit Latency */
 346   UINT8     Rrt   : 5;      /* Relative Read Throughput */
 347   UINT8     Rsvd3 : 3;      /* Reserved as of Nvm Express 1.1 Spec */
 348   UINT8     Rrl   : 5;      /* Relative Read Latency */
 349   UINT8     Rsvd4 : 3;      /* Reserved as of Nvm Express 1.1 Spec */
 350   UINT8     Rwt   : 5;      /* Relative Write Throughput */
 351   UINT8     Rsvd5 : 3;      /* Reserved as of Nvm Express 1.1 Spec */
 352   UINT8     Rwl   : 5;      /* Relative Write Latency */
 353   UINT8     Rsvd6 : 3;      /* Reserved as of Nvm Express 1.1 Spec */
 354   UINT8     Rsvd7[16];      /* Reserved as of Nvm Express 1.1 Spec */
 355 } NVME_PSDESCRIPTOR;
 356
 357 //
 358 //  Identify Controller Data
 359 //
 360 typedef struct {
 361   //
 362   // Controller Capabilities and Features 0-255
 363   //
 364   UINT16               Vid;    /* PCI Vendor ID */
 365   UINT16               Ssvid;  /* PCI sub-system vendor ID */
 366   UINT8                Sn[20]; /* Product serial number */
 367
 368   UINT8                Mn[40];      /* Product model number */
 369   UINT8                Fr[8];       /* Firmware Revision */
 370   UINT8                Rab;         /* Recommended Arbitration Burst */
 371   UINT8                Ieee_oui[3]; /* Organization Unique Identifier */
 372   UINT8                Cmic;        /* Multi-interface Capabilities */
 373   UINT8                Mdts;        /* Maximum Data Transfer Size */
 374   UINT8                Cntlid[2];   /* Controller ID */
 375   UINT8                Rsvd1[176];  /* Reserved as of Nvm Express 1.1 Spec */
 376   //
 377   // Admin Command Set Attributes
 378   //
 379   UINT16               Oacs;  /* Optional Admin Command Support */
 380   #define NAMESPACE_MANAGEMENT_SUPPORTED   BIT3
 381   #define FW_DOWNLOAD_ACTIVATE_SUPPORTED   BIT2
 382   #define FORMAT_NVM_SUPPORTED             BIT1
 383   #define SECURITY_SEND_RECEIVE_SUPPORTED  BIT0
 384   UINT8                Acl;   /* Abort Command Limit */
 385   UINT8                Aerl;  /* Async Event Request Limit */
 386   UINT8                Frmw;  /* Firmware updates */
 387   UINT8                Lpa;   /* Log Page Attributes */
 388   UINT8                Elpe;  /* Error Log Page Entries */
 389   UINT8                Npss;  /* Number of Power States Support */
 390   UINT8                Avscc; /* Admin Vendor Specific Command Configuration */
 391   UINT8                Apsta; /* Autonomous Power State Transition Attributes */
 392   //
 393   // Below fields before Rsvd2 are defined in NVM Express 1.4 Spec
 394   //
 395   UINT16               Wctemp;      /* Warning Composite Temperature Threshold */
 396   UINT16               Cctemp;      /* Critical Composite Temperature Threshold */
 397   UINT16               Mtfa;        /* Maximum Time for Firmware Activation */
 398   UINT32               Hmpre;       /* Host Memory Buffer Preferred Size */
 399   UINT32               Hmmin;       /* Host Memory Buffer Minimum Size */
 400   UINT8                Tnvmcap[16]; /* Total NVM Capacity */
 401   UINT8                Unvmcap[16]; /* Unallocated NVM Capacity */
 402   UINT32               Rpmbs;       /* Replay Protected Memory Block Support */
 403   UINT16               Edstt;       /* Extended Device Self-test Time */
 404   UINT8                Dsto;        /* Device Self-test Options  */
 405   UINT8                Fwug;        /* Firmware Update Granularity */
 406   UINT8                Rsvd2[192];  /* Reserved as of Nvm Express 1.4 Spec */
 407   //
 408   // NVM Command Set Attributes
 409   //
 410   UINT8                Sqes;       /* Submission Queue Entry Size */
 411   UINT8                Cqes;       /* Completion Queue Entry Size */
 412   UINT16               Rsvd3;      /* Reserved as of Nvm Express 1.1 Spec */
 413   UINT32               Nn;         /* Number of Namespaces */
 414   UINT16               Oncs;       /* Optional NVM Command Support */
 415   UINT16               Fuses;      /* Fused Operation Support */
 416   UINT8                Fna;        /* Format NVM Attributes */
 417   UINT8                Vwc;        /* Volatile Write Cache */
 418   UINT16               Awun;       /* Atomic Write Unit Normal */
 419   UINT16               Awupf;      /* Atomic Write Unit Power Fail */
 420   UINT8                Nvscc;      /* NVM Vendor Specific Command Configuration */
 421   UINT8                Rsvd4;      /* Reserved as of Nvm Express 1.1 Spec */
 422   UINT16               Acwu;       /* Atomic Compare & Write Unit */
 423   UINT16               Rsvd5;      /* Reserved as of Nvm Express 1.1 Spec */
 424   UINT32               Sgls;       /* SGL Support  */
 425   UINT8                Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
 426   //
 427   // I/O Command set Attributes
 428   //
 429   UINT8                Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
 430   //
 431   // Power State Descriptors
 432   //
 433   NVME_PSDESCRIPTOR    PsDescriptor[32];
 434
 435   UINT8                VendorData[1024]; /* Vendor specific data */
 436 } NVME_ADMIN_CONTROLLER_DATA;
 437
 438 typedef struct {
 439   UINT16    Ms;             /* Metadata Size */
 440   UINT8     Lbads;          /* LBA Data Size */
 441   UINT8     Rp    : 2;      /* Relative Performance */
 442   #define LBAF_RP_BEST      00b
 443   #define LBAF_RP_BETTER    01b
 444   #define LBAF_RP_GOOD      10b
 445   #define LBAF_RP_DEGRADED  11b
 446   UINT8     Rsvd1 : 6;      /* Reserved as of Nvm Express 1.1 Spec */
 447 } NVME_LBAFORMAT;
 448
 449 //
 450 // Identify Namespace Data
 451 //
 452 typedef struct {
 453   //
 454   // NVM Command Set Specific
 455   //
 456   UINT64            Nsze;      /* Namespace Size (total number of blocks in formatted namespace) */
 457   UINT64            Ncap;      /* Namespace Capacity (max number of logical blocks) */
 458   UINT64            Nuse;      /* Namespace Utilization */
 459   UINT8             Nsfeat;    /* Namespace Features */
 460   UINT8             Nlbaf;     /* Number of LBA Formats */
 461   UINT8             Flbas;     /* Formatted LBA size */
 462   UINT8             Mc;        /* Metadata Capabilities */
 463   UINT8             Dpc;       /* End-to-end Data Protection capabilities */
 464   UINT8             Dps;       /* End-to-end Data Protection Type Settings */
 465   UINT8             Nmic;      /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
 466   UINT8             Rescap;    /* Reservation Capabilities */
 467   UINT8             Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */
 468   UINT64            Eui64;     /* IEEE Extended Unique Identifier */
 469   //
 470   // LBA Format
 471   //
 472   NVME_LBAFORMAT    LbaFormat[16];
 473
 474   UINT8             Rsvd2[192];       /* Reserved as of Nvm Express 1.1 Spec */
 475   UINT8             VendorData[3712]; /* Vendor specific data */
 476 } NVME_ADMIN_NAMESPACE_DATA;
 477
 478 //
 479 // RPMB Device Configuration Block Data Structure as of Nvm Express 1.4 Spec
 480 //
 481 typedef struct {
 482   UINT8    Bppe;       /* Boot Partition Protection Enable */
 483   UINT8    Bpl;        /* Boot Partition Lock */
 484   UINT8    Nwpac;      /* Namespace Write Protection Authentication Control */
 485   UINT8    Rsvd1[509]; /* Reserved as of Nvm Express 1.4 Spec */
 486 } NVME_RPMB_CONFIGURATION_DATA;
 487
 488 #define RPMB_FRAME_STUFF_BYTES  223
 489
 490 //
 491 // RPMB Data Frame as of Nvm Express 1.4 Spec
 492 //
 493 typedef struct {
 494   UINT8     Sbakamc[RPMB_FRAME_STUFF_BYTES]; /* [222-N:00] Stuff Bytes */
 495                                              /* [222:222-(N-1)] Authentication Key or Message Authentication Code (MAC) */
 496   UINT8     Rpmbt;                           /* RPMB Target */
 497   UINT64    Nonce[2];
 498   UINT32    Wcounter;                        /* Write Counter */
 499   UINT32    Address;                         /* Starting address of data to be programmed to or read from the RPMB. */
 500   UINT32    Scount;                          /* Sector Count */
 501   UINT16    Result;
 502   UINT16    Rpmessage;                       /* Request/Response Message */
 503   // UINT8    *Data;                         /* Data to be written or read by signed access where M = 512 * Sector Count. */
 504 } NVME_RPMB_DATA_FRAME;
 505
 506 //
 507 // RPMB Device Configuration Block Data Structure.
 508 // (ref. NVMe Base spec. v2.0 Figure 460).
 509 //
 510 typedef struct {
 511   UINT8    BPPEnable;     /* Boot Partition Protection Enabled */
 512   UINT8    BPLock;        /* Boot Partition Lock */
 513   UINT8    NameSpaceWrP;  /* Namespace Write Protection */
 514   UINT8    Rsvd1[509];    /* Reserved as of Nvm Express 2.0 Spec */
 515 } NVME_RPMB_DCB;
 516
 517 //
 518 // RPMB Request and Response Message Types.
 519 // (ref. NVMe Base spec. v2.0 Figure 461).
 520 //
 521 #define NVME_RPMB_AUTHKEY_PROGRAM           0x0001
 522 #define NVME_RPMB_COUNTER_READ              0x0002
 523 #define NVME_RPMB_AUTHDATA_WRITE            0x0003
 524 #define NVME_RPMB_AUTHDATA_READ             0x0004
 525 #define NVME_RPMB_RESULT_READ               0x0005
 526 #define NVME_RPMB_DCB_WRITE                 0x0006
 527 #define NVME_RPMB_DCB_READ                  0x0007
 528 #define NVME_RPMB_AUTHKEY_PROGRAM_RESPONSE  0x0100
 529 #define NVME_RPMB_COUNTER_READ_RESPONSE     0x0200
 530 #define NVME_RPMB_AUTHDATA_WRITE_RESPONSE   0x0300
 531 #define NVME_RPMB_AUTHDATA_READ_RESPONSE    0x0400
 532 #define NVME_RPMB_DCB_WRITE_RESPONSE        0x0600
 533 #define NVME_RPMB_DCB_READ_RESPONSE         0x0700
 534
 535 //
 536 // RPMB Operation Result.
 537 // (ref. NVMe Base spec. v2.0 Figure 462).
 538 //
 539 #define NVME_RPMB_RESULT_SUCCESS                 0x00
 540 #define NVME_RPMB_RESULT_GENERAL_FAILURE         0x01
 541 #define NVME_RPMB_RESULT_AHTHENTICATION_FAILURE  0x02
 542 #define NVME_RPMB_RESULT_COUNTER_FAILURE         0x03
 543 #define NVME_RPMB_RESULT_ADDRESS_FAILURE         0x04
 544 #define NVME_RPMB_RESULT_WRITE_FAILURE           0x05
 545 #define NVME_RPMB_RESULT_READ_FAILURE            0x06
 546 #define NVME_RPMB_RESULT_AUTHKEY_NOT_PROGRAMMED  0x07
 547 #define NVME_RPMB_RESULT_INVALID_DCB             0x08
 548
 549 //
 550 // NvmExpress Admin Identify Cmd
 551 //
 552 typedef struct {
 553   //
 554   // CDW 10
 555   //
 556   UINT32    Cns   : 2;
 557   UINT32    Rsvd1 : 30;
 558 } NVME_ADMIN_IDENTIFY;
 559
 560 //
 561 // NvmExpress Admin Create I/O Completion Queue
 562 //
 563 typedef struct {
 564   //
 565   // CDW 10
 566   //
 567   UINT32    Qid   : 16;       /* Queue Identifier */
 568   UINT32    Qsize : 16;       /* Queue Size */
 569
 570   //
 571   // CDW 11
 572   //
 573   UINT32    Pc    : 1;        /* Physically Contiguous */
 574   UINT32    Ien   : 1;        /* Interrupts Enabled */
 575   UINT32    Rsvd1 : 14;       /* reserved as of Nvm Express 1.1 Spec */
 576   UINT32    Iv    : 16;       /* Interrupt Vector for MSI-X or MSI*/
 577 } NVME_ADMIN_CRIOCQ;
 578
 579 //
 580 // NvmExpress Admin Create I/O Submission Queue
 581 //
 582 typedef struct {
 583   //
 584   // CDW 10
 585   //
 586   UINT32    Qid   : 16;       /* Queue Identifier */
 587   UINT32    Qsize : 16;       /* Queue Size */
 588
 589   //
 590   // CDW 11
 591   //
 592   UINT32    Pc    : 1;        /* Physically Contiguous */
 593   UINT32    Qprio : 2;        /* Queue Priority */
 594   UINT32    Rsvd1 : 13;       /* Reserved as of Nvm Express 1.1 Spec */
 595   UINT32    Cqid  : 16;       /* Completion Queue ID */
 596 } NVME_ADMIN_CRIOSQ;
 597
 598 //
 599 // NvmExpress Admin Delete I/O Completion Queue
 600 //
 601 typedef struct {
 602   //
 603   // CDW 10
 604   //
 605   UINT16    Qid;
 606   UINT16    Rsvd1;
 607 } NVME_ADMIN_DEIOCQ;
 608
 609 //
 610 // NvmExpress Admin Delete I/O Submission Queue
 611 //
 612 typedef struct {
 613   //
 614   // CDW 10
 615   //
 616   UINT16    Qid;
 617   UINT16    Rsvd1;
 618 } NVME_ADMIN_DEIOSQ;
 619
 620 //
 621 // NvmExpress Admin Abort Command
 622 //
 623 typedef struct {
 624   //
 625   // CDW 10
 626   //
 627   UINT32    Sqid : 16;        /* Submission Queue identifier */
 628   UINT32    Cid  : 16;        /* Command Identifier */
 629 } NVME_ADMIN_ABORT;
 630
 631 //
 632 // NvmExpress Admin Firmware Activate Command
 633 //
 634 typedef struct {
 635   //
 636   // CDW 10
 637   //
 638   UINT32    Fs    : 3;        /* Submission Queue identifier */
 639   UINT32    Aa    : 2;        /* Command Identifier */
 640   UINT32    Rsvd1 : 27;
 641 } NVME_ADMIN_FIRMWARE_ACTIVATE;
 642
 643 //
 644 // NvmExpress Admin Firmware Image Download Command
 645 //
 646 typedef struct {
 647   //
 648   // CDW 10
 649   //
 650   UINT32    Numd;             /* Number of Dwords */
 651   //
 652   // CDW 11
 653   //
 654   UINT32    Ofst;             /* Offset */
 655 } NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
 656
 657 //
 658 // NvmExpress Admin Get Features Command
 659 //
 660 typedef struct {
 661   //
 662   // CDW 10
 663   //
 664   UINT32    Fid   : 8;         /* Feature Identifier */
 665   UINT32    Sel   : 3;         /* Select */
 666   UINT32    Rsvd1 : 21;
 667 } NVME_ADMIN_GET_FEATURES;
 668
 669 //
 670 // NvmExpress Admin Get Log Page Command
 671 //
 672 typedef struct {
 673   //
 674   // CDW 10
 675   //
 676   UINT32    Lid   : 8;        /* Log Page Identifier */
 677   #define LID_ERROR_INFO    0x1
 678   #define LID_SMART_INFO    0x2
 679   #define LID_FW_SLOT_INFO  0x3
 680   #define LID_BP_INFO       0x15
 681   UINT32    Rsvd1 : 8;
 682   UINT32    Numd  : 12;       /* Number of Dwords */
 683   UINT32    Rsvd2 : 4;        /* Reserved as of Nvm Express 1.1 Spec */
 684 } NVME_ADMIN_GET_LOG_PAGE;
 685
 686 //
 687 // NvmExpress Admin Set Features Command
 688 //
 689 typedef struct {
 690   //
 691   // CDW 10
 692   //
 693   UINT32    Fid   : 8;        /* Feature Identifier */
 694   UINT32    Rsvd1 : 23;
 695   UINT32    Sv    : 1;        /* Save */
 696 } NVME_ADMIN_SET_FEATURES;
 697
 698 //
 699 // NvmExpress Admin Format NVM Command
 700 //
 701 typedef struct {
 702   //
 703   // CDW 10
 704   //
 705   UINT32    Lbaf  : 4;        /* LBA Format */
 706   UINT32    Ms    : 1;        /* Metadata Settings */
 707   UINT32    Pi    : 3;        /* Protection Information */
 708   UINT32    Pil   : 1;        /* Protection Information Location */
 709   UINT32    Ses   : 3;        /* Secure Erase Settings */
 710   UINT32    Rsvd1 : 20;
 711 } NVME_ADMIN_FORMAT_NVM;
 712
 713 //
 714 // NvmExpress Admin Security Receive Command
 715 //
 716 typedef struct {
 717   //
 718   // CDW 10
 719   //
 720   UINT32    Rsvd1 : 8;
 721   UINT32    Spsp  : 16;       /* SP Specific */
 722   UINT32    Secp  : 8;        /* Security Protocol */
 723   //
 724   // CDW 11
 725   //
 726   UINT32    Al;               /* Allocation Length */
 727 } NVME_ADMIN_SECURITY_RECEIVE;
 728
 729 //
 730 // NvmExpress Admin Security Send Command
 731 //
 732 typedef struct {
 733   //
 734   // CDW 10
 735   //
 736   UINT32    Rsvd1 : 8;
 737   UINT32    Spsp  : 16;       /* SP Specific */
 738   UINT32    Secp  : 8;        /* Security Protocol */
 739   //
 740   // CDW 11
 741   //
 742   UINT32    Tl;               /* Transfer Length */
 743 } NVME_ADMIN_SECURITY_SEND;
 744
 745 typedef union {
 746   NVME_ADMIN_IDENTIFY                   Identify;
 747   NVME_ADMIN_CRIOCQ                     CrIoCq;
 748   NVME_ADMIN_CRIOSQ                     CrIoSq;
 749   NVME_ADMIN_DEIOCQ                     DeIoCq;
 750   NVME_ADMIN_DEIOSQ                     DeIoSq;
 751   NVME_ADMIN_ABORT                      Abort;
 752   NVME_ADMIN_FIRMWARE_ACTIVATE          Activate;
 753   NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD    FirmwareImageDownload;
 754   NVME_ADMIN_GET_FEATURES               GetFeatures;
 755   NVME_ADMIN_GET_LOG_PAGE               GetLogPage;
 756   NVME_ADMIN_SET_FEATURES               SetFeatures;
 757   NVME_ADMIN_FORMAT_NVM                 FormatNvm;
 758   NVME_ADMIN_SECURITY_RECEIVE           SecurityReceive;
 759   NVME_ADMIN_SECURITY_SEND              SecuritySend;
 760 } NVME_ADMIN_CMD;
 761
 762 typedef struct {
 763   UINT32    Cdw10;
 764   UINT32    Cdw11;
 765   UINT32    Cdw12;
 766   UINT32    Cdw13;
 767   UINT32    Cdw14;
 768   UINT32    Cdw15;
 769 } NVME_RAW;
 770
 771 typedef union {
 772   NVME_ADMIN_CMD    Admin; // Union of Admin commands
 773   NVME_CMD          Nvm;   // Union of Nvm commands
 774   NVME_RAW          Raw;
 775 } NVME_PAYLOAD;
 776
 777 //
 778 // Submission Queue
 779 //
 780 typedef struct {
 781   //
 782   // CDW 0, Common to all commands
 783   //
 784   UINT8           Opc;       // Opcode
 785   UINT8           Fuse  : 2; // Fused Operation
 786   UINT8           Rsvd1 : 5;
 787   UINT8           Psdt  : 1; // PRP or SGL for Data Transfer
 788   UINT16          Cid;       // Command Identifier
 789
 790   //
 791   // CDW 1
 792   //
 793   UINT32          Nsid;     // Namespace Identifier
 794
 795   //
 796   // CDW 2,3
 797   //
 798   UINT64          Rsvd2;
 799
 800   //
 801   // CDW 4,5
 802   //
 803   UINT64          Mptr;     // Metadata Pointer
 804
 805   //
 806   // CDW 6-9
 807   //
 808   UINT64          Prp[2];   // First and second PRP entries
 809
 810   NVME_PAYLOAD    Payload;
 811 } NVME_SQ;
 812
 813 //
 814 // Completion Queue
 815 //
 816 typedef struct {
 817   //
 818   // CDW 0
 819   //
 820   UINT32    Dword0;
 821   //
 822   // CDW 1
 823   //
 824   UINT32    Rsvd1;
 825   //
 826   // CDW 2
 827   //
 828   UINT16    Sqhd;           // Submission Queue Head Pointer
 829   UINT16    Sqid;           // Submission Queue Identifier
 830   //
 831   // CDW 3
 832   //
 833   UINT16    Cid;            // Command Identifier
 834   UINT16    Pt    : 1;      // Phase Tag
 835   UINT16    Sc    : 8;      // Status Code
 836   UINT16    Sct   : 3;      // Status Code Type
 837   UINT16    Rsvd2 : 2;
 838   UINT16    Mo    : 1;      // More
 839   UINT16    Dnr   : 1;      // Do Not Retry
 840 } NVME_CQ;
 841
 842 //
 843 // Nvm Express Admin cmd opcodes
 844 //
 845 #define NVME_ADMIN_DEIOSQ_CMD               0x00
 846 #define NVME_ADMIN_CRIOSQ_CMD               0x01
 847 #define NVME_ADMIN_GET_LOG_PAGE_CMD         0x02
 848 #define NVME_ADMIN_DEIOCQ_CMD               0x04
 849 #define NVME_ADMIN_CRIOCQ_CMD               0x05
 850 #define NVME_ADMIN_IDENTIFY_CMD             0x06
 851 #define NVME_ADMIN_ABORT_CMD                0x08
 852 #define NVME_ADMIN_SET_FEATURES_CMD         0x09
 853 #define NVME_ADMIN_GET_FEATURES_CMD         0x0A
 854 #define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD  0x0C
 855 #define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD  0x0D
 856 #define NVME_ADMIN_FW_COMMIT_CMD            0x10
 857 #define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD    0x11
 858 #define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD  0x15
 859 #define NVME_ADMIN_FORMAT_NVM_CMD           0x80
 860 #define NVME_ADMIN_SECURITY_SEND_CMD        0x81
 861 #define NVME_ADMIN_SECURITY_RECEIVE_CMD     0x82
 862
 863 #define NVME_IO_FLUSH_OPC  0
 864 #define NVME_IO_WRITE_OPC  1
 865 #define NVME_IO_READ_OPC   2
 866
 867 typedef enum {
 868   DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,
 869   CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,
 870   GetLogPageOpcode              = NVME_ADMIN_GET_LOG_PAGE_CMD,
 871   DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,
 872   CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,
 873   IdentifyOpcode                = NVME_ADMIN_IDENTIFY_CMD,
 874   AbortOpcode                   = NVME_ADMIN_ABORT_CMD,
 875   SetFeaturesOpcode             = NVME_ADMIN_SET_FEATURES_CMD,
 876   GetFeaturesOpcode             = NVME_ADMIN_GET_FEATURES_CMD,
 877   AsyncEventRequestOpcode       = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,
 878   NamespaceManagementOpcode     = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,
 879   FirmwareCommitOpcode          = NVME_ADMIN_FW_COMMIT_CMD,
 880   FirmwareImageDownloadOpcode   = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,
 881   NamespaceAttachmentOpcode     = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,
 882   FormatNvmOpcode               = NVME_ADMIN_FORMAT_NVM_CMD,
 883   SecuritySendOpcode            = NVME_ADMIN_SECURITY_SEND_CMD,
 884   SecurityReceiveOpcode         = NVME_ADMIN_SECURITY_RECEIVE_CMD
 885 } NVME_ADMIN_COMMAND_OPCODE;
 886
 887 //
 888 // Controller or Namespace Structure (CNS) field
 889 // (ref. spec. v1.1 figure 82).
 890 //
 891 typedef enum {
 892   IdentifyNamespaceCns    = 0x0,
 893   IdentifyControllerCns   = 0x1,
 894   IdentifyActiveNsListCns = 0x2
 895 } NVME_ADMIN_IDENTIFY_CNS;
 896
 897 //
 898 // Commit Action
 899 // (ref. spec. 1.1 figure 60).
 900 //
 901 typedef enum {
 902   ActivateActionReplace         = 0x0,
 903   ActivateActionReplaceActivate = 0x1,
 904   ActivateActionActivate        = 0x2
 905 } NVME_FW_ACTIVATE_ACTION;
 906
 907 //
 908 // Firmware Slot
 909 // (ref. spec. 1.1 Figure 60).
 910 //
 911 typedef enum {
 912   FirmwareSlotCtrlChooses = 0x0,
 913   FirmwareSlot1           = 0x1,
 914   FirmwareSlot2           = 0x2,
 915   FirmwareSlot3           = 0x3,
 916   FirmwareSlot4           = 0x4,
 917   FirmwareSlot5           = 0x5,
 918   FirmwareSlot6           = 0x6,
 919   FirmwareSlot7           = 0x7
 920 } NVME_FW_ACTIVATE_SLOT;
 921
 922 //
 923 // Get Log Page ? Log Page Identifiers
 924 // (ref. spec. v1.1 Figure 73).
 925 //
 926 typedef enum {
 927   ErrorInfoLogID        = LID_ERROR_INFO,
 928   SmartHealthInfoLogID  = LID_SMART_INFO,
 929   FirmwareSlotInfoLogID = LID_FW_SLOT_INFO
 930 } NVME_LOG_ID;
 931
 932 //
 933 // Get Log Page ? Firmware Slot Information Log
 934 // (ref. spec. v1.1 Figure 77).
 935 //
 936 typedef struct {
 937   //
 938   // Indicates the firmware slot from which the actively running firmware revision was loaded.
 939   //
 940   UINT8    ActivelyRunningFwSlot : 3;
 941   UINT8                          : 1;
 942   //
 943   // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.
 944   //
 945   UINT8    NextActiveFwSlot      : 3;
 946   UINT8                          : 1;
 947 } NVME_ACTIVE_FW_INFO;
 948
 949 //
 950 // Get Log Page ? Firmware Slot Information Log
 951 // (ref. spec. v1.1 Figure 77).
 952 //
 953 typedef struct {
 954   //
 955   // Specifies information about the active firmware revision.
 956   // s
 957   NVME_ACTIVE_FW_INFO    ActiveFwInfo;
 958   UINT8                  Reserved1[7];
 959   //
 960   // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.
 961   //
 962   CHAR8                  FwRevisionSlot[7][8];
 963   UINT8                  Reserved2[448];
 964 } NVME_FW_SLOT_INFO_LOG;
 965
 966 //
 967 // SMART / Health Information (Log Identifier 02h)
 968 // (ref. spec. v1.1 5.10.1.2)
 969 //
 970 typedef struct {
 971   //
 972   // This field indicates critical warnings for the state of the controller.
 973   //
 974   UINT8     CriticalWarningAvailableSpare : 1;
 975   UINT8     CriticalWarningTemperature    : 1;
 976   UINT8     CriticalWarningReliability    : 1;
 977   UINT8     CriticalWarningMediaReadOnly  : 1;
 978   UINT8     CriticalWarningVolatileBackup : 1;
 979   UINT8     CriticalWarningReserved       : 3;
 980   //
 981   // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.
 982   //
 983   UINT16    CompositeTemp;
 984   //
 985   // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.
 986   //
 987   UINT8     AvailableSpare;
 988   //
 989   // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).
 990   //
 991   UINT8     AvailableSpareThreshold;
 992   //
 993   // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
 994   //
 995   UINT8     PercentageUsed;
 996   UINT8     Reserved1[26];
 997   //
 998   // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.
 999   //
1000   UINT8     DataUnitsRead[16];
1001   //
1002   // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.
1003   //
1004   UINT8     DataUnitsWritten[16];
1005   //
1006   // Contains the number of read commands completed by the controller.
1007   //
1008   UINT8     HostReadCommands[16];
1009   //
1010   // Contains the number of write commands completed by the controller.
1011   //
1012   UINT8     HostWriteCommands[16];
1013   //
1014   // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.
1015   //
1016   UINT8     ControllerBusyTime[16];
1017   //
1018   // Contains the number of power cycles.
1019   //
1020   UINT8     PowerCycles[16];
1021   //
1022   // Contains the number of power-on hours.
1023   //
1024   UINT8     PowerOnHours[16];
1025   //
1026   // Contains the number of unsafe shutdowns.
1027   //
1028   UINT8     UnsafeShutdowns[16];
1029   //
1030   // Contains the number of occurrences where the controller detected an unrecovered data integrity error.
1031   //
1032   UINT8     MediaAndDataIntegrityErrors[16];
1033   //
1034   // Contains the number of Error Information log entries over the life of the controller.
1035   //
1036   UINT8     NumberErrorInformationLogEntries[16];
1037   //
1038   // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
1039   //
1040   UINT32    WarningCompositeTemperatureTime;
1041   //
1042   // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
1043   //
1044   UINT32    CriticalCompositeTemperatureTime;
1045   //
1046   // Contains the current temperature in degrees Kelvin reported by the temperature sensor.  An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.
1047   //
1048   UINT16    TemperatureSensor[8];
1049   UINT8     Reserved2[296];
1050 } NVME_SMART_HEALTH_INFO_LOG;
1051
1052 #pragma pack()
1053
1054 #endif