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MdePkg: Add registers of boot partition feature
[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Nvme.h
1 /** @file
2 Definitions based on NVMe spec. version 1.1.
3
4 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
5 Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 @par Specification Reference:
9 NVMe Specification 1.1
10 NVMe Specification 1.4
11
12 **/
13
14 #ifndef __NVM_E_H__
15 #define __NVM_E_H__
16
17 #pragma pack(1)
18
19 //
20 // controller register offsets
21 //
22 #define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
23 #define NVME_VER_OFFSET 0x0008 // Version
24 #define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
25 #define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
26 #define NVME_CC_OFFSET 0x0014 // Controller Configuration
27 #define NVME_CSTS_OFFSET 0x001c // Controller Status
28 #define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
29 #define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
30 #define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
31 #define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
32 #define NVME_BPINFO_OFFSET 0x0040 // Boot Partition Information
33 #define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read Select
34 #define NVME_BPMBL_OFFSET 0x0048 // Boot Partition Memory Buffer Location
35 #define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
36 #define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
37
38 //
39 // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
40 // Get the doorbell stride bit shift value from the controller capabilities.
41 //
42 #define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
43 #define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
44
45 #pragma pack(1)
46
47 //
48 // 3.1.1 Offset 00h: CAP - Controller Capabilities
49 //
50 typedef struct {
51 UINT16 Mqes; // Maximum Queue Entries Supported
52 UINT8 Cqr : 1; // Contiguous Queues Required
53 UINT8 Ams : 2; // Arbitration Mechanism Supported
54 UINT8 Rsvd1 : 5;
55 UINT8 To; // Timeout
56 UINT16 Dstrd : 4;
57 UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS
58 UINT16 Css : 8; // Command Sets Supported - Bit 37
59 UINT16 Bps : 1; // Boot Partition Support - Bit 45 in NVMe1.4
60 UINT16 Rsvd3 : 2;
61 UINT8 Mpsmin : 4;
62 UINT8 Mpsmax : 4;
63 UINT8 Pmrs : 1;
64 UINT8 Cmbs : 1;
65 UINT8 Rsvd4 : 6;
66 } NVME_CAP;
67
68 //
69 // 3.1.2 Offset 08h: VS - Version
70 //
71 typedef struct {
72 UINT16 Mnr; // Minor version number
73 UINT16 Mjr; // Major version number
74 } NVME_VER;
75
76 //
77 // 3.1.5 Offset 14h: CC - Controller Configuration
78 //
79 typedef struct {
80 UINT16 En : 1; // Enable
81 UINT16 Rsvd1 : 3;
82 UINT16 Css : 3; // I/O Command Set Selected
83 UINT16 Mps : 4; // Memory Page Size
84 UINT16 Ams : 3; // Arbitration Mechanism Selected
85 UINT16 Shn : 2; // Shutdown Notification
86 UINT8 Iosqes : 4; // I/O Submission Queue Entry Size
87 UINT8 Iocqes : 4; // I/O Completion Queue Entry Size
88 UINT8 Rsvd2;
89 } NVME_CC;
90 #define NVME_CC_SHN_NORMAL_SHUTDOWN 1
91 #define NVME_CC_SHN_ABRUPT_SHUTDOWN 2
92
93 //
94 // 3.1.6 Offset 1Ch: CSTS - Controller Status
95 //
96 typedef struct {
97 UINT32 Rdy : 1; // Ready
98 UINT32 Cfs : 1; // Controller Fatal Status
99 UINT32 Shst : 2; // Shutdown Status
100 UINT32 Nssro : 1; // NVM Subsystem Reset Occurred
101 UINT32 Rsvd1 : 27;
102 } NVME_CSTS;
103 #define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1
104 #define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2
105 //
106 // 3.1.8 Offset 24h: AQA - Admin Queue Attributes
107 //
108 typedef struct {
109 UINT16 Asqs : 12; // Submission Queue Size
110 UINT16 Rsvd1 : 4;
111 UINT16 Acqs : 12; // Completion Queue Size
112 UINT16 Rsvd2 : 4;
113 } NVME_AQA;
114
115 //
116 // 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
117 //
118 #define NVME_ASQ UINT64
119 //
120 // 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
121 //
122 #define NVME_ACQ UINT64
123
124 //
125 // 3.1.13 Offset 40h: BPINFO - Boot Partition Information
126 //
127 typedef struct {
128 UINT32 Bpsz : 15; // Boot Partition Size
129 UINT32 Rsvd1 : 9;
130 UINT32 Brs : 2; // Boot Read Status
131 UINT32 Rsvd2 : 5;
132 UINT32 Abpid : 1; // Active Boot Partition ID
133 } NVME_BPINFO;
134
135 //
136 // 3.1.14 Offset 44h: BPRSEL - Boot Partition Read Select
137 //
138 typedef struct {
139 UINT32 Bprsz : 10; // Boot Partition Read Size
140 UINT32 Bprof : 20; // Boot Partition Read Offset
141 UINT32 Rsvd1 : 1;
142 UINT32 Bpid : 1; // Boot Partition Identifier
143 } NVME_BPRSEL;
144
145 //
146 // 3.1.15 Offset 48h: BPMBL - Boot Partition Memory Buffer Location (Optional)
147 //
148 typedef struct {
149 UINT64 Rsvd1 : 12;
150 UINT64 Bmbba : 52; // Boot Partition Memory Buffer Base Address
151 } NVME_BPMBL;
152
153 //
154 // 3.1.25 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
155 //
156 typedef struct {
157 UINT16 Sqt;
158 UINT16 Rsvd1;
159 } NVME_SQTDBL;
160
161 //
162 // 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
163 //
164 typedef struct {
165 UINT16 Cqh;
166 UINT16 Rsvd1;
167 } NVME_CQHDBL;
168
169 //
170 // NVM command set structures
171 //
172 // Read Command
173 //
174 typedef struct {
175 //
176 // CDW 10, 11
177 //
178 UINT64 Slba; /* Starting Sector Address */
179 //
180 // CDW 12
181 //
182 UINT16 Nlb; /* Number of Sectors */
183 UINT16 Rsvd1 : 10;
184 UINT16 Prinfo : 4; /* Protection Info Check */
185 UINT16 Fua : 1; /* Force Unit Access */
186 UINT16 Lr : 1; /* Limited Retry */
187 //
188 // CDW 13
189 //
190 UINT32 Af : 4; /* Access Frequency */
191 UINT32 Al : 2; /* Access Latency */
192 UINT32 Sr : 1; /* Sequential Request */
193 UINT32 In : 1; /* Incompressible */
194 UINT32 Rsvd2 : 24;
195 //
196 // CDW 14
197 //
198 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
199 //
200 // CDW 15
201 //
202 UINT16 Elbat; /* Expected Logical Block Application Tag */
203 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
204 } NVME_READ;
205
206 //
207 // Write Command
208 //
209 typedef struct {
210 //
211 // CDW 10, 11
212 //
213 UINT64 Slba; /* Starting Sector Address */
214 //
215 // CDW 12
216 //
217 UINT16 Nlb; /* Number of Sectors */
218 UINT16 Rsvd1 : 10;
219 UINT16 Prinfo : 4; /* Protection Info Check */
220 UINT16 Fua : 1; /* Force Unit Access */
221 UINT16 Lr : 1; /* Limited Retry */
222 //
223 // CDW 13
224 //
225 UINT32 Af : 4; /* Access Frequency */
226 UINT32 Al : 2; /* Access Latency */
227 UINT32 Sr : 1; /* Sequential Request */
228 UINT32 In : 1; /* Incompressible */
229 UINT32 Rsvd2 : 24;
230 //
231 // CDW 14
232 //
233 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
234 //
235 // CDW 15
236 //
237 UINT16 Lbat; /* Logical Block Application Tag */
238 UINT16 Lbatm; /* Logical Block Application Tag Mask */
239 } NVME_WRITE;
240
241 //
242 // Flush
243 //
244 typedef struct {
245 //
246 // CDW 10
247 //
248 UINT32 Flush; /* Flush */
249 } NVME_FLUSH;
250
251 //
252 // Write Uncorrectable command
253 //
254 typedef struct {
255 //
256 // CDW 10, 11
257 //
258 UINT64 Slba; /* Starting LBA */
259 //
260 // CDW 12
261 //
262 UINT32 Nlb : 16; /* Number of Logical Blocks */
263 UINT32 Rsvd1 : 16;
264 } NVME_WRITE_UNCORRECTABLE;
265
266 //
267 // Write Zeroes command
268 //
269 typedef struct {
270 //
271 // CDW 10, 11
272 //
273 UINT64 Slba; /* Starting LBA */
274 //
275 // CDW 12
276 //
277 UINT16 Nlb; /* Number of Logical Blocks */
278 UINT16 Rsvd1 : 10;
279 UINT16 Prinfo : 4; /* Protection Info Check */
280 UINT16 Fua : 1; /* Force Unit Access */
281 UINT16 Lr : 1; /* Limited Retry */
282 //
283 // CDW 13
284 //
285 UINT32 Rsvd2;
286 //
287 // CDW 14
288 //
289 UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
290 //
291 // CDW 15
292 //
293 UINT16 Lbat; /* Logical Block Application Tag */
294 UINT16 Lbatm; /* Logical Block Application Tag Mask */
295 } NVME_WRITE_ZEROES;
296
297 //
298 // Compare command
299 //
300 typedef struct {
301 //
302 // CDW 10, 11
303 //
304 UINT64 Slba; /* Starting LBA */
305 //
306 // CDW 12
307 //
308 UINT16 Nlb; /* Number of Logical Blocks */
309 UINT16 Rsvd1 : 10;
310 UINT16 Prinfo : 4; /* Protection Info Check */
311 UINT16 Fua : 1; /* Force Unit Access */
312 UINT16 Lr : 1; /* Limited Retry */
313 //
314 // CDW 13
315 //
316 UINT32 Rsvd2;
317 //
318 // CDW 14
319 //
320 UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
321 //
322 // CDW 15
323 //
324 UINT16 Elbat; /* Expected Logical Block Application Tag */
325 UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
326 } NVME_COMPARE;
327
328 typedef union {
329 NVME_READ Read;
330 NVME_WRITE Write;
331 NVME_FLUSH Flush;
332 NVME_WRITE_UNCORRECTABLE WriteUncorrectable;
333 NVME_WRITE_ZEROES WriteZeros;
334 NVME_COMPARE Compare;
335 } NVME_CMD;
336
337 typedef struct {
338 UINT16 Mp; /* Maximum Power */
339 UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */
340 UINT8 Mps : 1; /* Max Power Scale */
341 UINT8 Nops : 1; /* Non-Operational State */
342 UINT8 Rsvd2 : 6; /* Reserved as of Nvm Express 1.1 Spec */
343 UINT32 Enlat; /* Entry Latency */
344 UINT32 Exlat; /* Exit Latency */
345 UINT8 Rrt : 5; /* Relative Read Throughput */
346 UINT8 Rsvd3 : 3; /* Reserved as of Nvm Express 1.1 Spec */
347 UINT8 Rrl : 5; /* Relative Read Latency */
348 UINT8 Rsvd4 : 3; /* Reserved as of Nvm Express 1.1 Spec */
349 UINT8 Rwt : 5; /* Relative Write Throughput */
350 UINT8 Rsvd5 : 3; /* Reserved as of Nvm Express 1.1 Spec */
351 UINT8 Rwl : 5; /* Relative Write Latency */
352 UINT8 Rsvd6 : 3; /* Reserved as of Nvm Express 1.1 Spec */
353 UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
354 } NVME_PSDESCRIPTOR;
355
356 //
357 // Identify Controller Data
358 //
359 typedef struct {
360 //
361 // Controller Capabilities and Features 0-255
362 //
363 UINT16 Vid; /* PCI Vendor ID */
364 UINT16 Ssvid; /* PCI sub-system vendor ID */
365 UINT8 Sn[20]; /* Product serial number */
366
367 UINT8 Mn[40]; /* Product model number */
368 UINT8 Fr[8]; /* Firmware Revision */
369 UINT8 Rab; /* Recommended Arbitration Burst */
370 UINT8 Ieee_oui[3]; /* Organization Unique Identifier */
371 UINT8 Cmic; /* Multi-interface Capabilities */
372 UINT8 Mdts; /* Maximum Data Transfer Size */
373 UINT8 Cntlid[2]; /* Controller ID */
374 UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
375 //
376 // Admin Command Set Attributes
377 //
378 UINT16 Oacs; /* Optional Admin Command Support */
379 #define NAMESPACE_MANAGEMENT_SUPPORTED BIT3
380 #define FW_DOWNLOAD_ACTIVATE_SUPPORTED BIT2
381 #define FORMAT_NVM_SUPPORTED BIT1
382 #define SECURITY_SEND_RECEIVE_SUPPORTED BIT0
383 UINT8 Acl; /* Abort Command Limit */
384 UINT8 Aerl; /* Async Event Request Limit */
385 UINT8 Frmw; /* Firmware updates */
386 UINT8 Lpa; /* Log Page Attributes */
387 UINT8 Elpe; /* Error Log Page Entries */
388 UINT8 Npss; /* Number of Power States Support */
389 UINT8 Avscc; /* Admin Vendor Specific Command Configuration */
390 UINT8 Apsta; /* Autonomous Power State Transition Attributes */
391 //
392 // Below fields before Rsvd2 are defined in NVM Express 1.4 Spec
393 //
394 UINT16 Wctemp; /* Warning Composite Temperature Threshold */
395 UINT16 Cctemp; /* Critical Composite Temperature Threshold */
396 UINT16 Mtfa; /* Maximum Time for Firmware Activation */
397 UINT32 Hmpre; /* Host Memory Buffer Preferred Size */
398 UINT32 Hmmin; /* Host Memory Buffer Minimum Size */
399 UINT8 Tnvmcap[16]; /* Total NVM Capacity */
400 UINT8 Unvmcap[16]; /* Unallocated NVM Capacity */
401 UINT32 Rpmbs; /* Replay Protected Memory Block Support */
402 UINT16 Edstt; /* Extended Device Self-test Time */
403 UINT8 Dsto; /* Device Self-test Options */
404 UINT8 Fwug; /* Firmware Update Granularity */
405 UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.4 Spec */
406 //
407 // NVM Command Set Attributes
408 //
409 UINT8 Sqes; /* Submission Queue Entry Size */
410 UINT8 Cqes; /* Completion Queue Entry Size */
411 UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
412 UINT32 Nn; /* Number of Namespaces */
413 UINT16 Oncs; /* Optional NVM Command Support */
414 UINT16 Fuses; /* Fused Operation Support */
415 UINT8 Fna; /* Format NVM Attributes */
416 UINT8 Vwc; /* Volatile Write Cache */
417 UINT16 Awun; /* Atomic Write Unit Normal */
418 UINT16 Awupf; /* Atomic Write Unit Power Fail */
419 UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
420 UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
421 UINT16 Acwu; /* Atomic Compare & Write Unit */
422 UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
423 UINT32 Sgls; /* SGL Support */
424 UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
425 //
426 // I/O Command set Attributes
427 //
428 UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
429 //
430 // Power State Descriptors
431 //
432 NVME_PSDESCRIPTOR PsDescriptor[32];
433
434 UINT8 VendorData[1024]; /* Vendor specific data */
435 } NVME_ADMIN_CONTROLLER_DATA;
436
437 typedef struct {
438 UINT16 Ms; /* Metadata Size */
439 UINT8 Lbads; /* LBA Data Size */
440 UINT8 Rp : 2; /* Relative Performance */
441 #define LBAF_RP_BEST 00b
442 #define LBAF_RP_BETTER 01b
443 #define LBAF_RP_GOOD 10b
444 #define LBAF_RP_DEGRADED 11b
445 UINT8 Rsvd1 : 6; /* Reserved as of Nvm Express 1.1 Spec */
446 } NVME_LBAFORMAT;
447
448 //
449 // Identify Namespace Data
450 //
451 typedef struct {
452 //
453 // NVM Command Set Specific
454 //
455 UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */
456 UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */
457 UINT64 Nuse; /* Namespace Utilization */
458 UINT8 Nsfeat; /* Namespace Features */
459 UINT8 Nlbaf; /* Number of LBA Formats */
460 UINT8 Flbas; /* Formatted LBA size */
461 UINT8 Mc; /* Metadata Capabilities */
462 UINT8 Dpc; /* End-to-end Data Protection capabilities */
463 UINT8 Dps; /* End-to-end Data Protection Type Settings */
464 UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
465 UINT8 Rescap; /* Reservation Capabilities */
466 UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */
467 UINT64 Eui64; /* IEEE Extended Unique Identifier */
468 //
469 // LBA Format
470 //
471 NVME_LBAFORMAT LbaFormat[16];
472
473 UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */
474 UINT8 VendorData[3712]; /* Vendor specific data */
475 } NVME_ADMIN_NAMESPACE_DATA;
476
477 //
478 // RPMB Device Configuration Block Data Structure as of Nvm Express 1.4 Spec
479 //
480 typedef struct {
481 UINT8 Bppe; /* Boot Partition Protection Enable */
482 UINT8 Bpl; /* Boot Partition Lock */
483 UINT8 Nwpac; /* Namespace Write Protection Authentication Control */
484 UINT8 Rsvd1[509]; /* Reserved as of Nvm Express 1.4 Spec */
485 } NVME_RPMB_CONFIGURATION_DATA;
486
487 #define RPMB_FRAME_STUFF_BYTES 223
488
489 //
490 // RPMB Data Frame as of Nvm Express 1.4 Spec
491 //
492 typedef struct {
493 UINT8 Sbakamc[RPMB_FRAME_STUFF_BYTES]; /* [222-N:00] Stuff Bytes */
494 /* [222:222-(N-1)] Authentication Key or Message Authentication Code (MAC) */
495 UINT8 Rpmbt; /* RPMB Target */
496 UINT64 Nonce[2];
497 UINT32 Wcounter; /* Write Counter */
498 UINT32 Address; /* Starting address of data to be programmed to or read from the RPMB. */
499 UINT32 Scount; /* Sector Count */
500 UINT16 Result;
501 UINT16 Rpmessage; /* Request/Response Message */
502 // UINT8 *Data; /* Data to be written or read by signed access where M = 512 * Sector Count. */
503 } NVME_RPMB_DATA_FRAME;
504
505 //
506 // NvmExpress Admin Identify Cmd
507 //
508 typedef struct {
509 //
510 // CDW 10
511 //
512 UINT32 Cns : 2;
513 UINT32 Rsvd1 : 30;
514 } NVME_ADMIN_IDENTIFY;
515
516 //
517 // NvmExpress Admin Create I/O Completion Queue
518 //
519 typedef struct {
520 //
521 // CDW 10
522 //
523 UINT32 Qid : 16; /* Queue Identifier */
524 UINT32 Qsize : 16; /* Queue Size */
525
526 //
527 // CDW 11
528 //
529 UINT32 Pc : 1; /* Physically Contiguous */
530 UINT32 Ien : 1; /* Interrupts Enabled */
531 UINT32 Rsvd1 : 14; /* reserved as of Nvm Express 1.1 Spec */
532 UINT32 Iv : 16; /* Interrupt Vector for MSI-X or MSI*/
533 } NVME_ADMIN_CRIOCQ;
534
535 //
536 // NvmExpress Admin Create I/O Submission Queue
537 //
538 typedef struct {
539 //
540 // CDW 10
541 //
542 UINT32 Qid : 16; /* Queue Identifier */
543 UINT32 Qsize : 16; /* Queue Size */
544
545 //
546 // CDW 11
547 //
548 UINT32 Pc : 1; /* Physically Contiguous */
549 UINT32 Qprio : 2; /* Queue Priority */
550 UINT32 Rsvd1 : 13; /* Reserved as of Nvm Express 1.1 Spec */
551 UINT32 Cqid : 16; /* Completion Queue ID */
552 } NVME_ADMIN_CRIOSQ;
553
554 //
555 // NvmExpress Admin Delete I/O Completion Queue
556 //
557 typedef struct {
558 //
559 // CDW 10
560 //
561 UINT16 Qid;
562 UINT16 Rsvd1;
563 } NVME_ADMIN_DEIOCQ;
564
565 //
566 // NvmExpress Admin Delete I/O Submission Queue
567 //
568 typedef struct {
569 //
570 // CDW 10
571 //
572 UINT16 Qid;
573 UINT16 Rsvd1;
574 } NVME_ADMIN_DEIOSQ;
575
576 //
577 // NvmExpress Admin Abort Command
578 //
579 typedef struct {
580 //
581 // CDW 10
582 //
583 UINT32 Sqid : 16; /* Submission Queue identifier */
584 UINT32 Cid : 16; /* Command Identifier */
585 } NVME_ADMIN_ABORT;
586
587 //
588 // NvmExpress Admin Firmware Activate Command
589 //
590 typedef struct {
591 //
592 // CDW 10
593 //
594 UINT32 Fs : 3; /* Submission Queue identifier */
595 UINT32 Aa : 2; /* Command Identifier */
596 UINT32 Rsvd1 : 27;
597 } NVME_ADMIN_FIRMWARE_ACTIVATE;
598
599 //
600 // NvmExpress Admin Firmware Image Download Command
601 //
602 typedef struct {
603 //
604 // CDW 10
605 //
606 UINT32 Numd; /* Number of Dwords */
607 //
608 // CDW 11
609 //
610 UINT32 Ofst; /* Offset */
611 } NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
612
613 //
614 // NvmExpress Admin Get Features Command
615 //
616 typedef struct {
617 //
618 // CDW 10
619 //
620 UINT32 Fid : 8; /* Feature Identifier */
621 UINT32 Sel : 3; /* Select */
622 UINT32 Rsvd1 : 21;
623 } NVME_ADMIN_GET_FEATURES;
624
625 //
626 // NvmExpress Admin Get Log Page Command
627 //
628 typedef struct {
629 //
630 // CDW 10
631 //
632 UINT32 Lid : 8; /* Log Page Identifier */
633 #define LID_ERROR_INFO 0x1
634 #define LID_SMART_INFO 0x2
635 #define LID_FW_SLOT_INFO 0x3
636 #define LID_BP_INFO 0x15
637 UINT32 Rsvd1 : 8;
638 UINT32 Numd : 12; /* Number of Dwords */
639 UINT32 Rsvd2 : 4; /* Reserved as of Nvm Express 1.1 Spec */
640 } NVME_ADMIN_GET_LOG_PAGE;
641
642 //
643 // NvmExpress Admin Set Features Command
644 //
645 typedef struct {
646 //
647 // CDW 10
648 //
649 UINT32 Fid : 8; /* Feature Identifier */
650 UINT32 Rsvd1 : 23;
651 UINT32 Sv : 1; /* Save */
652 } NVME_ADMIN_SET_FEATURES;
653
654 //
655 // NvmExpress Admin Format NVM Command
656 //
657 typedef struct {
658 //
659 // CDW 10
660 //
661 UINT32 Lbaf : 4; /* LBA Format */
662 UINT32 Ms : 1; /* Metadata Settings */
663 UINT32 Pi : 3; /* Protection Information */
664 UINT32 Pil : 1; /* Protection Information Location */
665 UINT32 Ses : 3; /* Secure Erase Settings */
666 UINT32 Rsvd1 : 20;
667 } NVME_ADMIN_FORMAT_NVM;
668
669 //
670 // NvmExpress Admin Security Receive Command
671 //
672 typedef struct {
673 //
674 // CDW 10
675 //
676 UINT32 Rsvd1 : 8;
677 UINT32 Spsp : 16; /* SP Specific */
678 UINT32 Secp : 8; /* Security Protocol */
679 //
680 // CDW 11
681 //
682 UINT32 Al; /* Allocation Length */
683 } NVME_ADMIN_SECURITY_RECEIVE;
684
685 //
686 // NvmExpress Admin Security Send Command
687 //
688 typedef struct {
689 //
690 // CDW 10
691 //
692 UINT32 Rsvd1 : 8;
693 UINT32 Spsp : 16; /* SP Specific */
694 UINT32 Secp : 8; /* Security Protocol */
695 //
696 // CDW 11
697 //
698 UINT32 Tl; /* Transfer Length */
699 } NVME_ADMIN_SECURITY_SEND;
700
701 typedef union {
702 NVME_ADMIN_IDENTIFY Identify;
703 NVME_ADMIN_CRIOCQ CrIoCq;
704 NVME_ADMIN_CRIOSQ CrIoSq;
705 NVME_ADMIN_DEIOCQ DeIoCq;
706 NVME_ADMIN_DEIOSQ DeIoSq;
707 NVME_ADMIN_ABORT Abort;
708 NVME_ADMIN_FIRMWARE_ACTIVATE Activate;
709 NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;
710 NVME_ADMIN_GET_FEATURES GetFeatures;
711 NVME_ADMIN_GET_LOG_PAGE GetLogPage;
712 NVME_ADMIN_SET_FEATURES SetFeatures;
713 NVME_ADMIN_FORMAT_NVM FormatNvm;
714 NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;
715 NVME_ADMIN_SECURITY_SEND SecuritySend;
716 } NVME_ADMIN_CMD;
717
718 typedef struct {
719 UINT32 Cdw10;
720 UINT32 Cdw11;
721 UINT32 Cdw12;
722 UINT32 Cdw13;
723 UINT32 Cdw14;
724 UINT32 Cdw15;
725 } NVME_RAW;
726
727 typedef union {
728 NVME_ADMIN_CMD Admin; // Union of Admin commands
729 NVME_CMD Nvm; // Union of Nvm commands
730 NVME_RAW Raw;
731 } NVME_PAYLOAD;
732
733 //
734 // Submission Queue
735 //
736 typedef struct {
737 //
738 // CDW 0, Common to all commands
739 //
740 UINT8 Opc; // Opcode
741 UINT8 Fuse : 2; // Fused Operation
742 UINT8 Rsvd1 : 5;
743 UINT8 Psdt : 1; // PRP or SGL for Data Transfer
744 UINT16 Cid; // Command Identifier
745
746 //
747 // CDW 1
748 //
749 UINT32 Nsid; // Namespace Identifier
750
751 //
752 // CDW 2,3
753 //
754 UINT64 Rsvd2;
755
756 //
757 // CDW 4,5
758 //
759 UINT64 Mptr; // Metadata Pointer
760
761 //
762 // CDW 6-9
763 //
764 UINT64 Prp[2]; // First and second PRP entries
765
766 NVME_PAYLOAD Payload;
767 } NVME_SQ;
768
769 //
770 // Completion Queue
771 //
772 typedef struct {
773 //
774 // CDW 0
775 //
776 UINT32 Dword0;
777 //
778 // CDW 1
779 //
780 UINT32 Rsvd1;
781 //
782 // CDW 2
783 //
784 UINT16 Sqhd; // Submission Queue Head Pointer
785 UINT16 Sqid; // Submission Queue Identifier
786 //
787 // CDW 3
788 //
789 UINT16 Cid; // Command Identifier
790 UINT16 Pt : 1; // Phase Tag
791 UINT16 Sc : 8; // Status Code
792 UINT16 Sct : 3; // Status Code Type
793 UINT16 Rsvd2 : 2;
794 UINT16 Mo : 1; // More
795 UINT16 Dnr : 1; // Do Not Retry
796 } NVME_CQ;
797
798 //
799 // Nvm Express Admin cmd opcodes
800 //
801 #define NVME_ADMIN_DEIOSQ_CMD 0x00
802 #define NVME_ADMIN_CRIOSQ_CMD 0x01
803 #define NVME_ADMIN_GET_LOG_PAGE_CMD 0x02
804 #define NVME_ADMIN_DEIOCQ_CMD 0x04
805 #define NVME_ADMIN_CRIOCQ_CMD 0x05
806 #define NVME_ADMIN_IDENTIFY_CMD 0x06
807 #define NVME_ADMIN_ABORT_CMD 0x08
808 #define NVME_ADMIN_SET_FEATURES_CMD 0x09
809 #define NVME_ADMIN_GET_FEATURES_CMD 0x0A
810 #define NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD 0x0C
811 #define NVME_ADMIN_NAMESACE_MANAGEMENT_CMD 0x0D
812 #define NVME_ADMIN_FW_COMMIT_CMD 0x10
813 #define NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD 0x11
814 #define NVME_ADMIN_NAMESACE_ATTACHMENT_CMD 0x15
815 #define NVME_ADMIN_FORMAT_NVM_CMD 0x80
816 #define NVME_ADMIN_SECURITY_SEND_CMD 0x81
817 #define NVME_ADMIN_SECURITY_RECEIVE_CMD 0x82
818
819 #define NVME_IO_FLUSH_OPC 0
820 #define NVME_IO_WRITE_OPC 1
821 #define NVME_IO_READ_OPC 2
822
823 typedef enum {
824 DeleteIOSubmissionQueueOpcode = NVME_ADMIN_DEIOSQ_CMD,
825 CreateIOSubmissionQueueOpcode = NVME_ADMIN_CRIOSQ_CMD,
826 GetLogPageOpcode = NVME_ADMIN_GET_LOG_PAGE_CMD,
827 DeleteIOCompletionQueueOpcode = NVME_ADMIN_DEIOCQ_CMD,
828 CreateIOCompletionQueueOpcode = NVME_ADMIN_CRIOCQ_CMD,
829 IdentifyOpcode = NVME_ADMIN_IDENTIFY_CMD,
830 AbortOpcode = NVME_ADMIN_ABORT_CMD,
831 SetFeaturesOpcode = NVME_ADMIN_SET_FEATURES_CMD,
832 GetFeaturesOpcode = NVME_ADMIN_GET_FEATURES_CMD,
833 AsyncEventRequestOpcode = NVME_ADMIN_ASYNC_EVENT_REQUEST_CMD,
834 NamespaceManagementOpcode = NVME_ADMIN_NAMESACE_MANAGEMENT_CMD,
835 FirmwareCommitOpcode = NVME_ADMIN_FW_COMMIT_CMD,
836 FirmwareImageDownloadOpcode = NVME_ADMIN_FW_IAMGE_DOWNLOAD_CMD,
837 NamespaceAttachmentOpcode = NVME_ADMIN_NAMESACE_ATTACHMENT_CMD,
838 FormatNvmOpcode = NVME_ADMIN_FORMAT_NVM_CMD,
839 SecuritySendOpcode = NVME_ADMIN_SECURITY_SEND_CMD,
840 SecurityReceiveOpcode = NVME_ADMIN_SECURITY_RECEIVE_CMD
841 } NVME_ADMIN_COMMAND_OPCODE;
842
843 //
844 // Controller or Namespace Structure (CNS) field
845 // (ref. spec. v1.1 figure 82).
846 //
847 typedef enum {
848 IdentifyNamespaceCns = 0x0,
849 IdentifyControllerCns = 0x1,
850 IdentifyActiveNsListCns = 0x2
851 } NVME_ADMIN_IDENTIFY_CNS;
852
853 //
854 // Commit Action
855 // (ref. spec. 1.1 figure 60).
856 //
857 typedef enum {
858 ActivateActionReplace = 0x0,
859 ActivateActionReplaceActivate = 0x1,
860 ActivateActionActivate = 0x2
861 } NVME_FW_ACTIVATE_ACTION;
862
863 //
864 // Firmware Slot
865 // (ref. spec. 1.1 Figure 60).
866 //
867 typedef enum {
868 FirmwareSlotCtrlChooses = 0x0,
869 FirmwareSlot1 = 0x1,
870 FirmwareSlot2 = 0x2,
871 FirmwareSlot3 = 0x3,
872 FirmwareSlot4 = 0x4,
873 FirmwareSlot5 = 0x5,
874 FirmwareSlot6 = 0x6,
875 FirmwareSlot7 = 0x7
876 } NVME_FW_ACTIVATE_SLOT;
877
878 //
879 // Get Log Page ? Log Page Identifiers
880 // (ref. spec. v1.1 Figure 73).
881 //
882 typedef enum {
883 ErrorInfoLogID = LID_ERROR_INFO,
884 SmartHealthInfoLogID = LID_SMART_INFO,
885 FirmwareSlotInfoLogID = LID_FW_SLOT_INFO
886 } NVME_LOG_ID;
887
888 //
889 // Get Log Page ? Firmware Slot Information Log
890 // (ref. spec. v1.1 Figure 77).
891 //
892 typedef struct {
893 //
894 // Indicates the firmware slot from which the actively running firmware revision was loaded.
895 //
896 UINT8 ActivelyRunningFwSlot : 3;
897 UINT8 : 1;
898 //
899 // Indicates the firmware slot that is going to be activated at the next controller reset. If this field is 0h, then the controller does not indicate the firmware slot that is going to be activated at the next controller reset.
900 //
901 UINT8 NextActiveFwSlot : 3;
902 UINT8 : 1;
903 } NVME_ACTIVE_FW_INFO;
904
905 //
906 // Get Log Page ? Firmware Slot Information Log
907 // (ref. spec. v1.1 Figure 77).
908 //
909 typedef struct {
910 //
911 // Specifies information about the active firmware revision.
912 // s
913 NVME_ACTIVE_FW_INFO ActiveFwInfo;
914 UINT8 Reserved1[7];
915 //
916 // Contains the revision of the firmware downloaded to firmware slot 1/7. If no valid firmware revision is present or if this slot is unsupported, all zeros shall be returned.
917 //
918 CHAR8 FwRevisionSlot[7][8];
919 UINT8 Reserved2[448];
920 } NVME_FW_SLOT_INFO_LOG;
921
922 //
923 // SMART / Health Information (Log Identifier 02h)
924 // (ref. spec. v1.1 5.10.1.2)
925 //
926 typedef struct {
927 //
928 // This field indicates critical warnings for the state of the controller.
929 //
930 UINT8 CriticalWarningAvailableSpare : 1;
931 UINT8 CriticalWarningTemperature : 1;
932 UINT8 CriticalWarningReliability : 1;
933 UINT8 CriticalWarningMediaReadOnly : 1;
934 UINT8 CriticalWarningVolatileBackup : 1;
935 UINT8 CriticalWarningReserved : 3;
936 //
937 // Contains a value corresponding to a temperature in degrees Kelvin that represents the current composite temperature of the controller and namespace(s) associated with that controller. The manner in which this value is computed is implementation specific and may not represent the actual temperature of any physical point in the NVM subsystem.
938 //
939 UINT16 CompositeTemp;
940 //
941 // Contains a normalized percentage (0 to 100%) of the remaining spare capacity available.
942 //
943 UINT8 AvailableSpare;
944 //
945 // When the Available Spare falls below the threshold indicated in this field, an asynchronous event completion may occur. The value is indicated as a normalized percentage (0 to 100%).
946 //
947 UINT8 AvailableSpareThreshold;
948 //
949 // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
950 //
951 UINT8 PercentageUsed;
952 UINT8 Reserved1[26];
953 //
954 // Contains the number of 512 byte data units the host has read from the controller; this value does not include metadata.
955 //
956 UINT8 DataUnitsRead[16];
957 //
958 // Contains the number of 512 byte data units the host has written to the controller; this value does not include metadata.
959 //
960 UINT8 DataUnitsWritten[16];
961 //
962 // Contains the number of read commands completed by the controller.
963 //
964 UINT8 HostReadCommands[16];
965 //
966 // Contains the number of write commands completed by the controller.
967 //
968 UINT8 HostWriteCommands[16];
969 //
970 // Contains the amount of time the controller is busy with I/O commands. This value is reported in minutes.
971 //
972 UINT8 ControllerBusyTime[16];
973 //
974 // Contains the number of power cycles.
975 //
976 UINT8 PowerCycles[16];
977 //
978 // Contains the number of power-on hours.
979 //
980 UINT8 PowerOnHours[16];
981 //
982 // Contains the number of unsafe shutdowns.
983 //
984 UINT8 UnsafeShutdowns[16];
985 //
986 // Contains the number of occurrences where the controller detected an unrecovered data integrity error.
987 //
988 UINT8 MediaAndDataIntegrityErrors[16];
989 //
990 // Contains the number of Error Information log entries over the life of the controller.
991 //
992 UINT8 NumberErrorInformationLogEntries[16];
993 //
994 // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater than or equal to the Warning Composite Temperature Threshold (WCTEMP) field and less than the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
995 //
996 UINT32 WarningCompositeTemperatureTime;
997 //
998 // Contains the amount of time in minutes that the controller is operational and the Composite Temperature is greater the Critical Composite Temperature Threshold (CCTEMP) field in the Identify Controller data structure in Figure 90.
999 //
1000 UINT32 CriticalCompositeTemperatureTime;
1001 //
1002 // Contains the current temperature in degrees Kelvin reported by the temperature sensor. An implementation that does not implement the temperature sensor reports a temperature of zero degrees Kelvin.
1003 //
1004 UINT16 TemperatureSensor[8];
1005 UINT8 Reserved2[296];
1006 } NVME_SMART_HEALTH_INFO_LOG;
1007
1008 #pragma pack()
1009
1010 #endif
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