2 Support for the latest PCI standard.
4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #ifndef _PCIEXPRESS21_H_
11 #define _PCIEXPRESS21_H_
13 #include <IndustryStandard/Pci30.h>
16 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
17 ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits
18 of Bus, Device, Function and Register are stripped prior to the generation of
21 @param Bus PCI Bus number. Range 0..255.
22 @param Device PCI Device number. Range 0..31.
23 @param Function PCI Function number. Range 0..7.
24 @param Register PCI Register number. Range 0..4095.
26 @return The encode ECAM address.
29 #define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \
30 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
34 /// PCI Express Capability Structure
39 UINT16 DevicePortType
: 4;
40 UINT16 SlotImplemented
: 1;
41 UINT16 InterruptMessageNumber
: 5;
46 } PCI_REG_PCIE_CAPABILITY
;
48 #define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0
49 #define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1
50 #define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4
51 #define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5
52 #define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6
53 #define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7
54 #define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8
55 #define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9
56 #define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10
60 UINT32 MaxPayloadSize
: 3;
61 UINT32 PhantomFunctions
: 2;
62 UINT32 ExtendedTagField
: 1;
63 UINT32 EndpointL0sAcceptableLatency
: 3;
64 UINT32 EndpointL1AcceptableLatency
: 3;
66 UINT32 RoleBasedErrorReporting
: 1;
68 UINT32 CapturedSlotPowerLimitValue
: 8;
69 UINT32 CapturedSlotPowerLimitScale
: 2;
70 UINT32 FunctionLevelReset
: 1;
74 } PCI_REG_PCIE_DEVICE_CAPABILITY
;
78 UINT16 CorrectableError
: 1;
79 UINT16 NonFatalError
: 1;
80 UINT16 FatalError
: 1;
81 UINT16 UnsupportedRequest
: 1;
82 UINT16 RelaxedOrdering
: 1;
83 UINT16 MaxPayloadSize
: 3;
84 UINT16 ExtendedTagField
: 1;
85 UINT16 PhantomFunctions
: 1;
88 UINT16 MaxReadRequestSize
: 3;
89 UINT16 BridgeConfigurationRetryOrFunctionLevelReset
: 1;
92 } PCI_REG_PCIE_DEVICE_CONTROL
;
96 UINT16 CorrectableError
: 1;
97 UINT16 NonFatalError
: 1;
98 UINT16 FatalError
: 1;
99 UINT16 UnsupportedRequest
: 1;
101 UINT16 TransactionsPending
: 1;
102 UINT16 Reserved
: 10;
105 } PCI_REG_PCIE_DEVICE_STATUS
;
109 UINT32 MaxLinkSpeed
: 4;
110 UINT32 MaxLinkWidth
: 6;
112 UINT32 L0sExitLatency
: 3;
113 UINT32 L1ExitLatency
: 3;
114 UINT32 ClockPowerManagement
: 1;
115 UINT32 SurpriseDownError
: 1;
116 UINT32 DataLinkLayerLinkActive
: 1;
117 UINT32 LinkBandwidthNotification
: 1;
118 UINT32 AspmOptionalityCompliance
: 1;
120 UINT32 PortNumber
: 8;
123 } PCI_REG_PCIE_LINK_CAPABILITY
;
125 #define PCIE_LINK_ASPM_L0S BIT0
126 #define PCIE_LINK_ASPM_L1 BIT1
130 UINT16 AspmControl
: 2;
132 UINT16 ReadCompletionBoundary
: 1;
133 UINT16 LinkDisable
: 1;
134 UINT16 RetrainLink
: 1;
135 UINT16 CommonClockConfiguration
: 1;
136 UINT16 ExtendedSynch
: 1;
137 UINT16 ClockPowerManagement
: 1;
138 UINT16 HardwareAutonomousWidthDisable
: 1;
139 UINT16 LinkBandwidthManagementInterrupt
: 1;
140 UINT16 LinkAutonomousBandwidthInterrupt
: 1;
143 } PCI_REG_PCIE_LINK_CONTROL
;
147 UINT16 CurrentLinkSpeed
: 4;
148 UINT16 NegotiatedLinkWidth
: 6;
149 UINT16 Undefined
: 1;
150 UINT16 LinkTraining
: 1;
151 UINT16 SlotClockConfiguration
: 1;
152 UINT16 DataLinkLayerLinkActive
: 1;
153 UINT16 LinkBandwidthManagement
: 1;
154 UINT16 LinkAutonomousBandwidth
: 1;
157 } PCI_REG_PCIE_LINK_STATUS
;
161 UINT32 AttentionButton
: 1;
162 UINT32 PowerController
: 1;
163 UINT32 MrlSensor
: 1;
164 UINT32 AttentionIndicator
: 1;
165 UINT32 PowerIndicator
: 1;
166 UINT32 HotPlugSurprise
: 1;
167 UINT32 HotPlugCapable
: 1;
168 UINT32 SlotPowerLimitValue
: 8;
169 UINT32 SlotPowerLimitScale
: 2;
170 UINT32 ElectromechanicalInterlock
: 1;
171 UINT32 NoCommandCompleted
: 1;
172 UINT32 PhysicalSlotNumber
: 13;
175 } PCI_REG_PCIE_SLOT_CAPABILITY
;
179 UINT16 AttentionButtonPressed
: 1;
180 UINT16 PowerFaultDetected
: 1;
181 UINT16 MrlSensorChanged
: 1;
182 UINT16 PresenceDetectChanged
: 1;
183 UINT16 CommandCompletedInterrupt
: 1;
184 UINT16 HotPlugInterrupt
: 1;
185 UINT16 AttentionIndicator
: 2;
186 UINT16 PowerIndicator
: 2;
187 UINT16 PowerController
: 1;
188 UINT16 ElectromechanicalInterlock
: 1;
189 UINT16 DataLinkLayerStateChanged
: 1;
193 } PCI_REG_PCIE_SLOT_CONTROL
;
197 UINT16 AttentionButtonPressed
: 1;
198 UINT16 PowerFaultDetected
: 1;
199 UINT16 MrlSensorChanged
: 1;
200 UINT16 PresenceDetectChanged
: 1;
201 UINT16 CommandCompleted
: 1;
202 UINT16 MrlSensor
: 1;
203 UINT16 PresenceDetect
: 1;
204 UINT16 ElectromechanicalInterlock
: 1;
205 UINT16 DataLinkLayerStateChanged
: 1;
209 } PCI_REG_PCIE_SLOT_STATUS
;
213 UINT16 SystemErrorOnCorrectableError
: 1;
214 UINT16 SystemErrorOnNonFatalError
: 1;
215 UINT16 SystemErrorOnFatalError
: 1;
216 UINT16 PmeInterrupt
: 1;
217 UINT16 CrsSoftwareVisibility
: 1;
218 UINT16 Reserved
: 11;
221 } PCI_REG_PCIE_ROOT_CONTROL
;
225 UINT16 CrsSoftwareVisibility
: 1;
226 UINT16 Reserved
: 15;
229 } PCI_REG_PCIE_ROOT_CAPABILITY
;
233 UINT32 PmeRequesterId
: 16;
234 UINT32 PmeStatus
: 1;
235 UINT32 PmePending
: 1;
236 UINT32 Reserved
: 14;
239 } PCI_REG_PCIE_ROOT_STATUS
;
243 UINT32 CompletionTimeoutRanges
: 4;
244 UINT32 CompletionTimeoutDisable
: 1;
245 UINT32 AriForwarding
: 1;
246 UINT32 AtomicOpRouting
: 1;
247 UINT32 AtomicOp32Completer
: 1;
248 UINT32 AtomicOp64Completer
: 1;
249 UINT32 Cas128Completer
: 1;
250 UINT32 NoRoEnabledPrPrPassing
: 1;
251 UINT32 LtrMechanism
: 1;
252 UINT32 TphCompleter
: 2;
255 UINT32 ExtendedFmtField
: 1;
256 UINT32 EndEndTlpPrefix
: 1;
257 UINT32 MaxEndEndTlpPrefixes
: 2;
258 UINT32 Reserved2
: 8;
261 } PCI_REG_PCIE_DEVICE_CAPABILITY2
;
263 #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
264 #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
268 UINT16 CompletionTimeoutValue
: 4;
269 UINT16 CompletionTimeoutDisable
: 1;
270 UINT16 AriForwarding
: 1;
271 UINT16 AtomicOpRequester
: 1;
272 UINT16 AtomicOpEgressBlocking
: 1;
273 UINT16 IdoRequest
: 1;
274 UINT16 IdoCompletion
: 1;
275 UINT16 LtrMechanism
: 2;
278 UINT16 EndEndTlpPrefixBlocking
: 1;
281 } PCI_REG_PCIE_DEVICE_CONTROL2
;
283 #define PCIE_COMPLETION_TIMEOUT_50US_50MS 0
284 #define PCIE_COMPLETION_TIMEOUT_50US_100US 1
285 #define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2
286 #define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5
287 #define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6
288 #define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9
289 #define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10
290 #define PCIE_COMPLETION_TIMEOUT_4S_13S 13
291 #define PCIE_COMPLETION_TIMEOUT_17S_64S 14
293 #define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0
294 #define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1
295 #define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2
296 #define PCIE_DEVICE_CONTROL_OBFF_WAKE 3
301 UINT32 LinkSpeedsVector
: 7;
302 UINT32 Crosslink
: 1;
303 UINT32 Reserved2
: 23;
306 } PCI_REG_PCIE_LINK_CAPABILITY2
;
310 UINT16 TargetLinkSpeed
: 4;
311 UINT16 EnterCompliance
: 1;
312 UINT16 HardwareAutonomousSpeedDisable
: 1;
313 UINT16 SelectableDeemphasis
: 1;
314 UINT16 TransmitMargin
: 3;
315 UINT16 EnterModifiedCompliance
: 1;
316 UINT16 ComplianceSos
: 1;
317 UINT16 CompliancePresetDeemphasis
: 4;
320 } PCI_REG_PCIE_LINK_CONTROL2
;
324 UINT16 CurrentDeemphasisLevel
: 1;
325 UINT16 EqualizationComplete
: 1;
326 UINT16 EqualizationPhase1Successful
: 1;
327 UINT16 EqualizationPhase2Successful
: 1;
328 UINT16 EqualizationPhase3Successful
: 1;
329 UINT16 LinkEqualizationRequest
: 1;
330 UINT16 Reserved
: 10;
333 } PCI_REG_PCIE_LINK_STATUS2
;
336 EFI_PCI_CAPABILITY_HDR Hdr
;
337 PCI_REG_PCIE_CAPABILITY Capability
;
338 PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability
;
339 PCI_REG_PCIE_DEVICE_CONTROL DeviceControl
;
340 PCI_REG_PCIE_DEVICE_STATUS DeviceStatus
;
341 PCI_REG_PCIE_LINK_CAPABILITY LinkCapability
;
342 PCI_REG_PCIE_LINK_CONTROL LinkControl
;
343 PCI_REG_PCIE_LINK_STATUS LinkStatus
;
344 PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability
;
345 PCI_REG_PCIE_SLOT_CONTROL SlotControl
;
346 PCI_REG_PCIE_SLOT_STATUS SlotStatus
;
347 PCI_REG_PCIE_ROOT_CONTROL RootControl
;
348 PCI_REG_PCIE_ROOT_CAPABILITY RootCapability
;
349 PCI_REG_PCIE_ROOT_STATUS RootStatus
;
350 PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2
;
351 PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2
;
352 UINT16 DeviceStatus2
;
353 PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2
;
354 PCI_REG_PCIE_LINK_CONTROL2 LinkControl2
;
355 PCI_REG_PCIE_LINK_STATUS2 LinkStatus2
;
356 UINT32 SlotCapability2
;
359 } PCI_CAPABILITY_PCIEXP
;
361 #define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
362 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
363 #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
364 #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20
365 #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28
366 #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
371 #define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
372 #define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
373 #define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
374 #define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
377 UINT32 CapabilityHeader
;
384 UINT8 FunctionDependencyLink
;
386 UINT16 FirstVFOffset
;
390 UINT32 SupportedPageSize
;
391 UINT32 SystemPageSize
;
393 UINT32 VFMigrationStateArrayOffset
;
394 } SR_IOV_CAPABILITY_REGISTER
;
396 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04
397 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08
398 #define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A
399 #define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C
400 #define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E
401 #define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10
402 #define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12
403 #define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14
404 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16
405 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A
406 #define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C
407 #define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20
408 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24
409 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28
410 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C
411 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30
412 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34
413 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38
414 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C
417 UINT32 CapabilityId
:16;
418 UINT32 CapabilityVersion
:4;
419 UINT32 NextCapabilityOffset
:12;
420 } PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
;
422 #define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
424 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001
425 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
426 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
430 UINT32 Undefined
: 1;
432 UINT32 DataLinkProtocolError
: 1;
433 UINT32 SurpriseDownError
: 1;
434 UINT32 Reserved2
: 6;
435 UINT32 PoisonedTlp
: 1;
436 UINT32 FlowControlProtocolError
: 1;
437 UINT32 CompletionTimeout
: 1;
438 UINT32 CompleterAbort
: 1;
439 UINT32 UnexpectedCompletion
: 1;
440 UINT32 ReceiverOverflow
: 1;
441 UINT32 MalformedTlp
: 1;
442 UINT32 EcrcError
: 1;
443 UINT32 UnsupportedRequestError
: 1;
444 UINT32 AcsVoilation
: 1;
445 UINT32 UncorrectableInternalError
: 1;
446 UINT32 McBlockedTlp
: 1;
447 UINT32 AtomicOpEgressBlocked
: 1;
448 UINT32 TlpPrefixBlockedError
: 1;
449 UINT32 Reserved3
: 6;
452 } PCI_EXPRESS_REG_UNCORRECTABLE_ERROR
;
455 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
456 PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus
;
457 PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask
;
458 PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity
;
459 UINT32 CorrectableErrorStatus
;
460 UINT32 CorrectableErrorMask
;
461 UINT32 AdvancedErrorCapabilitiesAndControl
;
463 UINT32 RootErrorCommand
;
464 UINT32 RootErrorStatus
;
465 UINT16 ErrorSourceIdentification
;
466 UINT16 CorrectableErrorSourceIdentification
;
467 UINT32 TlpPrefixLog
[4];
468 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
;
470 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002
471 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009
472 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1
475 UINT32 VcResourceCapability
:24;
476 UINT32 PortArbTableOffset
:8;
477 UINT32 VcResourceControl
;
479 UINT16 VcResourceStatus
;
480 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
;
483 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
484 UINT32 ExtendedVcCount
:3;
485 UINT32 PortVcCapability1
:29;
486 UINT32 PortVcCapability2
:24;
487 UINT32 VcArbTableOffset
:8;
488 UINT16 PortVcControl
;
490 PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability
[1];
491 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
;
493 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003
494 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1
497 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
499 } PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
;
501 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005
502 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1
505 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
506 UINT32 ElementSelfDescription
;
509 } PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
;
511 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
513 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006
514 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1
517 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
518 UINT32 RootComplexLinkCapabilities
;
519 UINT16 RootComplexLinkControl
;
520 UINT16 RootComplexLinkStatus
;
521 } PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
;
523 #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004
524 #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1
527 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
531 UINT32 PowerBudgetCapability
:1;
534 } PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
;
536 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D
537 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1
540 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
541 UINT16 AcsCapability
;
543 UINT8 EgressControlVectorArray
[1];
544 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
;
546 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
547 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
549 #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007
550 #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1
553 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
554 UINT32 AssociationBitmap
;
555 } PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
;
557 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008
558 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1
560 typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY
;
562 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B
563 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1
566 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
567 UINT32 VendorSpecificHeader
;
568 UINT8 VendorSpecific
[1];
569 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
;
571 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
573 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A
574 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1
577 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
580 UINT32 RcrbCapabilities
;
583 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
;
585 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012
586 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1
589 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
590 UINT16 MultiCastCapability
;
591 UINT16 MulticastControl
;
592 UINT64 McBaseAddress
;
593 UINT64 McReceiveAddress
;
595 UINT64 McBlockUntranslated
;
597 } PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
;
599 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015
600 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1
603 UINT32 ResizableBarCapability
;
604 UINT16 ResizableBarControl
;
606 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY
;
609 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
610 PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability
[1];
611 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
;
613 #define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)
615 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E
616 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1
619 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
620 UINT16 AriCapability
;
622 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
;
624 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016
625 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1
628 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
629 UINT32 DpaCapability
;
630 UINT32 DpaLatencyIndicator
;
633 UINT8 DpaPowerAllocationArray
[1];
634 } PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
;
636 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))
639 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018
640 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1
643 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
644 UINT16 MaxSnoopLatency
;
645 UINT16 MaxNoSnoopLatency
;
646 } PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
;
648 #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017
649 #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1
652 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
653 UINT32 TphRequesterCapability
;
654 UINT32 TphRequesterControl
;
655 UINT16 TphStTable
[1];
656 } PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
;
658 #define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)