MdePkg/Include/IndustryStandard/Sal.h

   1 /** @file
   2   Main SAL API's defined in SAL 3.0 specification.
   3
   4   Copyright (c) 2006, Intel Corporation
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __SAL_API_H__
  16 #define __SAL_API_H__
  17
  18 ///
  19 /// FIT Types
  20 /// Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003
  21 ///
  22 #define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00
  23 #define EFI_SAL_FIT_PAL_B_TYPE      0x01
  24
  25 ///
  26 /// type from 0x02 to 0x0E is reserved.
  27 ///
  28 #define EFI_SAL_FIT_PAL_A_TYPE  0x0F
  29
  30 ///
  31 /// OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10
  32 ///
  33 #define EFI_SAL_FIT_PEI_CORE_TYPE 0x10
  34 #define EFI_SAL_FIT_UNUSED_TYPE   0x7F
  35
  36 ///
  37 /// EFI_SAL_STATUS
  38 ///
  39 typedef UINTN EFI_SAL_STATUS;
  40
  41 #define EFI_SAL_SUCCESS               ((EFI_SAL_STATUS) 0)
  42 #define EFI_SAL_MORE_RECORDS          ((EFI_SAL_STATUS) 3)
  43 #define EFI_SAL_NOT_IMPLEMENTED       ((EFI_SAL_STATUS) - 1)
  44 #define EFI_SAL_INVALID_ARGUMENT      ((EFI_SAL_STATUS) - 2)
  45 #define EFI_SAL_ERROR                 ((EFI_SAL_STATUS) - 3)
  46 #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
  47 #define EFI_SAL_NO_INFORMATION        ((EFI_SAL_STATUS) - 5)
  48 #define EFI_SAL_NOT_ENOUGH_SCRATCH    ((EFI_SAL_STATUS) - 9)
  49
  50 //
  51 //  Return values from SAL
  52 //
  53 typedef struct {
  54   EFI_SAL_STATUS  Status; // register r8
  55   UINTN           r9;
  56   UINTN           r10;
  57   UINTN           r11;
  58 } SAL_RETURN_REGS;
  59
  60 ///
  61 ///  Delivery Mode of IPF CPU.
  62 ///
  63 typedef enum {
  64   EFI_DELIVERY_MODE_INT,
  65   EFI_DELIVERY_MODE_MPreserved1,
  66   EFI_DELIVERY_MODE_PMI,
  67   EFI_DELIVERY_MODE_MPreserved2,
  68   EFI_DELIVERY_MODE_NMI,
  69   EFI_DELIVERY_MODE_INIT,
  70   EFI_DELIVERY_MODE_MPreserved3,
  71   EFI_DELIVERY_MODE_ExtINT
  72 } EFI_DELIVERY_MODE;
  73
  74 typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)
  75   (
  76     IN UINT64 FunctionId,
  77     IN UINT64 Arg2,
  78     IN UINT64 Arg3,
  79     IN UINT64 Arg4,
  80     IN UINT64 Arg5,
  81     IN UINT64 Arg6,
  82     IN UINT64 Arg7,
  83     IN UINT64 Arg8
  84   );
  85
  86 //
  87 // SAL Procedure FunctionId definition
  88 //
  89 #define EFI_SAL_SET_VECTORS             0x01000000
  90 #define EFI_SAL_GET_STATE_INFO          0x01000001
  91 #define EFI_SAL_GET_STATE_INFO_SIZE     0x01000002
  92 #define EFI_SAL_CLEAR_STATE_INFO        0x01000003
  93 #define EFI_SAL_MC_RENDEZ               0x01000004
  94 #define EFI_SAL_MC_SET_PARAMS           0x01000005
  95 #define EFI_SAL_REGISTER_PHYSICAL_ADDR  0x01000006
  96 #define EFI_SAL_CACHE_FLUSH             0x01000008
  97 #define EFI_SAL_CACHE_INIT              0x01000009
  98 #define EFI_SAL_PCI_CONFIG_READ         0x01000010
  99 #define EFI_SAL_PCI_CONFIG_WRITE        0x01000011
 100 #define EFI_SAL_FREQ_BASE               0x01000012
 101 #define EFI_SAL_PHYSICAL_ID_INFO        0x01000013
 102 #define EFI_SAL_UPDATE_PAL              0x01000020
 103
 104 #define EFI_SAL_FUNCTION_ID_MASK        0x0000ffff
 105 #define EFI_SAL_MAX_SAL_FUNCTION_ID     0x00000021
 106
 107 //
 108 // SAL Procedure parameter definitions
 109 // Not much point in using typedefs or enums because all params
 110 // are UINT64 and the entry point is common
 111 //
 112 // EFI_SAL_SET_VECTORS
 113 //
 114 #define EFI_SAL_SET_MCA_VECTOR          0x0
 115 #define EFI_SAL_SET_INIT_VECTOR         0x1
 116 #define EFI_SAL_SET_BOOT_RENDEZ_VECTOR  0x2
 117
 118 typedef struct {
 119   UINT64  Length : 32;
 120   UINT64  ChecksumValid : 1;
 121   UINT64  Reserved1 : 7;
 122   UINT64  ByteChecksum : 8;
 123   UINT64  Reserved2 : 16;
 124 } SAL_SET_VECTORS_CS_N;
 125
 126 //
 127 // EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,
 128 // EFI_SAL_CLEAR_STATE_INFO
 129 //
 130 #define EFI_SAL_MCA_STATE_INFO  0x0
 131 #define EFI_SAL_INIT_STATE_INFO 0x1
 132 #define EFI_SAL_CMC_STATE_INFO  0x2
 133 #define EFI_SAL_CP_STATE_INFO   0x3
 134
 135 //
 136 // EFI_SAL_MC_SET_PARAMS
 137 //
 138 #define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
 139 #define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
 140 #define EFI_SAL_MC_SET_CPE_PARAM    0x3
 141
 142 #define EFI_SAL_MC_SET_INTR_PARAM   0x1
 143 #define EFI_SAL_MC_SET_MEM_PARAM    0x2
 144
 145 //
 146 // EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
 147 //
 148 #define EFI_SAL_REGISTER_PAL_ADDR 0x0
 149
 150 //
 151 // EFI_SAL_CACHE_FLUSH
 152 //
 153 #define EFI_SAL_FLUSH_I_CACHE       0x01
 154 #define EFI_SAL_FLUSH_D_CACHE       0x02
 155 #define EFI_SAL_FLUSH_BOTH_CACHE    0x03
 156 #define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
 157
 158 //
 159 // EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE
 160 //
 161 #define EFI_SAL_PCI_CONFIG_ONE_BYTE   0x1
 162 #define EFI_SAL_PCI_CONFIG_TWO_BYTES  0x2
 163 #define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
 164
 165 typedef struct {
 166   UINT64  Register : 8;
 167   UINT64  Function : 3;
 168   UINT64  Device : 5;
 169   UINT64  Bus : 8;
 170   UINT64  Segment : 8;
 171   UINT64  Reserved : 32;
 172 } SAL_PCI_ADDRESS;
 173
 174 //
 175 // EFI_SAL_FREQ_BASE
 176 //
 177 #define EFI_SAL_CPU_INPUT_FREQ_BASE     0x0
 178 #define EFI_SAL_PLATFORM_IT_FREQ_BASE   0x1
 179 #define EFI_SAL_PLATFORM_RTC_FREQ_BASE  0x2
 180
 181 //
 182 // EFI_SAL_UPDATE_PAL
 183 //
 184 #define EFI_SAL_UPDATE_BAD_PAL_VERSION  ((UINT64) -1)
 185 #define EFI_SAL_UPDATE_PAL_AUTH_FAIL    ((UINT64) -2)
 186 #define EFI_SAL_UPDATE_PAL_BAD_TYPE     ((UINT64) -3)
 187 #define EFI_SAL_UPDATE_PAL_READONLY     ((UINT64) -4)
 188 #define EFI_SAL_UPDATE_PAL_WRITE_FAIL   ((UINT64) -10)
 189 #define EFI_SAL_UPDATE_PAL_ERASE_FAIL   ((UINT64) -11)
 190 #define EFI_SAL_UPDATE_PAL_READ_FAIL    ((UINT64) -12)
 191 #define EFI_SAL_UPDATE_PAL_CANT_FIT     ((UINT64) -13)
 192
 193 typedef struct {
 194   UINT32  Size;
 195   UINT32  MmddyyyyDate;
 196   UINT16  Version;
 197   UINT8   Type;
 198   UINT8   Reserved[5];
 199   UINT64  FwVendorId;
 200 } SAL_UPDATE_PAL_DATA_BLOCK;
 201
 202 typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
 203   struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;
 204   struct SAL_UPDATE_PAL_DATA_BLOCK  *DataBlock;
 205   UINT8                             StoreChecksum;
 206   UINT8                             Reserved[15];
 207 } SAL_UPDATE_PAL_INFO_BLOCK;
 208
 209 //
 210 // SAL System Table Definitions
 211 //
 212 #pragma pack(1)
 213 typedef struct {
 214   UINT32  Signature;
 215   UINT32  Length;
 216   UINT16  SalRevision;
 217   UINT16  EntryCount;
 218   UINT8   CheckSum;
 219   UINT8   Reserved[7];
 220   UINT16  SalAVersion;
 221   UINT16  SalBVersion;
 222   UINT8   OemId[32];
 223   UINT8   ProductId[32];
 224   UINT8   Reserved2[8];
 225 } SAL_SYSTEM_TABLE_HEADER;
 226 #pragma pack()
 227
 228 #define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
 229 #define EFI_SAL_REVISION            0x0300
 230 //
 231 // SAL System Types
 232 //
 233 #define EFI_SAL_ST_ENTRY_POINT        0
 234 #define EFI_SAL_ST_MEMORY_DESCRIPTOR  1
 235 #define EFI_SAL_ST_PLATFORM_FEATURES  2
 236 #define EFI_SAL_ST_TR_USAGE           3
 237 #define EFI_SAL_ST_PTC                4
 238 #define EFI_SAL_ST_AP_WAKEUP          5
 239
 240 //
 241 // SAL System Type Sizes
 242 //
 243 #define EFI_SAL_ST_ENTRY_POINT_SIZE        48
 244 #define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE  32
 245 #define EFI_SAL_ST_PLATFORM_FEATURES_SIZE  16
 246 #define EFI_SAL_ST_TR_USAGE_SIZE           32
 247 #define EFI_SAL_ST_PTC_SIZE                16
 248 #define EFI_SAL_ST_AP_WAKEUP_SIZE          16
 249
 250 #pragma pack(1)
 251 typedef struct {
 252   UINT8   Type; //  Type == 0
 253   UINT8   Reserved[7];
 254   UINT64  PalProcEntry;
 255   UINT64  SalProcEntry;
 256   UINT64  SalGlobalDataPointer;
 257   UINT64  Reserved2[2];
 258 } SAL_ST_ENTRY_POINT_DESCRIPTOR;
 259
 260 #pragma pack(1)
 261 typedef struct {
 262   UINT8 Type;                     // Type == 2
 263   UINT8 PlatformFeatures;
 264   UINT8 Reserved[14];
 265 } SAL_ST_PLATFORM_FEATURES;
 266 #pragma pack()
 267
 268 #define SAL_PLAT_FEAT_BUS_LOCK      0x01
 269 #define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
 270 #define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
 271
 272 #pragma pack(1)
 273 typedef struct {
 274   UINT8   Type;                   // Type == 3
 275   UINT8   TRType;
 276   UINT8   TRNumber;
 277   UINT8   Reserved[5];
 278   UINT64  VirtualAddress;
 279   UINT64  EncodedPageSize;
 280   UINT64  Reserved1;
 281 } SAL_ST_TR_DECRIPTOR;
 282 #pragma pack()
 283
 284 #define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
 285 #define EFI_SAL_ST_TR_USAGE_DATA        01
 286
 287 #pragma pack(1)
 288 typedef struct {
 289   UINT64  NumberOfProcessors;
 290   UINT64  LocalIDRegister;
 291 } SAL_COHERENCE_DOMAIN_INFO;
 292 #pragma pack()
 293
 294 #pragma pack(1)
 295 typedef struct {
 296   UINT8                     Type; // Type == 4
 297   UINT8                     Reserved[3];
 298   UINT32                    NumberOfDomains;
 299   SAL_COHERENCE_DOMAIN_INFO *DomainInformation;
 300 } SAL_ST_CACHE_COHERENCE_DECRIPTOR;
 301 #pragma pack()
 302
 303 #pragma pack(1)
 304 typedef struct {
 305   UINT8   Type;                   // Type == 5
 306   UINT8   WakeUpType;
 307   UINT8   Reserved[6];
 308   UINT64  ExternalInterruptVector;
 309 } SAL_ST_AP_WAKEUP_DECRIPTOR;
 310 #pragma pack()
 311 //
 312 // FIT Entry
 313 //
 314 #define EFI_SAL_FIT_ENTRY_PTR   (0x100000000 - 32)  // 4GB - 24
 315 #define EFI_SAL_FIT_PALA_ENTRY  (0x100000000 - 48)  // 4GB - 32
 316 #define EFI_SAL_FIT_PALB_TYPE   01
 317
 318 typedef struct {
 319   UINT64  Address;
 320   UINT8   Size[3];
 321   UINT8   Reserved;
 322   UINT16  Revision;
 323   UINT8   Type : 7;
 324   UINT8   CheckSumValid : 1;
 325   UINT8   CheckSum;
 326 } EFI_SAL_FIT_ENTRY;
 327
 328 //
 329 //  SAL Common Record Header
 330 //
 331 typedef struct {
 332   UINT16  Length;
 333   UINT8   Data[1024];
 334 } SAL_OEM_DATA;
 335
 336 typedef struct {
 337   UINT8 Seconds;
 338   UINT8 Minutes;
 339   UINT8 Hours;
 340   UINT8 Reserved;
 341   UINT8 Day;
 342   UINT8 Month;
 343   UINT8 Year;
 344   UINT8 Century;
 345 } SAL_TIME_STAMP;
 346
 347 typedef struct {
 348   UINT64          RecordId;
 349   UINT16          Revision;
 350   UINT8           ErrorSeverity;
 351   UINT8           ValidationBits;
 352   UINT32          RecordLength;
 353   SAL_TIME_STAMP  TimeStamp;
 354   UINT8           OemPlatformId[16];
 355 } SAL_RECORD_HEADER;
 356
 357 typedef struct {
 358   GUID                  Guid;
 359   UINT16    Revision;
 360   UINT8     ErrorRecoveryInfo;
 361   UINT8     Reserved;
 362   UINT32    SectionLength;
 363 } SAL_SEC_HEADER;
 364
 365 //
 366 // SAL Processor Record
 367 //
 368 #define SAL_PROCESSOR_ERROR_RECORD_INFO \
 369   { \
 370     0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 371   }
 372
 373 #define CHECK_INFO_VALID_BIT_MASK   0x1
 374 #define REQUESTOR_ID_VALID_BIT_MASK 0x2
 375 #define RESPONDER_ID_VALID_BIT_MASK 0x4
 376 #define TARGER_ID_VALID_BIT_MASK    0x8
 377 #define PRECISE_IP_VALID_BIT_MASK   0x10
 378
 379 typedef struct {
 380   UINT64  InfoValid : 1;
 381   UINT64  ReqValid : 1;
 382   UINT64  RespValid : 1;
 383   UINT64  TargetValid : 1;
 384   UINT64  IpValid : 1;
 385   UINT64  Reserved : 59;
 386   UINT64  Info;
 387   UINT64  Req;
 388   UINT64  Resp;
 389   UINT64  Target;
 390   UINT64  Ip;
 391 } MOD_ERROR_INFO;
 392
 393 typedef struct {
 394   UINT8 CpuidInfo[40];
 395   UINT8 Reserved;
 396 } CPUID_INFO;
 397
 398 typedef struct {
 399   UINT64  FrLow;
 400   UINT64  FrHigh;
 401 } FR_STRUCT;
 402
 403 #define MIN_STATE_VALID_BIT_MASK  0x1
 404 #define BR_VALID_BIT_MASK         0x2
 405 #define CR_VALID_BIT_MASK         0x4
 406 #define AR_VALID_BIT_MASK         0x8
 407 #define RR_VALID_BIT_MASK         0x10
 408 #define FR_VALID_BIT_MASK         0x20
 409
 410 typedef struct {
 411   UINT64    ValidFieldBits;
 412   UINT8     MinStateInfo[1024];
 413   UINT64    Br[8];
 414   UINT64    Cr[128];
 415   UINT64    Ar[128];
 416   UINT64    Rr[8];
 417   FR_STRUCT Fr[128];
 418 } PSI_STATIC_STRUCT;
 419
 420 #define PROC_ERROR_MAP_VALID_BIT_MASK       0x1
 421 #define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
 422 #define PROC_CR_LID_VALID_BIT_MASK          0x4
 423 #define PROC_STATIC_STRUCT_VALID_BIT_MASK   0x8
 424 #define CPU_INFO_VALID_BIT_MASK             0x1000000
 425
 426 typedef struct {
 427   SAL_SEC_HEADER    SectionHeader;
 428   UINT64            ValidationBits;
 429   UINT64            ProcErrorMap;
 430   UINT64            ProcStateParameter;
 431   UINT64            ProcCrLid;
 432   MOD_ERROR_INFO    CacheError[15];
 433   MOD_ERROR_INFO    TlbError[15];
 434   MOD_ERROR_INFO    BusError[15];
 435   MOD_ERROR_INFO    RegFileCheck[15];
 436   MOD_ERROR_INFO    MsCheck[15];
 437   CPUID_INFO        CpuInfo;
 438   PSI_STATIC_STRUCT PsiValidData;
 439 } SAL_PROCESSOR_ERROR_RECORD;
 440
 441 //
 442 //  Sal Platform memory Error Record
 443 //
 444 #define SAL_MEMORY_ERROR_RECORD_INFO \
 445   { \
 446     0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 447   }
 448
 449 #define MEMORY_ERROR_STATUS_VALID_BIT_MASK                0x1
 450 #define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK            0x2
 451 #define MEMORY_ADDR_BIT_MASK                              0x4
 452 #define MEMORY_NODE_VALID_BIT_MASK                        0x8
 453 #define MEMORY_CARD_VALID_BIT_MASK                        0x10
 454 #define MEMORY_MODULE_VALID_BIT_MASK                      0x20
 455 #define MEMORY_BANK_VALID_BIT_MASK                        0x40
 456 #define MEMORY_DEVICE_VALID_BIT_MASK                      0x80
 457 #define MEMORY_ROW_VALID_BIT_MASK                         0x100
 458 #define MEMORY_COLUMN_VALID_BIT_MASK                      0x200
 459 #define MEMORY_BIT_POSITION_VALID_BIT_MASK                0x400
 460 #define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK       0x800
 461 #define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK       0x1000
 462 #define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK             0x2000
 463 #define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK  0x4000
 464 #define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK             0x8000
 465 #define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK    0x10000
 466
 467 typedef struct {
 468   SAL_SEC_HEADER  SectionHeader;
 469   UINT64          ValidationBits;
 470   UINT64          MemErrorStatus;
 471   UINT64          MemPhysicalAddress;
 472   UINT64          MemPhysicalAddressMask;
 473   UINT16          MemNode;
 474   UINT16          MemCard;
 475   UINT16          MemModule;
 476   UINT16          MemBank;
 477   UINT16          MemDevice;
 478   UINT16          MemRow;
 479   UINT16          MemColumn;
 480   UINT16          MemBitPosition;
 481   UINT64          ModRequestorId;
 482   UINT64          ModResponderId;
 483   UINT64          ModTargetId;
 484   UINT64          BusSpecificData;
 485   UINT8           MemPlatformOemId[16];
 486 } SAL_MEMORY_ERROR_RECORD;
 487
 488 //
 489 //  PCI BUS Errors
 490 //
 491 #define SAL_PCI_BUS_ERROR_RECORD_INFO \
 492   { \
 493     0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 494   }
 495
 496 #define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK     0x1
 497 #define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK       0x2
 498 #define PCI_BUS_ID_VALID_BIT_MASK               0x4
 499 #define PCI_BUS_ADDRESS_VALID_BIT_MASK          0x8
 500 #define PCI_BUS_DATA_VALID_BIT_MASK             0x10
 501 #define PCI_BUS_CMD_VALID_BIT_MASK              0x20
 502 #define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK     0x40
 503 #define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK     0x80
 504 #define PCI_BUS_TARGET_VALID_BIT_MASK           0x100
 505 #define PCI_BUS_OEM_ID_VALID_BIT_MASK           0x200
 506 #define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK  0x400
 507
 508 typedef struct {
 509   UINT8 BusNumber;
 510   UINT8 SegmentNumber;
 511 } PCI_BUS_ID;
 512
 513 typedef struct {
 514   SAL_SEC_HEADER  SectionHeader;
 515   UINT64          ValidationBits;
 516   UINT64          PciBusErrorStatus;
 517   UINT16          PciBusErrorType;
 518   PCI_BUS_ID      PciBusId;
 519   UINT32          Reserved;
 520   UINT64          PciBusAddress;
 521   UINT64          PciBusData;
 522   UINT64          PciBusCommand;
 523   UINT64          PciBusRequestorId;
 524   UINT64          PciBusResponderId;
 525   UINT64          PciBusTargetId;
 526   UINT8           PciBusOemId[16];
 527 } SAL_PCI_BUS_ERROR_RECORD;
 528
 529 //
 530 //  PCI Component Errors
 531 //
 532 #define SAL_PCI_COMP_ERROR_RECORD_INFO \
 533   { \
 534     0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 535   }
 536
 537 #define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK    0x1
 538 #define PCI_COMP_INFO_VALID_BIT_MASK            0x2
 539 #define PCI_COMP_MEM_NUM_VALID_BIT_MASK         0x4
 540 #define PCI_COMP_IO_NUM_VALID_BIT_MASK          0x8
 541 #define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK   0x10
 542 #define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
 543
 544 typedef struct {
 545   UINT16  VendorId;
 546   UINT16  DeviceId;
 547   UINT8   ClassCode[3];
 548   UINT8   FunctionNumber;
 549   UINT8   DeviceNumber;
 550   UINT8   BusNumber;
 551   UINT8   SegmentNumber;
 552   UINT8   Reserved[5];
 553 } PCI_COMP_INFO;
 554
 555 typedef struct {
 556   SAL_SEC_HEADER  SectionHeader;
 557   UINT64          ValidationBits;
 558   UINT64          PciComponentErrorStatus;
 559   PCI_COMP_INFO   PciComponentInfo;
 560   UINT32          PciComponentMemNum;
 561   UINT32          PciComponentIoNum;
 562   UINT8           PciBusOemId[16];
 563 } SAL_PCI_COMPONENT_ERROR_RECORD;
 564
 565 //
 566 //  Sal Device Errors Info.
 567 //
 568 #define SAL_DEVICE_ERROR_RECORD_INFO \
 569   { \
 570     0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 571   }
 572
 573 #define SEL_RECORD_ID_VALID_BIT_MASK      0x1;
 574 #define SEL_RECORD_TYPE_VALID_BIT_MASK    0x2;
 575 #define SEL_GENERATOR_ID_VALID_BIT_MASK   0x4;
 576 #define SEL_EVM_REV_VALID_BIT_MASK        0x8;
 577 #define SEL_SENSOR_TYPE_VALID_BIT_MASK    0x10;
 578 #define SEL_SENSOR_NUM_VALID_BIT_MASK     0x20;
 579 #define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
 580 #define SEL_EVENT_DATA1_VALID_BIT_MASK    0x80;
 581 #define SEL_EVENT_DATA2_VALID_BIT_MASK    0x100;
 582 #define SEL_EVENT_DATA3_VALID_BIT_MASK    0x200;
 583
 584 typedef struct {
 585   SAL_SEC_HEADER  SectionHeader;
 586   UINT64          ValidationBits;
 587   UINT16          SelRecordId;
 588   UINT8           SelRecordType;
 589   UINT32          TimeStamp;
 590   UINT16          GeneratorId;
 591   UINT8           EvmRevision;
 592   UINT8           SensorType;
 593   UINT8           SensorNum;
 594   UINT8           EventDirType;
 595   UINT8           Data1;
 596   UINT8           Data2;
 597   UINT8           Data3;
 598 } SAL_DEVICE_ERROR_RECORD;
 599
 600 //
 601 //  Sal SMBIOS Device Errors Info.
 602 //
 603 #define SAL_SMBIOS_ERROR_RECORD_INFO \
 604   { \
 605     0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 606   }
 607
 608 #define SMBIOS_EVENT_TYPE_VALID_BIT_MASK  0x1
 609 #define SMBIOS_LENGTH_VALID_BIT_MASK      0x2
 610 #define SMBIOS_TIME_STAMP_VALID_BIT_MASK  0x4
 611 #define SMBIOS_DATA_VALID_BIT_MASK        0x8
 612
 613 typedef struct {
 614   SAL_SEC_HEADER  SectionHeader;
 615   UINT64          ValidationBits;
 616   UINT8           SmbiosEventType;
 617   UINT8           SmbiosLength;
 618   UINT8           SmbiosBcdTimeStamp[6];
 619 } SAL_SMBIOS_DEVICE_ERROR_RECORD;
 620
 621 ///
 622 ///  Sal Platform Specific Errors Info.
 623 ///
 624 #define SAL_PLATFORM_ERROR_RECORD_INFO \
 625   { \
 626     0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 627   }
 628
 629 #define PLATFORM_ERROR_STATUS_VALID_BIT_MASK    0x1
 630 #define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK    0x2
 631 #define PLATFORM_RESPONDER_ID_VALID_BIT_MASK    0x4
 632 #define PLATFORM_TARGET_VALID_BIT_MASK          0x8
 633 #define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK   0x10
 634 #define PLATFORM_OEM_ID_VALID_BIT_MASK          0x20
 635 #define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
 636 #define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
 637
 638 typedef struct {
 639   SAL_SEC_HEADER  SectionHeader;
 640   UINT64          ValidationBits;
 641   UINT64          PlatformErrorStatus;
 642   UINT64          PlatformRequestorId;
 643   UINT64          PlatformResponderId;
 644   UINT64          PlatformTargetId;
 645   UINT64          PlatformBusSpecificData;
 646   UINT8           OemComponentId[16];
 647 } SAL_PLATFORM_SPECIFIC_ERROR_RECORD;
 648
 649 ///
 650 /// Union of all the possible Sal Record Types
 651 ///
 652 typedef union {
 653   SAL_RECORD_HEADER                   *RecordHeader;
 654   SAL_PROCESSOR_ERROR_RECORD          *SalProcessorRecord;
 655   SAL_PCI_BUS_ERROR_RECORD            *SalPciBusRecord;
 656   SAL_PCI_COMPONENT_ERROR_RECORD      *SalPciComponentRecord;
 657   SAL_DEVICE_ERROR_RECORD             *ImpiRecord;
 658   SAL_SMBIOS_DEVICE_ERROR_RECORD      *SmbiosRecord;
 659   SAL_PLATFORM_SPECIFIC_ERROR_RECORD  *PlatformRecord;
 660   SAL_MEMORY_ERROR_RECORD             *MemoryRecord;
 661   UINT8                               *Raw;
 662 } SAL_ERROR_RECORDS_POINTERS;
 663
 664 #pragma pack()
 665
 666 #endif