MdePkg/Include/IndustryStandard/Sal.h

   1 /** @file
   2   Main SAL API's defined in SAL 3.0 specification.
   3
   4   Copyright (c) 2006, Intel Corporation
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __SAL_API_H__
  16 #define __SAL_API_H__
  17
  18 //
  19 // FIT Types
  20 // Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003
  21 //
  22 #define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00
  23 #define EFI_SAL_FIT_PAL_B_TYPE      0x01
  24 //
  25 // type from 0x02 to 0x0E is reserved.
  26 //
  27 #define EFI_SAL_FIT_PAL_A_TYPE  0x0F
  28 //
  29 // OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10
  30 //
  31 #define EFI_SAL_FIT_PEI_CORE_TYPE 0x10
  32 #define EFI_SAL_FIT_UNUSED_TYPE   0x7F
  33
  34 //
  35 // EFI_SAL_STATUS
  36 //
  37 typedef UINTN EFI_SAL_STATUS;
  38
  39 #define EFI_SAL_SUCCESS               ((EFI_SAL_STATUS) 0)
  40 #define EFI_SAL_MORE_RECORDS          ((EFI_SAL_STATUS) 3)
  41 #define EFI_SAL_NOT_IMPLEMENTED       ((EFI_SAL_STATUS) - 1)
  42 #define EFI_SAL_INVALID_ARGUMENT      ((EFI_SAL_STATUS) - 2)
  43 #define EFI_SAL_ERROR                 ((EFI_SAL_STATUS) - 3)
  44 #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
  45 #define EFI_SAL_NO_INFORMATION        ((EFI_SAL_STATUS) - 5)
  46 #define EFI_SAL_NOT_ENOUGH_SCRATCH    ((EFI_SAL_STATUS) - 9)
  47
  48 //
  49 //  Return values from SAL
  50 //
  51 typedef struct {
  52   EFI_SAL_STATUS  Status; // register r8
  53   UINTN           r9;
  54   UINTN           r10;
  55   UINTN           r11;
  56 } SAL_RETURN_REGS;
  57
  58 //
  59 //  Delivery Mode of IPF CPU.
  60 //
  61 typedef enum {
  62   EFI_DELIVERY_MODE_INT,
  63   EFI_DELIVERY_MODE_MPreserved1,
  64   EFI_DELIVERY_MODE_PMI,
  65   EFI_DELIVERY_MODE_MPreserved2,
  66   EFI_DELIVERY_MODE_NMI,
  67   EFI_DELIVERY_MODE_INIT,
  68   EFI_DELIVERY_MODE_MPreserved3,
  69   EFI_DELIVERY_MODE_ExtINT
  70 } EFI_DELIVERY_MODE;
  71
  72 typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)
  73   (
  74     IN UINT64 FunctionId,
  75     IN UINT64 Arg2,
  76     IN UINT64 Arg3,
  77     IN UINT64 Arg4,
  78     IN UINT64 Arg5,
  79     IN UINT64 Arg6,
  80     IN UINT64 Arg7,
  81     IN UINT64 Arg8
  82   );
  83
  84 //
  85 // SAL Procedure FunctionId definition
  86 //
  87 #define EFI_SAL_SET_VECTORS             0x01000000
  88 #define EFI_SAL_GET_STATE_INFO          0x01000001
  89 #define EFI_SAL_GET_STATE_INFO_SIZE     0x01000002
  90 #define EFI_SAL_CLEAR_STATE_INFO        0x01000003
  91 #define EFI_SAL_MC_RENDEZ               0x01000004
  92 #define EFI_SAL_MC_SET_PARAMS           0x01000005
  93 #define EFI_SAL_REGISTER_PHYSICAL_ADDR  0x01000006
  94 #define EFI_SAL_CACHE_FLUSH             0x01000008
  95 #define EFI_SAL_CACHE_INIT              0x01000009
  96 #define EFI_SAL_PCI_CONFIG_READ         0x01000010
  97 #define EFI_SAL_PCI_CONFIG_WRITE        0x01000011
  98 #define EFI_SAL_FREQ_BASE               0x01000012
  99 #define EFI_SAL_PHYSICAL_ID_INFO        0x01000013
 100 #define EFI_SAL_UPDATE_PAL              0x01000020
 101
 102 #define EFI_SAL_FUNCTION_ID_MASK        0x0000ffff
 103 #define EFI_SAL_MAX_SAL_FUNCTION_ID     0x00000021
 104
 105 //
 106 // SAL Procedure parameter definitions
 107 // Not much point in using typedefs or enums because all params
 108 // are UINT64 and the entry point is common
 109 //
 110 // EFI_SAL_SET_VECTORS
 111 //
 112 #define EFI_SAL_SET_MCA_VECTOR          0x0
 113 #define EFI_SAL_SET_INIT_VECTOR         0x1
 114 #define EFI_SAL_SET_BOOT_RENDEZ_VECTOR  0x2
 115
 116 typedef struct {
 117   UINT64  Length : 32;
 118   UINT64  ChecksumValid : 1;
 119   UINT64  Reserved1 : 7;
 120   UINT64  ByteChecksum : 8;
 121   UINT64  Reserved2 : 16;
 122 } SAL_SET_VECTORS_CS_N;
 123
 124 //
 125 // EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,
 126 // EFI_SAL_CLEAR_STATE_INFO
 127 //
 128 #define EFI_SAL_MCA_STATE_INFO  0x0
 129 #define EFI_SAL_INIT_STATE_INFO 0x1
 130 #define EFI_SAL_CMC_STATE_INFO  0x2
 131 #define EFI_SAL_CP_STATE_INFO   0x3
 132
 133 //
 134 // EFI_SAL_MC_SET_PARAMS
 135 //
 136 #define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
 137 #define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
 138 #define EFI_SAL_MC_SET_CPE_PARAM    0x3
 139
 140 #define EFI_SAL_MC_SET_INTR_PARAM   0x1
 141 #define EFI_SAL_MC_SET_MEM_PARAM    0x2
 142
 143 //
 144 // EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
 145 //
 146 #define EFI_SAL_REGISTER_PAL_ADDR 0x0
 147
 148 //
 149 // EFI_SAL_CACHE_FLUSH
 150 //
 151 #define EFI_SAL_FLUSH_I_CACHE       0x01
 152 #define EFI_SAL_FLUSH_D_CACHE       0x02
 153 #define EFI_SAL_FLUSH_BOTH_CACHE    0x03
 154 #define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
 155
 156 //
 157 // EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE
 158 //
 159 #define EFI_SAL_PCI_CONFIG_ONE_BYTE   0x1
 160 #define EFI_SAL_PCI_CONFIG_TWO_BYTES  0x2
 161 #define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
 162
 163 typedef struct {
 164   UINT64  Register : 8;
 165   UINT64  Function : 3;
 166   UINT64  Device : 5;
 167   UINT64  Bus : 8;
 168   UINT64  Segment : 8;
 169   UINT64  Reserved : 32;
 170 } SAL_PCI_ADDRESS;
 171
 172 //
 173 // EFI_SAL_FREQ_BASE
 174 //
 175 #define EFI_SAL_CPU_INPUT_FREQ_BASE     0x0
 176 #define EFI_SAL_PLATFORM_IT_FREQ_BASE   0x1
 177 #define EFI_SAL_PLATFORM_RTC_FREQ_BASE  0x2
 178
 179 //
 180 // EFI_SAL_UPDATE_PAL
 181 //
 182 #define EFI_SAL_UPDATE_BAD_PAL_VERSION  ((UINT64) -1)
 183 #define EFI_SAL_UPDATE_PAL_AUTH_FAIL    ((UINT64) -2)
 184 #define EFI_SAL_UPDATE_PAL_BAD_TYPE     ((UINT64) -3)
 185 #define EFI_SAL_UPDATE_PAL_READONLY     ((UINT64) -4)
 186 #define EFI_SAL_UPDATE_PAL_WRITE_FAIL   ((UINT64) -10)
 187 #define EFI_SAL_UPDATE_PAL_ERASE_FAIL   ((UINT64) -11)
 188 #define EFI_SAL_UPDATE_PAL_READ_FAIL    ((UINT64) -12)
 189 #define EFI_SAL_UPDATE_PAL_CANT_FIT     ((UINT64) -13)
 190
 191 typedef struct {
 192   UINT32  Size;
 193   UINT32  MmddyyyyDate;
 194   UINT16  Version;
 195   UINT8   Type;
 196   UINT8   Reserved[5];
 197   UINT64  FwVendorId;
 198 } SAL_UPDATE_PAL_DATA_BLOCK;
 199
 200 typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
 201   struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;
 202   struct SAL_UPDATE_PAL_DATA_BLOCK  *DataBlock;
 203   UINT8                             StoreChecksum;
 204   UINT8                             Reserved[15];
 205 } SAL_UPDATE_PAL_INFO_BLOCK;
 206
 207 //
 208 // SAL System Table Definitions
 209 //
 210 #pragma pack(1)
 211 typedef struct {
 212   UINT32  Signature;
 213   UINT32  Length;
 214   UINT16  SalRevision;
 215   UINT16  EntryCount;
 216   UINT8   CheckSum;
 217   UINT8   Reserved[7];
 218   UINT16  SalAVersion;
 219   UINT16  SalBVersion;
 220   UINT8   OemId[32];
 221   UINT8   ProductId[32];
 222   UINT8   Reserved2[8];
 223 } SAL_SYSTEM_TABLE_HEADER;
 224 #pragma pack()
 225
 226 #define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
 227 #define EFI_SAL_REVISION            0x0300
 228 //
 229 // SAL System Types
 230 //
 231 #define EFI_SAL_ST_ENTRY_POINT        0
 232 #define EFI_SAL_ST_MEMORY_DESCRIPTOR  1
 233 #define EFI_SAL_ST_PLATFORM_FEATURES  2
 234 #define EFI_SAL_ST_TR_USAGE           3
 235 #define EFI_SAL_ST_PTC                4
 236 #define EFI_SAL_ST_AP_WAKEUP          5
 237
 238 //
 239 // SAL System Type Sizes
 240 //
 241 #define EFI_SAL_ST_ENTRY_POINT_SIZE        48
 242 #define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE  32
 243 #define EFI_SAL_ST_PLATFORM_FEATURES_SIZE  16
 244 #define EFI_SAL_ST_TR_USAGE_SIZE           32
 245 #define EFI_SAL_ST_PTC_SIZE                16
 246 #define EFI_SAL_ST_AP_WAKEUP_SIZE          16
 247
 248 #pragma pack(1)
 249 typedef struct {
 250   UINT8   Type; //  Type == 0
 251   UINT8   Reserved[7];
 252   UINT64  PalProcEntry;
 253   UINT64  SalProcEntry;
 254   UINT64  SalGlobalDataPointer;
 255   UINT64  Reserved2[2];
 256 } SAL_ST_ENTRY_POINT_DESCRIPTOR;
 257
 258 #pragma pack(1)
 259 typedef struct {
 260   UINT8 Type;                     // Type == 2
 261   UINT8 PlatformFeatures;
 262   UINT8 Reserved[14];
 263 } SAL_ST_PLATFORM_FEATURES;
 264 #pragma pack()
 265
 266 #define SAL_PLAT_FEAT_BUS_LOCK      0x01
 267 #define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
 268 #define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
 269
 270 #pragma pack(1)
 271 typedef struct {
 272   UINT8   Type;                   // Type == 3
 273   UINT8   TRType;
 274   UINT8   TRNumber;
 275   UINT8   Reserved[5];
 276   UINT64  VirtualAddress;
 277   UINT64  EncodedPageSize;
 278   UINT64  Reserved1;
 279 } SAL_ST_TR_DECRIPTOR;
 280 #pragma pack()
 281
 282 #define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
 283 #define EFI_SAL_ST_TR_USAGE_DATA        01
 284
 285 #pragma pack(1)
 286 typedef struct {
 287   UINT64  NumberOfProcessors;
 288   UINT64  LocalIDRegister;
 289 } SAL_COHERENCE_DOMAIN_INFO;
 290 #pragma pack()
 291
 292 #pragma pack(1)
 293 typedef struct {
 294   UINT8                     Type; // Type == 4
 295   UINT8                     Reserved[3];
 296   UINT32                    NumberOfDomains;
 297   SAL_COHERENCE_DOMAIN_INFO *DomainInformation;
 298 } SAL_ST_CACHE_COHERENCE_DECRIPTOR;
 299 #pragma pack()
 300
 301 #pragma pack(1)
 302 typedef struct {
 303   UINT8   Type;                   // Type == 5
 304   UINT8   WakeUpType;
 305   UINT8   Reserved[6];
 306   UINT64  ExternalInterruptVector;
 307 } SAL_ST_AP_WAKEUP_DECRIPTOR;
 308 #pragma pack()
 309 //
 310 // FIT Entry
 311 //
 312 #define EFI_SAL_FIT_ENTRY_PTR   (0x100000000 - 32)  // 4GB - 24
 313 #define EFI_SAL_FIT_PALA_ENTRY  (0x100000000 - 48)  // 4GB - 32
 314 #define EFI_SAL_FIT_PALB_TYPE   01
 315
 316 typedef struct {
 317   UINT64  Address;
 318   UINT8   Size[3];
 319   UINT8   Reserved;
 320   UINT16  Revision;
 321   UINT8   Type : 7;
 322   UINT8   CheckSumValid : 1;
 323   UINT8   CheckSum;
 324 } EFI_SAL_FIT_ENTRY;
 325
 326 //
 327 //  SAL Common Record Header
 328 //
 329 typedef struct {
 330   UINT16  Length;
 331   UINT8   Data[1024];
 332 } SAL_OEM_DATA;
 333
 334 typedef struct {
 335   UINT8 Seconds;
 336   UINT8 Minutes;
 337   UINT8 Hours;
 338   UINT8 Reserved;
 339   UINT8 Day;
 340   UINT8 Month;
 341   UINT8 Year;
 342   UINT8 Century;
 343 } SAL_TIME_STAMP;
 344
 345 typedef struct {
 346   UINT64          RecordId;
 347   UINT16          Revision;
 348   UINT8           ErrorSeverity;
 349   UINT8           ValidationBits;
 350   UINT32          RecordLength;
 351   SAL_TIME_STAMP  TimeStamp;
 352   UINT8           OemPlatformId[16];
 353 } SAL_RECORD_HEADER;
 354
 355 typedef struct {
 356   GUID                  Guid;
 357   UINT16    Revision;
 358   UINT8     ErrorRecoveryInfo;
 359   UINT8     Reserved;
 360   UINT32    SectionLength;
 361 } SAL_SEC_HEADER;
 362
 363 //
 364 // SAL Processor Record
 365 //
 366 #define SAL_PROCESSOR_ERROR_RECORD_INFO \
 367   { \
 368     0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 369   }
 370
 371 #define CHECK_INFO_VALID_BIT_MASK   0x1
 372 #define REQUESTOR_ID_VALID_BIT_MASK 0x2
 373 #define RESPONDER_ID_VALID_BIT_MASK 0x4
 374 #define TARGER_ID_VALID_BIT_MASK    0x8
 375 #define PRECISE_IP_VALID_BIT_MASK   0x10
 376
 377 typedef struct {
 378   UINT64  InfoValid : 1;
 379   UINT64  ReqValid : 1;
 380   UINT64  RespValid : 1;
 381   UINT64  TargetValid : 1;
 382   UINT64  IpValid : 1;
 383   UINT64  Reserved : 59;
 384   UINT64  Info;
 385   UINT64  Req;
 386   UINT64  Resp;
 387   UINT64  Target;
 388   UINT64  Ip;
 389 } MOD_ERROR_INFO;
 390
 391 typedef struct {
 392   UINT8 CpuidInfo[40];
 393   UINT8 Reserved;
 394 } CPUID_INFO;
 395
 396 typedef struct {
 397   UINT64  FrLow;
 398   UINT64  FrHigh;
 399 } FR_STRUCT;
 400
 401 #define MIN_STATE_VALID_BIT_MASK  0x1
 402 #define BR_VALID_BIT_MASK         0x2
 403 #define CR_VALID_BIT_MASK         0x4
 404 #define AR_VALID_BIT_MASK         0x8
 405 #define RR_VALID_BIT_MASK         0x10
 406 #define FR_VALID_BIT_MASK         0x20
 407
 408 typedef struct {
 409   UINT64    ValidFieldBits;
 410   UINT8     MinStateInfo[1024];
 411   UINT64    Br[8];
 412   UINT64    Cr[128];
 413   UINT64    Ar[128];
 414   UINT64    Rr[8];
 415   FR_STRUCT Fr[128];
 416 } PSI_STATIC_STRUCT;
 417
 418 #define PROC_ERROR_MAP_VALID_BIT_MASK       0x1
 419 #define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
 420 #define PROC_CR_LID_VALID_BIT_MASK          0x4
 421 #define PROC_STATIC_STRUCT_VALID_BIT_MASK   0x8
 422 #define CPU_INFO_VALID_BIT_MASK             0x1000000
 423
 424 typedef struct {
 425   SAL_SEC_HEADER    SectionHeader;
 426   UINT64            ValidationBits;
 427   UINT64            ProcErrorMap;
 428   UINT64            ProcStateParameter;
 429   UINT64            ProcCrLid;
 430   MOD_ERROR_INFO    CacheError[15];
 431   MOD_ERROR_INFO    TlbError[15];
 432   MOD_ERROR_INFO    BusError[15];
 433   MOD_ERROR_INFO    RegFileCheck[15];
 434   MOD_ERROR_INFO    MsCheck[15];
 435   CPUID_INFO        CpuInfo;
 436   PSI_STATIC_STRUCT PsiValidData;
 437 } SAL_PROCESSOR_ERROR_RECORD;
 438
 439 //
 440 //  Sal Platform memory Error Record
 441 //
 442 #define SAL_MEMORY_ERROR_RECORD_INFO \
 443   { \
 444     0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 445   }
 446
 447 #define MEMORY_ERROR_STATUS_VALID_BIT_MASK                0x1
 448 #define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK            0x2
 449 #define MEMORY_ADDR_BIT_MASK                              0x4
 450 #define MEMORY_NODE_VALID_BIT_MASK                        0x8
 451 #define MEMORY_CARD_VALID_BIT_MASK                        0x10
 452 #define MEMORY_MODULE_VALID_BIT_MASK                      0x20
 453 #define MEMORY_BANK_VALID_BIT_MASK                        0x40
 454 #define MEMORY_DEVICE_VALID_BIT_MASK                      0x80
 455 #define MEMORY_ROW_VALID_BIT_MASK                         0x100
 456 #define MEMORY_COLUMN_VALID_BIT_MASK                      0x200
 457 #define MEMORY_BIT_POSITION_VALID_BIT_MASK                0x400
 458 #define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK       0x800
 459 #define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK       0x1000
 460 #define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK             0x2000
 461 #define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK  0x4000
 462 #define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK             0x8000
 463 #define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK    0x10000
 464
 465 typedef struct {
 466   SAL_SEC_HEADER  SectionHeader;
 467   UINT64          ValidationBits;
 468   UINT64          MemErrorStatus;
 469   UINT64          MemPhysicalAddress;
 470   UINT64          MemPhysicalAddressMask;
 471   UINT16          MemNode;
 472   UINT16          MemCard;
 473   UINT16          MemModule;
 474   UINT16          MemBank;
 475   UINT16          MemDevice;
 476   UINT16          MemRow;
 477   UINT16          MemColumn;
 478   UINT16          MemBitPosition;
 479   UINT64          ModRequestorId;
 480   UINT64          ModResponderId;
 481   UINT64          ModTargetId;
 482   UINT64          BusSpecificData;
 483   UINT8           MemPlatformOemId[16];
 484 } SAL_MEMORY_ERROR_RECORD;
 485
 486 //
 487 //  PCI BUS Errors
 488 //
 489 #define SAL_PCI_BUS_ERROR_RECORD_INFO \
 490   { \
 491     0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 492   }
 493
 494 #define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK     0x1
 495 #define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK       0x2
 496 #define PCI_BUS_ID_VALID_BIT_MASK               0x4
 497 #define PCI_BUS_ADDRESS_VALID_BIT_MASK          0x8
 498 #define PCI_BUS_DATA_VALID_BIT_MASK             0x10
 499 #define PCI_BUS_CMD_VALID_BIT_MASK              0x20
 500 #define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK     0x40
 501 #define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK     0x80
 502 #define PCI_BUS_TARGET_VALID_BIT_MASK           0x100
 503 #define PCI_BUS_OEM_ID_VALID_BIT_MASK           0x200
 504 #define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK  0x400
 505
 506 typedef struct {
 507   UINT8 BusNumber;
 508   UINT8 SegmentNumber;
 509 } PCI_BUS_ID;
 510
 511 typedef struct {
 512   SAL_SEC_HEADER  SectionHeader;
 513   UINT64          ValidationBits;
 514   UINT64          PciBusErrorStatus;
 515   UINT16          PciBusErrorType;
 516   PCI_BUS_ID      PciBusId;
 517   UINT32          Reserved;
 518   UINT64          PciBusAddress;
 519   UINT64          PciBusData;
 520   UINT64          PciBusCommand;
 521   UINT64          PciBusRequestorId;
 522   UINT64          PciBusResponderId;
 523   UINT64          PciBusTargetId;
 524   UINT8           PciBusOemId[16];
 525 } SAL_PCI_BUS_ERROR_RECORD;
 526
 527 //
 528 //  PCI Component Errors
 529 //
 530 #define SAL_PCI_COMP_ERROR_RECORD_INFO \
 531   { \
 532     0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 533   }
 534
 535 #define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK    0x1
 536 #define PCI_COMP_INFO_VALID_BIT_MASK            0x2
 537 #define PCI_COMP_MEM_NUM_VALID_BIT_MASK         0x4
 538 #define PCI_COMP_IO_NUM_VALID_BIT_MASK          0x8
 539 #define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK   0x10
 540 #define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
 541
 542 typedef struct {
 543   UINT16  VendorId;
 544   UINT16  DeviceId;
 545   UINT8   ClassCode[3];
 546   UINT8   FunctionNumber;
 547   UINT8   DeviceNumber;
 548   UINT8   BusNumber;
 549   UINT8   SegmentNumber;
 550   UINT8   Reserved[5];
 551 } PCI_COMP_INFO;
 552
 553 typedef struct {
 554   SAL_SEC_HEADER  SectionHeader;
 555   UINT64          ValidationBits;
 556   UINT64          PciComponentErrorStatus;
 557   PCI_COMP_INFO   PciComponentInfo;
 558   UINT32          PciComponentMemNum;
 559   UINT32          PciComponentIoNum;
 560   UINT8           PciBusOemId[16];
 561 } SAL_PCI_COMPONENT_ERROR_RECORD;
 562
 563 //
 564 //  Sal Device Errors Info.
 565 //
 566 #define SAL_DEVICE_ERROR_RECORD_INFO \
 567   { \
 568     0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 569   }
 570
 571 #define SEL_RECORD_ID_VALID_BIT_MASK      0x1;
 572 #define SEL_RECORD_TYPE_VALID_BIT_MASK    0x2;
 573 #define SEL_GENERATOR_ID_VALID_BIT_MASK   0x4;
 574 #define SEL_EVM_REV_VALID_BIT_MASK        0x8;
 575 #define SEL_SENSOR_TYPE_VALID_BIT_MASK    0x10;
 576 #define SEL_SENSOR_NUM_VALID_BIT_MASK     0x20;
 577 #define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
 578 #define SEL_EVENT_DATA1_VALID_BIT_MASK    0x80;
 579 #define SEL_EVENT_DATA2_VALID_BIT_MASK    0x100;
 580 #define SEL_EVENT_DATA3_VALID_BIT_MASK    0x200;
 581
 582 typedef struct {
 583   SAL_SEC_HEADER  SectionHeader;
 584   UINT64          ValidationBits;
 585   UINT16          SelRecordId;
 586   UINT8           SelRecordType;
 587   UINT32          TimeStamp;
 588   UINT16          GeneratorId;
 589   UINT8           EvmRevision;
 590   UINT8           SensorType;
 591   UINT8           SensorNum;
 592   UINT8           EventDirType;
 593   UINT8           Data1;
 594   UINT8           Data2;
 595   UINT8           Data3;
 596 } SAL_DEVICE_ERROR_RECORD;
 597
 598 //
 599 //  Sal SMBIOS Device Errors Info.
 600 //
 601 #define SAL_SMBIOS_ERROR_RECORD_INFO \
 602   { \
 603     0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 604   }
 605
 606 #define SMBIOS_EVENT_TYPE_VALID_BIT_MASK  0x1
 607 #define SMBIOS_LENGTH_VALID_BIT_MASK      0x2
 608 #define SMBIOS_TIME_STAMP_VALID_BIT_MASK  0x4
 609 #define SMBIOS_DATA_VALID_BIT_MASK        0x8
 610
 611 typedef struct {
 612   SAL_SEC_HEADER  SectionHeader;
 613   UINT64          ValidationBits;
 614   UINT8           SmbiosEventType;
 615   UINT8           SmbiosLength;
 616   UINT8           SmbiosBcdTimeStamp[6];
 617 } SAL_SMBIOS_DEVICE_ERROR_RECORD;
 618
 619 //
 620 //  Sal Platform Specific Errors Info.
 621 //
 622 #define SAL_PLATFORM_ERROR_RECORD_INFO \
 623   { \
 624     0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
 625   }
 626
 627 #define PLATFORM_ERROR_STATUS_VALID_BIT_MASK    0x1
 628 #define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK    0x2
 629 #define PLATFORM_RESPONDER_ID_VALID_BIT_MASK    0x4
 630 #define PLATFORM_TARGET_VALID_BIT_MASK          0x8
 631 #define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK   0x10
 632 #define PLATFORM_OEM_ID_VALID_BIT_MASK          0x20
 633 #define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
 634 #define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
 635
 636 typedef struct {
 637   SAL_SEC_HEADER  SectionHeader;
 638   UINT64          ValidationBits;
 639   UINT64          PlatformErrorStatus;
 640   UINT64          PlatformRequestorId;
 641   UINT64          PlatformResponderId;
 642   UINT64          PlatformTargetId;
 643   UINT64          PlatformBusSpecificData;
 644   UINT8           OemComponentId[16];
 645 } SAL_PLATFORM_SPECIFIC_ERROR_RECORD;
 646
 647 //
 648 // Union of all the possible Sal Record Types
 649 //
 650 typedef union {
 651   SAL_RECORD_HEADER                   *RecordHeader;
 652   SAL_PROCESSOR_ERROR_RECORD          *SalProcessorRecord;
 653   SAL_PCI_BUS_ERROR_RECORD            *SalPciBusRecord;
 654   SAL_PCI_COMPONENT_ERROR_RECORD      *SalPciComponentRecord;
 655   SAL_DEVICE_ERROR_RECORD             *ImpiRecord;
 656   SAL_SMBIOS_DEVICE_ERROR_RECORD      *SmbiosRecord;
 657   SAL_PLATFORM_SPECIFIC_ERROR_RECORD  *PlatformRecord;
 658   SAL_MEMORY_ERROR_RECORD             *MemoryRecord;
 659   UINT8                               *Raw;
 660 } SAL_ERROR_RECORDS_POINTERS;
 661
 662 #pragma pack()
 663
 664 #endif