MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h

   1 /** @file
   2   This file contains definitions for SPD LPDDR.
   3
   4   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7   @par Revision Reference:
   8     - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2
   9       http://www.jedec.org/standards-documents/docs/spd412m-2
  10 **/
  11
  12 #ifndef _SDRAM_SPD_LPDDR_H_
  13 #define _SDRAM_SPD_LPDDR_H_
  14
  15 #pragma pack (push, 1)
  16
  17 typedef union {
  18   struct {
  19     UINT8  BytesUsed                           :  4; ///< Bits 3:0
  20     UINT8  BytesTotal                          :  3; ///< Bits 6:4
  21     UINT8  CrcCoverage                         :  1; ///< Bits 7:7
  22   } Bits;
  23   UINT8  Data;
  24 } SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT;
  25
  26 typedef union {
  27   struct {
  28     UINT8  Minor                               :  4; ///< Bits 3:0
  29     UINT8  Major                               :  4; ///< Bits 7:4
  30   } Bits;
  31   UINT8  Data;
  32 } SPD_LPDDR_REVISION_STRUCT;
  33
  34 typedef union {
  35   struct {
  36     UINT8  Type                                :  8; ///< Bits 7:0
  37   } Bits;
  38   UINT8  Data;
  39 } SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT;
  40
  41 typedef union {
  42   struct {
  43     UINT8  ModuleType                          :  4; ///< Bits 3:0
  44     UINT8  HybridMedia                         :  3; ///< Bits 6:4
  45     UINT8  Hybrid                              :  1; ///< Bits 7:7
  46   } Bits;
  47   UINT8  Data;
  48 } SPD_LPDDR_MODULE_TYPE_STRUCT;
  49
  50 typedef union {
  51   struct {
  52     UINT8  Density                             :  4; ///< Bits 3:0
  53     UINT8  BankAddress                         :  2; ///< Bits 5:4
  54     UINT8  BankGroup                           :  2; ///< Bits 7:6
  55   } Bits;
  56   UINT8  Data;
  57 } SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT;
  58
  59 typedef union {
  60   struct {
  61     UINT8  ColumnAddress                       :  3; ///< Bits 2:0
  62     UINT8  RowAddress                          :  3; ///< Bits 5:3
  63     UINT8  Reserved                            :  2; ///< Bits 7:6
  64   } Bits;
  65   UINT8  Data;
  66 } SPD_LPDDR_SDRAM_ADDRESSING_STRUCT;
  67
  68 typedef union {
  69   struct {
  70     UINT8  SignalLoading                       :  2; ///< Bits 1:0
  71     UINT8  ChannelsPerDie                      :  2; ///< Bits 3:2
  72     UINT8  DieCount                            :  3; ///< Bits 6:4
  73     UINT8  SdramPackageType                    :  1; ///< Bits 7:7
  74   } Bits;
  75   UINT8  Data;
  76 } SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT;
  77
  78 typedef union {
  79   struct {
  80     UINT8  MaximumActivateCount                :  4; ///< Bits 3:0
  81     UINT8  MaximumActivateWindow               :  2; ///< Bits 5:4
  82     UINT8  Reserved                            :  2; ///< Bits 7:6
  83   } Bits;
  84   UINT8  Data;
  85 } SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT;
  86
  87 typedef union {
  88   struct {
  89     UINT8  Reserved                            :  8; ///< Bits 7:0
  90   } Bits;
  91   UINT8  Data;
  92 } SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT;
  93
  94 typedef union {
  95   struct {
  96     UINT8  Reserved                            :  5; ///< Bits 4:0
  97     UINT8  SoftPPR                             :  1; ///< Bits 5:5
  98     UINT8  PostPackageRepair                   :  2; ///< Bits 7:6
  99   } Bits;
 100   UINT8  Data;
 101 } SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;
 102
 103 typedef union {
 104   struct {
 105     UINT8  OperationAt1_20                     :  1; ///< Bits 0:0
 106     UINT8  EndurantAt1_20                      :  1; ///< Bits 1:1
 107     UINT8  OperationAt1_10                     :  1; ///< Bits 2:2
 108     UINT8  EndurantAt1_10                      :  1; ///< Bits 3:3
 109     UINT8  OperationAtTBD2V                    :  1; ///< Bits 4:4
 110     UINT8  EndurantAtTBD2V                     :  1; ///< Bits 5:5
 111     UINT8  Reserved                            :  2; ///< Bits 7:6
 112   } Bits;
 113   UINT8  Data;
 114 } SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT;
 115
 116 typedef union {
 117   struct {
 118     UINT8  SdramDeviceWidth                    :  3; ///< Bits 2:0
 119     UINT8  RankCount                           :  3; ///< Bits 5:3
 120     UINT8  Reserved                            :  2; ///< Bits 7:6
 121   } Bits;
 122   UINT8  Data;
 123 } SPD_LPDDR_MODULE_ORGANIZATION_STRUCT;
 124
 125 typedef union {
 126   struct {
 127     UINT8  PrimaryBusWidth                     :  3; ///< Bits 2:0
 128     UINT8  BusWidthExtension                   :  2; ///< Bits 4:3
 129     UINT8  NumberofChannels                    :  3; ///< Bits 7:5
 130   } Bits;
 131   UINT8  Data;
 132 } SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT;
 133
 134 typedef union {
 135   struct {
 136     UINT8  Reserved                            :  7; ///< Bits 6:0
 137     UINT8  ThermalSensorPresence               :  1; ///< Bits 7:7
 138   } Bits;
 139   UINT8  Data;
 140 } SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT;
 141
 142 typedef union {
 143   struct {
 144     UINT8  ExtendedBaseModuleType              :  4; ///< Bits 3:0
 145     UINT8  Reserved                            :  4; ///< Bits 7:4
 146   } Bits;
 147   UINT8  Data;
 148 } SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT;
 149
 150 typedef union {
 151   struct {
 152     UINT8  ChipSelectLoading                   :  3; ///< Bits 2:0
 153     UINT8  CommandAddressControlClockLoading   :  3; ///< Bits 5:3
 154     UINT8  DataStrobeMaskLoading               :  2; ///< Bits 7:6
 155   } Bits;
 156   UINT8  Data;
 157 } SPD_LPDDR_SIGNAL_LOADING_STRUCT;
 158
 159 typedef union {
 160   struct {
 161     UINT8  Fine                                :  2; ///< Bits 1:0
 162     UINT8  Medium                              :  2; ///< Bits 3:2
 163     UINT8  Reserved                            :  4; ///< Bits 7:4
 164   } Bits;
 165   UINT8  Data;
 166 } SPD_LPDDR_TIMEBASE_STRUCT;
 167
 168 typedef union {
 169   struct {
 170     UINT8  tCKmin                              :  8; ///< Bits 7:0
 171   } Bits;
 172   UINT8  Data;
 173 } SPD_LPDDR_TCK_MIN_MTB_STRUCT;
 174
 175 typedef union {
 176   struct {
 177     UINT8  tCKmax                              :  8; ///< Bits 7:0
 178   } Bits;
 179   UINT8  Data;
 180 } SPD_LPDDR_TCK_MAX_MTB_STRUCT;
 181
 182 typedef union {
 183   struct {
 184     UINT32 Cl3                                 :  1;  ///< Bits 0:0
 185     UINT32 Cl6                                 :  1;  ///< Bits 1:1
 186     UINT32 Cl8                                 :  1;  ///< Bits 2:2
 187     UINT32 Cl9                                 :  1;  ///< Bits 3:3
 188     UINT32 Cl10                                :  1;  ///< Bits 4:4
 189     UINT32 Cl11                                :  1;  ///< Bits 5:5
 190     UINT32 Cl12                                :  1;  ///< Bits 6:6
 191     UINT32 Cl14                                :  1;  ///< Bits 7:7
 192     UINT32 Cl16                                :  1;  ///< Bits 8:8
 193     UINT32 Reserved0                           :  1;  ///< Bits 9:9
 194     UINT32 Cl20                                :  1;  ///< Bits 10:10
 195     UINT32 Cl22                                :  1;  ///< Bits 11:11
 196     UINT32 Cl24                                :  1;  ///< Bits 12:12
 197     UINT32 Reserved1                           :  1;  ///< Bits 13:13
 198     UINT32 Cl28                                :  1;  ///< Bits 14:14
 199     UINT32 Reserved2                           :  1;  ///< Bits 15:15
 200     UINT32 Cl32                                :  1;  ///< Bits 16:16
 201     UINT32 Reserved3                           :  1;  ///< Bits 17:17
 202     UINT32 Cl36                                :  1;  ///< Bits 18:18
 203     UINT32 Reserved4                           :  1;  ///< Bits 19:19
 204     UINT32 Cl40                                :  1;  ///< Bits 20:20
 205     UINT32 Reserved5                           :  11; ///< Bits 31:21
 206   } Bits;
 207   UINT32 Data;
 208   UINT16 Data16[2];
 209   UINT8  Data8[4];
 210 } SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT;
 211
 212 typedef union {
 213   struct {
 214     UINT8  tAAmin                              :  8; ///< Bits 7:0
 215   } Bits;
 216   UINT8  Data;
 217 } SPD_LPDDR_TAA_MIN_MTB_STRUCT;
 218
 219 typedef union {
 220   struct {
 221     UINT8  ReadLatencyMode                     :  2; ///< Bits 1:0
 222     UINT8  WriteLatencySet                     :  2; ///< Bits 3:2
 223     UINT8  Reserved                            :  4; ///< Bits 7:4
 224   } Bits;
 225   UINT8  Data;
 226 } SPD_LPDDR_RW_LATENCY_OPTION_STRUCT;
 227
 228 typedef union {
 229   struct {
 230     UINT8  tRCDmin                             :  8; ///< Bits 7:0
 231   } Bits;
 232   UINT8  Data;
 233 } SPD_LPDDR_TRCD_MIN_MTB_STRUCT;
 234
 235 typedef union {
 236   struct {
 237     UINT8  tRPab                               :  8; ///< Bits 7:0
 238   } Bits;
 239   UINT8  Data;
 240 } SPD_LPDDR_TRP_AB_MTB_STRUCT;
 241
 242 typedef union {
 243   struct {
 244     UINT8  tRPpb                               :  8; ///< Bits 7:0
 245   } Bits;
 246   UINT8  Data;
 247 } SPD_LPDDR_TRP_PB_MTB_STRUCT;
 248
 249 typedef union {
 250   struct {
 251     UINT16  tRFCab                             :  16; ///< Bits 15:0
 252   } Bits;
 253   UINT16 Data;
 254   UINT8  Data8[2];
 255 } SPD_LPDDR_TRFC_AB_MTB_STRUCT;
 256
 257 typedef union {
 258 struct {
 259     UINT16  tRFCpb                             :  16; ///< Bits 15:0
 260   } Bits;
 261   UINT16 Data;
 262   UINT8  Data8[2];
 263 } SPD_LPDDR_TRFC_PB_MTB_STRUCT;
 264
 265 typedef union {
 266   struct {
 267     UINT8  BitOrderatSDRAM                     :  5; ///< Bits 4:0
 268     UINT8  WiredtoUpperLowerNibble             :  1; ///< Bits 5:5
 269     UINT8  PackageRankMap                      :  2; ///< Bits 7:6
 270   } Bits;
 271   UINT8  Data;
 272 } SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;
 273
 274 typedef union {
 275   struct {
 276     INT8  tRPpbFine                            :  8; ///< Bits 7:0
 277   } Bits;
 278   INT8  Data;
 279 } SPD_LPDDR_TRP_PB_FTB_STRUCT;
 280
 281 typedef union {
 282   struct {
 283     INT8  tRPabFine                            :  8; ///< Bits 7:0
 284   } Bits;
 285   INT8  Data;
 286 } SPD_LPDDR_TRP_AB_FTB_STRUCT;
 287
 288 typedef union {
 289   struct {
 290     INT8  tRCDminFine                          :  8; ///< Bits 7:0
 291   } Bits;
 292   INT8  Data;
 293 } SPD_LPDDR_TRCD_MIN_FTB_STRUCT;
 294
 295 typedef union {
 296   struct {
 297     INT8  tAAminFine                           :  8; ///< Bits 7:0
 298   } Bits;
 299   INT8  Data;
 300 } SPD_LPDDR_TAA_MIN_FTB_STRUCT;
 301
 302 typedef union {
 303   struct {
 304     INT8  tCKmaxFine                           :  8; ///< Bits 7:0
 305   } Bits;
 306   INT8  Data;
 307 } SPD_LPDDR_TCK_MAX_FTB_STRUCT;
 308
 309 typedef union {
 310   struct {
 311     INT8  tCKminFine                           :  8; ///< Bits 7:0
 312   } Bits;
 313   INT8  Data;
 314 } SPD_LPDDR_TCK_MIN_FTB_STRUCT;
 315
 316 typedef union {
 317   struct {
 318     UINT16 ContinuationCount                   :  7; ///< Bits 6:0
 319     UINT16 ContinuationParity                  :  1; ///< Bits 7:7
 320     UINT16 LastNonZeroByte                     :  8; ///< Bits 15:8
 321   } Bits;
 322   UINT16 Data;
 323   UINT8  Data8[2];
 324 } SPD_LPDDR_MANUFACTURER_ID_CODE;
 325
 326 typedef struct {
 327   UINT8 Location;                              ///< Module Manufacturing Location
 328 } SPD_LPDDR_MANUFACTURING_LOCATION;
 329
 330 typedef struct {
 331   UINT8  Year;                                 ///< Year represented in BCD (00h = 2000)
 332   UINT8  Week;                                 ///< Year represented in BCD (47h = week 47)
 333 } SPD_LPDDR_MANUFACTURING_DATE;
 334
 335 typedef union {
 336   UINT32 Data;
 337   UINT16 SerialNumber16[2];
 338   UINT8  SerialNumber8[4];
 339 } SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER;
 340
 341 typedef struct {
 342   SPD_LPDDR_MANUFACTURER_ID_CODE            IdCode;                   ///< Module Manufacturer ID Code
 343   SPD_LPDDR_MANUFACTURING_LOCATION          Location;                 ///< Module Manufacturing Location
 344   SPD_LPDDR_MANUFACTURING_DATE              Date;                     ///< Module Manufacturing Year, in BCD (range: 2000-2255)
 345   SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER      SerialNumber;             ///< Module Serial Number
 346 } SPD_LPDDR_UNIQUE_MODULE_ID;
 347
 348 typedef union {
 349   struct {
 350     UINT8  FrontThickness                      :  4; ///< Bits 3:0
 351     UINT8  BackThickness                       :  4; ///< Bits 7:4
 352   } Bits;
 353   UINT8 Data;
 354 } SPD_LPDDR_MODULE_MAXIMUM_THICKNESS;
 355
 356 typedef union {
 357   struct {
 358     UINT8  Height                              :  5; ///< Bits 4:0
 359     UINT8  RawCardExtension                    :  3; ///< Bits 7:5
 360   } Bits;
 361   UINT8  Data;
 362 } SPD_LPDDR_MODULE_NOMINAL_HEIGHT;
 363
 364 typedef union {
 365   struct {
 366     UINT8  Card                                :  5; ///< Bits 4:0
 367     UINT8  Revision                            :  2; ///< Bits 6:5
 368     UINT8  Extension                           :  1; ///< Bits 7:7
 369   } Bits;
 370   UINT8  Data;
 371 } SPD_LPDDR_REFERENCE_RAW_CARD;
 372
 373 typedef union {
 374   UINT16 Crc[1];
 375   UINT8  Data8[2];
 376 } SPD_LPDDR_CYCLIC_REDUNDANCY_CODE;
 377
 378 typedef struct {
 379   SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT            Description;              ///< 0       Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
 380   SPD_LPDDR_REVISION_STRUCT                      Revision;                 ///< 1       SPD Revision
 381   SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT              DramDeviceType;           ///< 2       DRAM Device Type
 382   SPD_LPDDR_MODULE_TYPE_STRUCT                   ModuleType;               ///< 3       Module Type
 383   SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT           SdramDensityAndBanks;     ///< 4       SDRAM Density and Banks
 384   SPD_LPDDR_SDRAM_ADDRESSING_STRUCT              SdramAddressing;          ///< 5       SDRAM Addressing
 385   SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT            SdramPackageType;         ///< 6       SDRAM Package Type
 386   SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT       SdramOptionalFeatures;    ///< 7       SDRAM Optional Features
 387   SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT         ThermalAndRefreshOptions; ///< 8       SDRAM Thermal and Refresh Options
 388   SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures;    ///< 9      Other SDRAM Optional Features
 389   UINT8                                          Reserved0;                ///< 10      Reserved
 390   SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT        ModuleNominalVoltage;     ///< 11      Module Nominal Voltage, VDD
 391   SPD_LPDDR_MODULE_ORGANIZATION_STRUCT           ModuleOrganization;       ///< 12      Module Organization
 392   SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT       ModuleMemoryBusWidth;     ///< 13      Module Memory Bus Width
 393   SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT         ModuleThermalSensor;      ///< 14      Module Thermal Sensor
 394   SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT          ExtendedModuleType;       ///< 15      Extended Module Type
 395   SPD_LPDDR_SIGNAL_LOADING_STRUCT                SignalLoading;            ///< 16      Signal Loading
 396   SPD_LPDDR_TIMEBASE_STRUCT                      Timebase;                 ///< 17      Timebases
 397   SPD_LPDDR_TCK_MIN_MTB_STRUCT                   tCKmin;                   ///< 18      SDRAM Minimum Cycle Time (tCKmin)
 398   SPD_LPDDR_TCK_MAX_MTB_STRUCT                   tCKmax;                   ///< 19      SDRAM Maximum Cycle Time (tCKmax)
 399   SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT       CasLatencies;             ///< 20-23   CAS Latencies Supported
 400   SPD_LPDDR_TAA_MIN_MTB_STRUCT                   tAAmin;                   ///< 24      Minimum CAS Latency Time (tAAmin)
 401   SPD_LPDDR_RW_LATENCY_OPTION_STRUCT             LatencySetOptions;        ///< 25      Read and Write Latency Set Options
 402   SPD_LPDDR_TRCD_MIN_MTB_STRUCT                  tRCDmin;                  ///< 26      Minimum RAS# to CAS# Delay Time (tRCDmin)
 403   SPD_LPDDR_TRP_AB_MTB_STRUCT                    tRPab;                    ///< 27      Minimum Row Precharge Delay Time (tRPab), all banks
 404   SPD_LPDDR_TRP_PB_MTB_STRUCT                    tRPpb;                    ///< 28      Minimum Row Precharge Delay Time (tRPpb), per bank
 405   SPD_LPDDR_TRFC_AB_MTB_STRUCT                   tRFCab;                   ///< 29-30   Minimum Refresh Recovery Delay Time (tRFCab), all banks
 406   SPD_LPDDR_TRFC_PB_MTB_STRUCT                   tRFCpb;                   ///< 31-32   Minimum Refresh Recovery Delay Time (tRFCpb), per bank
 407   UINT8                                          Reserved1[59 - 33 + 1];   ///< 33-59   Reserved
 408   SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT    BitMapping[77 - 60 + 1];  ///< 60-77   Connector to SDRAM Bit Mapping
 409   UINT8                                          Reserved2[119 - 78 + 1];  ///< 78-119  Reserved
 410   SPD_LPDDR_TRP_PB_FTB_STRUCT                    tRPpbFine;                ///< 120     Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank
 411   SPD_LPDDR_TRP_AB_FTB_STRUCT                    tRPabFine;                ///< 121     Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks
 412   SPD_LPDDR_TRCD_MIN_FTB_STRUCT                  tRCDminFine;              ///< 122     Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
 413   SPD_LPDDR_TAA_MIN_FTB_STRUCT                   tAAminFine;               ///< 123     Fine Offset for Minimum CAS Latency Time (tAAmin)
 414   SPD_LPDDR_TCK_MAX_FTB_STRUCT                   tCKmaxFine;               ///< 124     Fine Offset for SDRAM Maximum Cycle Time (tCKmax)
 415   SPD_LPDDR_TCK_MIN_FTB_STRUCT                   tCKminFine;               ///< 125     Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
 416   SPD_LPDDR_CYCLIC_REDUNDANCY_CODE               Crc;                      ///< 126-127 Cyclical Redundancy Code (CRC)
 417 } SPD_LPDDR_BASE_SECTION;
 418
 419 typedef struct {
 420   SPD_LPDDR_MODULE_NOMINAL_HEIGHT         ModuleNominalHeight;      ///< 128     Module Nominal Height
 421   SPD_LPDDR_MODULE_MAXIMUM_THICKNESS      ModuleMaximumThickness;   ///< 129     Module Maximum Thickness
 422   SPD_LPDDR_REFERENCE_RAW_CARD            ReferenceRawCardUsed;     ///< 130     Reference Raw Card Used
 423   UINT8                                   Reserved[253 - 131 + 1];  ///< 131-253 Reserved
 424   SPD_LPDDR_CYCLIC_REDUNDANCY_CODE        Crc;                      ///< 254-255 Cyclical Redundancy Code (CRC)
 425 } SPD_LPDDR_MODULE_LPDIMM;
 426
 427 typedef struct {
 428   SPD_LPDDR_MODULE_LPDIMM                 LpDimm;                   ///< 128-255 Unbuffered Memory Module Types
 429 } SPD_LPDDR_MODULE_SPECIFIC;
 430
 431 typedef struct {
 432   UINT8                                   ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number
 433 } SPD_LPDDR_MODULE_PART_NUMBER;
 434
 435 typedef struct {
 436   UINT8                                   ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
 437 } SPD_LPDDR_MANUFACTURER_SPECIFIC;
 438
 439 typedef UINT8                             SPD_LPDDR_MODULE_REVISION_CODE;///< 349     Module Revision Code
 440 typedef UINT8                             SPD_LPDDR_DRAM_STEPPING;       ///< 352     Dram Stepping
 441
 442 typedef struct {
 443   SPD_LPDDR_UNIQUE_MODULE_ID              ModuleId;                 ///< 320-328 Unique Module ID
 444   SPD_LPDDR_MODULE_PART_NUMBER            ModulePartNumber;         ///< 329-348 Module Part Number
 445   SPD_LPDDR_MODULE_REVISION_CODE          ModuleRevisionCode;       ///< 349     Module Revision Code
 446   SPD_LPDDR_MANUFACTURER_ID_CODE          DramIdCode;               ///< 350-351 Dram Manufacturer ID Code
 447   SPD_LPDDR_DRAM_STEPPING                 DramStepping;             ///< 352     Dram Stepping
 448   SPD_LPDDR_MANUFACTURER_SPECIFIC         ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data
 449   UINT8                                   Reserved[383 - 382 + 1];  ///< 382-383 Reserved
 450 } SPD_LPDDR_MANUFACTURING_DATA;
 451
 452 typedef struct {
 453   UINT8                                   Reserved[511 - 384 + 1];  ///< 384-511 End User Programmable
 454 } SPD_LPDDR_END_USER_SECTION;
 455
 456 ///
 457 /// LPDDR Serial Presence Detect structure
 458 ///
 459 typedef struct {
 460   SPD_LPDDR_BASE_SECTION                  Base;                     ///< 0-127   Base Configuration and DRAM Parameters
 461   SPD_LPDDR_MODULE_SPECIFIC               Module;                   ///< 128-255 Module-Specific Section
 462   UINT8                                   Reserved[319 - 256 + 1];  ///< 256-319 Hybrid Memory Parameters
 463   SPD_LPDDR_MANUFACTURING_DATA            ManufactureInfo;          ///< 320-383 Manufacturing Information
 464   SPD_LPDDR_END_USER_SECTION              EndUser;                  ///< 384-511 End User Programmable
 465 } SPD_LPDDR;
 466
 467 #pragma pack (pop)
 468 #endif