2 Platform TPM Profile Specification definition for TPM2.0.
3 It covers both FIFO and CRB interface.
5 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
14 // PTP FIFO definition
18 // Set structure alignment to 1-byte
23 // Register set map as specified in PTP specification Chapter 5
27 /// Used to gain ownership for this particular port.
30 UINT8 Reserved1
[7]; // 1
32 /// Controls interrupts.
34 UINT32 IntEnable
; // 8
36 /// SIRQ vector to be used by the TPM.
38 UINT8 IntVector
; // 0ch
39 UINT8 Reserved2
[3]; // 0dh
41 /// What caused interrupt.
45 /// Shows which interrupts are supported by that particular TPM.
47 UINT32 InterfaceCapability
; // 14h
49 /// Status Register. Provides status of the TPM.
53 /// Number of consecutive writes that can be done to the TPM.
55 UINT16 BurstCount
; // 19h
57 /// Additional Status Register.
59 UINT8 StatusEx
; // 1Bh
62 /// Read or write FIFO, depending on transaction.
64 UINT32 DataFifo
; // 24h
65 UINT8 Reserved4
[8]; // 28h
67 /// Used to identify the Interface types supported by the TPM.
69 UINT32 InterfaceId
; // 30h
70 UINT8 Reserved5
[0x4c]; // 34h
72 /// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)
74 UINT32 XDataFifo
; // 80h
75 UINT8 Reserved6
[0xe7c]; // 84h
88 UINT8 Reserved
[0xfb]; // 0f05h
92 // Restore original structure alignment
97 // Define pointer types used to access TIS registers on PC
99 typedef PTP_FIFO_REGISTERS
*PTP_FIFO_REGISTERS_PTR
;
102 // Define bits of FIFO Interface Identifier Register
106 UINT32 InterfaceType
: 4;
107 UINT32 InterfaceVersion
: 4;
108 UINT32 CapLocality
: 1;
109 UINT32 Reserved1
: 2;
110 UINT32 CapDataXferSizeSupport
: 2;
114 UINT32 InterfaceSelector
: 2;
115 UINT32 IntfSelLock
: 1;
116 UINT32 Reserved2
: 4;
117 UINT32 Reserved3
: 8;
120 } PTP_FIFO_INTERFACE_IDENTIFIER
;
123 // Define bits of FIFO Interface Capability Register
127 UINT32 DataAvailIntSupport
: 1;
128 UINT32 StsValidIntSupport
: 1;
129 UINT32 LocalityChangeIntSupport
: 1;
130 UINT32 InterruptLevelHigh
: 1;
131 UINT32 InterruptLevelLow
: 1;
132 UINT32 InterruptEdgeRising
: 1;
133 UINT32 InterruptEdgeFalling
: 1;
134 UINT32 CommandReadyIntSupport
: 1;
135 UINT32 BurstCountStatic
: 1;
136 UINT32 DataTransferSizeSupport
: 2;
137 UINT32 Reserved
: 17;
138 UINT32 InterfaceVersion
: 3;
139 UINT32 Reserved2
: 1;
142 } PTP_FIFO_INTERFACE_CAPABILITY
;
147 #define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12 0x0
148 #define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2
149 #define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3
152 // Define bits of ACCESS and STATUS registers
156 /// This bit is a 1 to indicate that the other bits in this register are valid.
158 #define PTP_FIFO_VALID BIT7
160 /// Indicate that this locality is active.
162 #define PTP_FIFO_ACC_ACTIVE BIT5
164 /// Set to 1 to indicate that this locality had the TPM taken away while
165 /// this locality had the TIS_PC_ACC_ACTIVE bit set.
167 #define PTP_FIFO_ACC_SEIZED BIT4
169 /// Set to 1 to indicate that TPM MUST reset the
170 /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
171 /// locality that is writing this bit.
173 #define PTP_FIFO_ACC_SEIZE BIT3
175 /// When this bit is 1, another locality is requesting usage of the TPM.
177 #define PTP_FIFO_ACC_PENDIND BIT2
179 /// Set to 1 to indicate that this locality is requesting to use TPM.
181 #define PTP_FIFO_ACC_RQUUSE BIT1
183 /// A value of 1 indicates that a T/OS has not been established on the platform
185 #define PTP_FIFO_ACC_ESTABLISH BIT0
188 /// This field indicates that STS_DATA and STS_EXPECT are valid
190 #define PTP_FIFO_STS_VALID BIT7
192 /// When this bit is 1, TPM is in the Ready state,
193 /// indicating it is ready to receive a new command.
195 #define PTP_FIFO_STS_READY BIT6
197 /// Write a 1 to this bit to cause the TPM to execute that command.
199 #define PTP_FIFO_STS_GO BIT5
201 /// This bit indicates that the TPM has data available as a response.
203 #define PTP_FIFO_STS_DATA BIT4
205 /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
207 #define PTP_FIFO_STS_EXPECT BIT3
209 /// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
211 #define PTP_FIFO_STS_SELFTEST_DONE BIT2
213 /// Writes a 1 to this bit to force the TPM to re-send the response.
215 #define PTP_FIFO_STS_RETRY BIT1
218 /// TPM Family Identifier.
219 /// 00: TPM 1.2 Family
220 /// 01: TPM 2.0 Family
222 #define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3)
223 #define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2)
224 #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0)
225 #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)
227 /// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.
228 /// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.
230 #define PTP_FIFO_STS_EX_CANCEL BIT0
233 // PTP CRB definition
237 // Set structure alignment to 1-byte
242 // Register set map as specified in PTP specification Chapter 5
246 /// Used to determine current state of Locality of the TPM.
248 UINT32 LocalityState
; // 0
249 UINT8 Reserved1
[4]; // 4
251 /// Used to gain control of the TPM by this Locality.
253 UINT32 LocalityControl
; // 8
255 /// Used to determine whether Locality has been granted or Seized.
257 UINT32 LocalityStatus
; // 0ch
258 UINT8 Reserved2
[0x20]; // 10h
260 /// Used to identify the Interface types supported by the TPM.
262 UINT32 InterfaceId
; // 30h
272 /// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.
274 UINT64 CrbControlExtension
; // 38h
276 /// Register used to initiate transactions for the CRB interface.
278 UINT32 CrbControlRequest
; // 40h
280 /// Register used by the TPM to provide status of the CRB interface.
282 UINT32 CrbControlStatus
; // 44h
284 /// Register used by software to cancel command processing.
286 UINT32 CrbControlCancel
; // 48h
288 /// Register used to indicate presence of command or response data in the CRB buffer.
290 UINT32 CrbControlStart
; // 4Ch
292 /// Register used to configure and respond to interrupts.
294 UINT32 CrbInterruptEnable
; // 50h
295 UINT32 CrbInterruptStatus
; // 54h
297 /// Size of the Command buffer.
299 UINT32 CrbControlCommandSize
; // 58h
301 /// Command buffer start address
303 UINT32 CrbControlCommandAddressLow
; // 5Ch
304 UINT32 CrbControlCommandAddressHigh
; // 60h
306 /// Size of the Response buffer
308 UINT32 CrbControlResponseSize
; // 64h
310 /// Address of the start of the Response buffer
312 UINT64 CrbControlResponseAddrss
; // 68h
313 UINT8 Reserved4
[0x10]; // 70h
315 /// Command/Response Data may be defined as large as 3968 (0xF80).
317 UINT8 CrbDataBuffer
[0xF80]; // 80h
321 // Define pointer types used to access CRB registers on PTP
323 typedef PTP_CRB_REGISTERS
*PTP_CRB_REGISTERS_PTR
;
326 // Define bits of CRB Interface Identifier Register
330 UINT32 InterfaceType
: 4;
331 UINT32 InterfaceVersion
: 4;
332 UINT32 CapLocality
: 1;
333 UINT32 CapCRBIdleBypass
: 1;
334 UINT32 Reserved1
: 1;
335 UINT32 CapDataXferSizeSupport
: 2;
339 UINT32 InterfaceSelector
: 2;
340 UINT32 IntfSelLock
: 1;
341 UINT32 Reserved2
: 4;
345 } PTP_CRB_INTERFACE_IDENTIFIER
;
350 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO 0x0
351 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB 0x1
352 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS 0xF
357 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO 0x0
358 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB 0x1
361 /// InterfaceSelector
363 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO 0x0
364 #define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB 0x1
367 // Define bits of Locality State Register
371 /// This bit indicates whether all other bits of this register contain valid values, if it is a 1.
373 #define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7
382 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4)
383 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0)
384 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)
385 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3)
386 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3)
387 #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4)
390 /// A 0 indicates to the host that no locality is assigned.
391 /// A 1 indicates a locality has been assigned.
393 #define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1
396 /// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End
397 /// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.
399 #define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0
402 // Define bits of Locality Control Register
406 /// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4.
408 #define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT BIT3
411 /// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.
413 #define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2
416 /// Writes (1): The active Locality is done with the TPM.
418 #define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1
421 /// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.
423 #define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0
426 // Define bits of Locality Status Register
430 /// 0: A higher locality has not initiated a Seize arbitration process.
431 /// 1: A higher locality has Seized the TPM from this locality.
433 #define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1
436 /// 0: Locality has not been granted to the TPM.
437 /// 1: Locality has been granted access to the TPM
439 #define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0
442 // Define bits of CRB Control Area Request Register
446 /// Used by Software to indicate transition the TPM to and from the Idle state
447 /// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle
448 /// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.
449 /// TPM SHALL complete this transition within TIMEOUT_C.
451 #define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1
454 /// Used by Software to request the TPM transition to the Ready State.
455 /// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command.
456 /// 0: Cleared to 0 by TPM to acknowledge the request.
457 /// TPM SHALL complete this transition within TIMEOUT_C.
459 #define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0
462 // Define bits of CRB Control Area Status Register
466 /// Used by TPM to indicate it is in the Idle State
467 /// 1: Set by TPM when in the Idle State
468 /// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.
469 /// SHALL be cleared by TIMEOUT_C.
471 #define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1
474 /// Used by the TPM to indicate current status.
475 /// 1: Set by TPM to indicate a FATAL Error
476 /// 0: Indicates TPM is operational
478 #define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0
481 // Define bits of CRB Control Cancel Register
485 /// Used by software to cancel command processing Reads return correct value
486 /// Writes (0000 0001h): Cancel a command
487 /// Writes (0000 0000h): Clears field when command has been cancelled
489 #define PTP_CRB_CONTROL_CANCEL BIT0
492 // Define bits of CRB Control Start Register
496 /// When set by software, indicates a command is ready for processing.
497 /// Writes (0000 0001h): TPM transitions to Command Execution
498 /// Writes (0000 0000h): TPM clears this field and transitions to Command Completion
500 #define PTP_CRB_CONTROL_START BIT0
503 // Restore original structure alignment
508 // Default TimeOut value
510 #define PTP_TIMEOUT_A (750 * 1000) // 750ms
511 #define PTP_TIMEOUT_B (2000 * 1000) // 2s
512 #define PTP_TIMEOUT_C (200 * 1000) // 200ms
513 #define PTP_TIMEOUT_D (30 * 1000) // 30ms