MdePkg/Include/IndustryStandard/TpmTis.h

   1 /** @file
   2   TPM Interface Specification definition.
   3   It covers both TPM1.2 and TPM2.0.
   4
   5 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef _TPM_TIS_H_
  11 #define _TPM_TIS_H_
  12
  13 //
  14 // Set structure alignment to 1-byte
  15 //
  16 #pragma pack (1)
  17
  18 //
  19 // Register set map as specified in TIS specification Chapter 10
  20 //
  21 typedef struct {
  22   ///
  23   /// Used to gain ownership for this particular port.
  24   ///
  25   UINT8                             Access;             // 0
  26   UINT8                             Reserved1[7];       // 1
  27   ///
  28   /// Controls interrupts.
  29   ///
  30   UINT32                            IntEnable;          // 8
  31   ///
  32   /// SIRQ vector to be used by the TPM.
  33   ///
  34   UINT8                             IntVector;          // 0ch
  35   UINT8                             Reserved2[3];       // 0dh
  36   ///
  37   /// What caused interrupt.
  38   ///
  39   UINT32                            IntSts;             // 10h
  40   ///
  41   /// Shows which interrupts are supported by that particular TPM.
  42   ///
  43   UINT32                            IntfCapability;     // 14h
  44   ///
  45   /// Status Register. Provides status of the TPM.
  46   ///
  47   UINT8                             Status;             // 18h
  48   ///
  49   /// Number of consecutive writes that can be done to the TPM.
  50   ///
  51   UINT16                            BurstCount;         // 19h
  52   UINT8                             Reserved3[9];
  53   ///
  54   /// Read or write FIFO, depending on transaction.
  55   ///
  56   UINT32                            DataFifo;           // 24h
  57   UINT8                             Reserved4[0xed8];   // 28h
  58   ///
  59   /// Vendor ID
  60   ///
  61   UINT16                            Vid;                // 0f00h
  62   ///
  63   /// Device ID
  64   ///
  65   UINT16                            Did;                // 0f02h
  66   ///
  67   /// Revision ID
  68   ///
  69   UINT8                             Rid;                // 0f04h
  70   UINT8                             Reserved[0x7b];     // 0f05h
  71   ///
  72   /// Alias to I/O legacy space.
  73   ///
  74   UINT32                            LegacyAddress1;     // 0f80h
  75   ///
  76   /// Additional 8 bits for I/O legacy space extension.
  77   ///
  78   UINT32                            LegacyAddress1Ex;   // 0f84h
  79   ///
  80   /// Alias to second I/O legacy space.
  81   ///
  82   UINT32                            LegacyAddress2;     // 0f88h
  83   ///
  84   /// Additional 8 bits for second I/O legacy space extension.
  85   ///
  86   UINT32                            LegacyAddress2Ex;   // 0f8ch
  87   ///
  88   /// Vendor-defined configuration registers.
  89   ///
  90   UINT8                             VendorDefined[0x70];// 0f90h
  91 } TIS_PC_REGISTERS;
  92
  93 //
  94 // Restore original structure alignment
  95 //
  96 #pragma pack ()
  97
  98 //
  99 // Define pointer types used to access TIS registers on PC
 100 //
 101 typedef TIS_PC_REGISTERS  *TIS_PC_REGISTERS_PTR;
 102
 103 //
 104 // Define bits of ACCESS and STATUS registers
 105 //
 106
 107 ///
 108 /// This bit is a 1 to indicate that the other bits in this register are valid.
 109 ///
 110 #define TIS_PC_VALID                BIT7
 111 ///
 112 /// Indicate that this locality is active.
 113 ///
 114 #define TIS_PC_ACC_ACTIVE           BIT5
 115 ///
 116 /// Set to 1 to indicate that this locality had the TPM taken away while
 117 /// this locality had the TIS_PC_ACC_ACTIVE bit set.
 118 ///
 119 #define TIS_PC_ACC_SEIZED           BIT4
 120 ///
 121 /// Set to 1 to indicate that TPM MUST reset the
 122 /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
 123 /// locality that is writing this bit.
 124 ///
 125 #define TIS_PC_ACC_SEIZE            BIT3
 126 ///
 127 /// When this bit is 1, another locality is requesting usage of the TPM.
 128 ///
 129 #define TIS_PC_ACC_PENDIND          BIT2
 130 ///
 131 /// Set to 1 to indicate that this locality is requesting to use TPM.
 132 ///
 133 #define TIS_PC_ACC_RQUUSE           BIT1
 134 ///
 135 /// A value of 1 indicates that a T/OS has not been established on the platform
 136 ///
 137 #define TIS_PC_ACC_ESTABLISH        BIT0
 138
 139 ///
 140 /// Write a 1 to this bit to notify TPM to cancel currently executing command
 141 ///
 142 #define TIS_PC_STS_CANCEL           BIT24
 143 ///
 144 /// This field indicates that STS_DATA and STS_EXPECT are valid
 145 ///
 146 #define TIS_PC_STS_VALID            BIT7
 147 ///
 148 /// When this bit is 1, TPM is in the Ready state,
 149 /// indicating it is ready to receive a new command.
 150 ///
 151 #define TIS_PC_STS_READY            BIT6
 152 ///
 153 /// Write a 1 to this bit to cause the TPM to execute that command.
 154 ///
 155 #define TIS_PC_STS_GO               BIT5
 156 ///
 157 /// This bit indicates that the TPM has data available as a response.
 158 ///
 159 #define TIS_PC_STS_DATA             BIT4
 160 ///
 161 /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
 162 ///
 163 #define TIS_PC_STS_EXPECT           BIT3
 164 ///
 165 /// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.
 166 ///
 167 #define TIS_PC_STS_SELFTEST_DONE    BIT2
 168 ///
 169 /// Writes a 1 to this bit to force the TPM to re-send the response.
 170 ///
 171 #define TIS_PC_STS_RETRY            BIT1
 172
 173 //
 174 // Default TimeOut value
 175 //
 176 #define TIS_TIMEOUT_A               (750  * 1000)  // 750ms
 177 #define TIS_TIMEOUT_B               (2000 * 1000)  // 2s
 178 #define TIS_TIMEOUT_C               (750  * 1000)  // 750ms
 179 #define TIS_TIMEOUT_D               (750  * 1000)  // 750ms
 180
 181 #endif