MdePkg/Include/Library/CacheMaintenanceLib.h

   1 /** @file
   2   Provides services to maintain instruction and data caches.
   3
   4   The Cache Maintenance Library provides abstractions for basic processor cache operations.
   5   It removes the need to use assembly in C code.
   6
   7 Copyright (c) 2006 - 2008, Intel Corporation<BR>
   8 All rights reserved. This program and the accompanying materials
   9 are licensed and made available under the terms and conditions of the BSD License
  10 which accompanies this distribution.  The full text of the license may be found at
  11 http://opensource.org/licenses/bsd-license.php
  12
  13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16 **/
  17
  18 #ifndef __CACHE_MAINTENANCE_LIB__
  19 #define __CACHE_MAINTENANCE_LIB__
  20
  21 /**
  22   Invalidates the entire instruction cache in cache coherency domain of the
  23   calling CPU.
  24
  25   Invalidates the entire instruction cache in cache coherency domain of the
  26   calling CPU.
  27
  28 **/
  29 VOID
  30 EFIAPI
  31 InvalidateInstructionCache (
  32   VOID
  33   );
  34
  35 /**
  36   Invalidates a range of instruction cache lines in the cache coherency domain
  37   of the calling CPU.
  38
  39   Invalidates the instruction cache lines specified by Address and Length. If
  40   Address is not aligned on a cache line boundary, then entire instruction
  41   cache line containing Address is invalidated. If Address + Length is not
  42   aligned on a cache line boundary, then the entire instruction cache line
  43   containing Address + Length -1 is invalidated. This function may choose to
  44   invalidate the entire instruction cache if that is more efficient than
  45   invalidating the specified range. If Length is 0, the no instruction cache
  46   lines are invalidated. Address is returned.
  47
  48   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  49
  50   @param  Address The base address of the instruction cache lines to
  51                   invalidate. If the CPU is in a physical addressing mode, then
  52                   Address is a physical address. If the CPU is in a virtual
  53                   addressing mode, then Address is a virtual address.
  54
  55   @param  Length  The number of bytes to invalidate from the instruction cache.
  56
  57   @return Address.
  58
  59 **/
  60 VOID *
  61 EFIAPI
  62 InvalidateInstructionCacheRange (
  63   IN      VOID                      *Address,
  64   IN      UINTN                     Length
  65   );
  66
  67 /**
  68   Writes Back and Invalidates the entire data cache in cache coherency domain
  69   of the calling CPU.
  70
  71   Writes Back and Invalidates the entire data cache in cache coherency domain
  72   of the calling CPU. This function guarantees that all dirty cache lines are
  73   written back to system memory, and also invalidates all the data cache lines
  74   in the cache coherency domain of the calling CPU.
  75
  76 **/
  77 VOID
  78 EFIAPI
  79 WriteBackInvalidateDataCache (
  80   VOID
  81   );
  82
  83 /**
  84   Writes Back and Invalidates a range of data cache lines in the cache
  85   coherency domain of the calling CPU.
  86
  87   Writes Back and Invalidate the data cache lines specified by Address and
  88   Length. If Address is not aligned on a cache line boundary, then entire data
  89   cache line containing Address is written back and invalidated. If Address +
  90   Length is not aligned on a cache line boundary, then the entire data cache
  91   line containing Address + Length -1 is written back and invalidated. This
  92   function may choose to write back and invalidate the entire data cache if
  93   that is more efficient than writing back and invalidating the specified
  94   range. If Length is 0, the no data cache lines are written back and
  95   invalidated. Address is returned.
  96
  97   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  98
  99   @param  Address The base address of the data cache lines to write back and
 100                   invalidate. If the CPU is in a physical addressing mode, then
 101                   Address is a physical address. If the CPU is in a virtual
 102                   addressing mode, then Address is a virtual address.
 103   @param  Length  The number of bytes to write back and invalidate from the
 104                   data cache.
 105
 106   @return Address of cache invalidation.
 107
 108 **/
 109 VOID *
 110 EFIAPI
 111 WriteBackInvalidateDataCacheRange (
 112   IN      VOID                      *Address,
 113   IN      UINTN                     Length
 114   );
 115
 116 /**
 117   Writes Back the entire data cache in cache coherency domain of the calling
 118   CPU.
 119
 120   Writes Back the entire data cache in cache coherency domain of the calling
 121   CPU. This function guarantees that all dirty cache lines are written back to
 122   system memory. This function may also invalidate all the data cache lines in
 123   the cache coherency domain of the calling CPU.
 124
 125 **/
 126 VOID
 127 EFIAPI
 128 WriteBackDataCache (
 129   VOID
 130   );
 131
 132 /**
 133   Writes Back a range of data cache lines in the cache coherency domain of the
 134   calling CPU.
 135
 136   Writes Back the data cache lines specified by Address and Length. If Address
 137   is not aligned on a cache line boundary, then entire data cache line
 138   containing Address is written back. If Address + Length is not aligned on a
 139   cache line boundary, then the entire data cache line containing Address +
 140   Length -1 is written back. This function may choose to write back the entire
 141   data cache if that is more efficient than writing back the specified range.
 142   If Length is 0, the no data cache lines are written back. This function may
 143   also invalidate all the data cache lines in the specified range of the cache
 144   coherency domain of the calling CPU. Address is returned.
 145
 146   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 147
 148   @param  Address The base address of the data cache lines to write back. If
 149                   the CPU is in a physical addressing mode, then Address is a
 150                   physical address. If the CPU is in a virtual addressing
 151                   mode, then Address is a virtual address.
 152   @param  Length  The number of bytes to write back from the data cache.
 153
 154   @return Address of cache written in main memory.
 155
 156 **/
 157 VOID *
 158 EFIAPI
 159 WriteBackDataCacheRange (
 160   IN      VOID                      *Address,
 161   IN      UINTN                     Length
 162   );
 163
 164 /**
 165   Invalidates the entire data cache in cache coherency domain of the calling
 166   CPU.
 167
 168   Invalidates the entire data cache in cache coherency domain of the calling
 169   CPU. This function must be used with care because dirty cache lines are not
 170   written back to system memory. It is typically used for cache diagnostics. If
 171   the CPU does not support invalidation of the entire data cache, then a write
 172   back and invalidate operation should be performed on the entire data cache.
 173
 174 **/
 175 VOID
 176 EFIAPI
 177 InvalidateDataCache (
 178   VOID
 179   );
 180
 181 /**
 182   Invalidates a range of data cache lines in the cache coherency domain of the
 183   calling CPU.
 184
 185   Invalidates the data cache lines specified by Address and Length. If Address
 186   is not aligned on a cache line boundary, then entire data cache line
 187   containing Address is invalidated. If Address + Length is not aligned on a
 188   cache line boundary, then the entire data cache line containing Address +
 189   Length -1 is invalidated. This function must never invalidate any cache lines
 190   outside the specified range. If Length is 0, the no data cache lines are
 191   invalidated. Address is returned. This function must be used with care
 192   because dirty cache lines are not written back to system memory. It is
 193   typically used for cache diagnostics. If the CPU does not support
 194   invalidation of a data cache range, then a write back and invalidate
 195   operation should be performed on the data cache range.
 196
 197   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 198
 199   @param  Address The base address of the data cache lines to invalidate. If
 200                   the CPU is in a physical addressing mode, then Address is a
 201                   physical address. If the CPU is in a virtual addressing mode,
 202                   then Address is a virtual address.
 203   @param  Length  The number of bytes to invalidate from the data cache.
 204
 205   @return Address.
 206
 207 **/
 208 VOID *
 209 EFIAPI
 210 InvalidateDataCacheRange (
 211   IN      VOID                      *Address,
 212   IN      UINTN                     Length
 213   );
 214
 215 #endif