MdePkg/Include/Library/PciCf8Lib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
   3
   4   This library is identical to the PCI Library, except the access method for performing PCI
   5   configuration cycles must be through I/O ports 0xCF8 and 0xCFC.  This library only allows
   6   access to PCI Segment #0.
   7
   8 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   9 SPDX-License-Identifier: BSD-2-Clause-Patent
  10
  11 **/
  12
  13 #ifndef __PCI_CF8_LIB_H__
  14 #define __PCI_CF8_LIB_H__
  15
  16
  17 /**
  18   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  19   address that can be passed to the PCI Library functions.
  20
  21   Computes an address that is compatible with the PCI Library functions. The
  22   unused upper bits of Bus, Device, Function and Register are stripped prior to
  23   the generation of the address.
  24
  25   @param  Bus       PCI Bus number. Range 0..255.
  26   @param  Device    PCI Device number. Range 0..31.
  27   @param  Function  PCI Function number. Range 0..7.
  28   @param  Register  PCI Register number. Range 0..255.
  29
  30   @return The encode PCI address.
  31
  32 **/
  33 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
  34   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  35
  36 /**
  37   Registers a PCI device so PCI configuration registers may be accessed after
  38   SetVirtualAddressMap().
  39
  40   Registers the PCI device specified by Address so all the PCI configuration registers
  41   associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
  42
  43   If Address > 0x0FFFFFFF, then ASSERT().
  44   If the register specified by Address >= 0x100, then ASSERT().
  45
  46   @param  Address Address that encodes the PCI Bus, Device, Function and
  47                   Register.
  48
  49   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  50   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  51                                    after ExitBootServices().
  52   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  53                                    at runtime could not be mapped.
  54   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  55                                    complete the registration.
  56
  57 **/
  58 RETURN_STATUS
  59 EFIAPI
  60 PciCf8RegisterForRuntimeAccess (
  61   IN UINTN  Address
  62   );
  63
  64 /**
  65   Reads an 8-bit PCI configuration register.
  66
  67   Reads and returns the 8-bit PCI configuration register specified by Address.
  68   This function must guarantee that all PCI read and write operations are
  69   serialized.
  70
  71   If Address > 0x0FFFFFFF, then ASSERT().
  72   If the register specified by Address >= 0x100, then ASSERT().
  73
  74   @param  Address Address that encodes the PCI Bus, Device, Function and
  75                   Register.
  76
  77   @return The read value from the PCI configuration register.
  78
  79 **/
  80 UINT8
  81 EFIAPI
  82 PciCf8Read8 (
  83   IN      UINTN                     Address
  84   );
  85
  86 /**
  87   Writes an 8-bit PCI configuration register.
  88
  89   Writes the 8-bit PCI configuration register specified by Address with the
  90   value specified by Value. Value is returned. This function must guarantee
  91   that all PCI read and write operations are serialized.
  92
  93   If Address > 0x0FFFFFFF, then ASSERT().
  94   If the register specified by Address >= 0x100, then ASSERT().
  95
  96   @param  Address Address that encodes the PCI Bus, Device, Function and
  97                   Register.
  98   @param  Value   The value to write.
  99
 100   @return The value written to the PCI configuration register.
 101
 102 **/
 103 UINT8
 104 EFIAPI
 105 PciCf8Write8 (
 106   IN      UINTN                     Address,
 107   IN      UINT8                     Value
 108   );
 109
 110 /**
 111   Performs a bitwise OR of an 8-bit PCI configuration register with
 112   an 8-bit value.
 113
 114   Reads the 8-bit PCI configuration register specified by Address, performs a
 115   bitwise OR between the read result and the value specified by
 116   OrData, and writes the result to the 8-bit PCI configuration register
 117   specified by Address. The value written to the PCI configuration register is
 118   returned. This function must guarantee that all PCI read and write operations
 119   are serialized.
 120
 121   If Address > 0x0FFFFFFF, then ASSERT().
 122   If the register specified by Address >= 0x100, then ASSERT().
 123
 124   @param  Address Address that encodes the PCI Bus, Device, Function and
 125                   Register.
 126   @param  OrData  The value to OR with the PCI configuration register.
 127
 128   @return The value written back to the PCI configuration register.
 129
 130 **/
 131 UINT8
 132 EFIAPI
 133 PciCf8Or8 (
 134   IN      UINTN                     Address,
 135   IN      UINT8                     OrData
 136   );
 137
 138 /**
 139   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 140   value.
 141
 142   Reads the 8-bit PCI configuration register specified by Address, performs a
 143   bitwise AND between the read result and the value specified by AndData, and
 144   writes the result to the 8-bit PCI configuration register specified by
 145   Address. The value written to the PCI configuration register is returned.
 146   This function must guarantee that all PCI read and write operations are
 147   serialized.
 148
 149   If Address > 0x0FFFFFFF, then ASSERT().
 150   If the register specified by Address >= 0x100, then ASSERT().
 151
 152   @param  Address Address that encodes the PCI Bus, Device, Function and
 153                   Register.
 154   @param  AndData The value to AND with the PCI configuration register.
 155
 156   @return The value written back to the PCI configuration register.
 157
 158 **/
 159 UINT8
 160 EFIAPI
 161 PciCf8And8 (
 162   IN      UINTN                     Address,
 163   IN      UINT8                     AndData
 164   );
 165
 166 /**
 167   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 168   value, followed a  bitwise OR with another 8-bit value.
 169
 170   Reads the 8-bit PCI configuration register specified by Address, performs a
 171   bitwise AND between the read result and the value specified by AndData,
 172   performs a bitwise OR between the result of the AND operation and
 173   the value specified by OrData, and writes the result to the 8-bit PCI
 174   configuration register specified by Address. The value written to the PCI
 175   configuration register is returned. This function must guarantee that all PCI
 176   read and write operations are serialized.
 177
 178   If Address > 0x0FFFFFFF, then ASSERT().
 179   If the register specified by Address >= 0x100, then ASSERT().
 180
 181   @param  Address Address that encodes the PCI Bus, Device, Function and
 182                   Register.
 183   @param  AndData The value to AND with the PCI configuration register.
 184   @param  OrData  The value to OR with the result of the AND operation.
 185
 186   @return The value written back to the PCI configuration register.
 187
 188 **/
 189 UINT8
 190 EFIAPI
 191 PciCf8AndThenOr8 (
 192   IN      UINTN                     Address,
 193   IN      UINT8                     AndData,
 194   IN      UINT8                     OrData
 195   );
 196
 197 /**
 198   Reads a bit field of a PCI configuration register.
 199
 200   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 201   specified by the StartBit and the EndBit. The value of the bit field is
 202   returned.
 203
 204   If Address > 0x0FFFFFFF, then ASSERT().
 205   If the register specified by Address >= 0x100, then ASSERT().
 206   If StartBit is greater than 7, then ASSERT().
 207   If EndBit is greater than 7, then ASSERT().
 208   If EndBit is less than StartBit, then ASSERT().
 209
 210   @param  Address   PCI configuration register to read.
 211   @param  StartBit  The ordinal of the least significant bit in the bit field.
 212                     Range 0..7.
 213   @param  EndBit    The ordinal of the most significant bit in the bit field.
 214                     Range 0..7.
 215
 216   @return The value of the bit field read from the PCI configuration register.
 217
 218 **/
 219 UINT8
 220 EFIAPI
 221 PciCf8BitFieldRead8 (
 222   IN      UINTN                     Address,
 223   IN      UINTN                     StartBit,
 224   IN      UINTN                     EndBit
 225   );
 226
 227 /**
 228   Writes a bit field to a PCI configuration register.
 229
 230   Writes Value to the bit field of the PCI configuration register. The bit
 231   field is specified by the StartBit and the EndBit. All other bits in the
 232   destination PCI configuration register are preserved. The new value of the
 233   8-bit register is returned.
 234
 235   If Address > 0x0FFFFFFF, then ASSERT().
 236   If the register specified by Address >= 0x100, then ASSERT().
 237   If StartBit is greater than 7, then ASSERT().
 238   If EndBit is greater than 7, then ASSERT().
 239   If EndBit is less than StartBit, then ASSERT().
 240   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 241
 242   @param  Address   PCI configuration register to write.
 243   @param  StartBit  The ordinal of the least significant bit in the bit field.
 244                     Range 0..7.
 245   @param  EndBit    The ordinal of the most significant bit in the bit field.
 246                     Range 0..7.
 247   @param  Value     New value of the bit field.
 248
 249   @return The value written back to the PCI configuration register.
 250
 251 **/
 252 UINT8
 253 EFIAPI
 254 PciCf8BitFieldWrite8 (
 255   IN      UINTN                     Address,
 256   IN      UINTN                     StartBit,
 257   IN      UINTN                     EndBit,
 258   IN      UINT8                     Value
 259   );
 260
 261 /**
 262   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 263   writes the result back to the bit field in the 8-bit port.
 264
 265   Reads the 8-bit PCI configuration register specified by Address, performs a
 266   bitwise OR between the read result and the value specified by
 267   OrData, and writes the result to the 8-bit PCI configuration register
 268   specified by Address. The value written to the PCI configuration register is
 269   returned. This function must guarantee that all PCI read and write operations
 270   are serialized. Extra left bits in OrData are stripped.
 271
 272   If Address > 0x0FFFFFFF, then ASSERT().
 273   If the register specified by Address >= 0x100, then ASSERT().
 274   If StartBit is greater than 7, then ASSERT().
 275   If EndBit is greater than 7, then ASSERT().
 276   If EndBit is less than StartBit, then ASSERT().
 277   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 278
 279   @param  Address   PCI configuration register to write.
 280   @param  StartBit  The ordinal of the least significant bit in the bit field.
 281                     Range 0..7.
 282   @param  EndBit    The ordinal of the most significant bit in the bit field.
 283                     Range 0..7.
 284   @param  OrData    The value to OR with the PCI configuration register.
 285
 286   @return The value written back to the PCI configuration register.
 287
 288 **/
 289 UINT8
 290 EFIAPI
 291 PciCf8BitFieldOr8 (
 292   IN      UINTN                     Address,
 293   IN      UINTN                     StartBit,
 294   IN      UINTN                     EndBit,
 295   IN      UINT8                     OrData
 296   );
 297
 298 /**
 299   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 300   AND, and writes the result back to the bit field in the 8-bit register.
 301
 302   Reads the 8-bit PCI configuration register specified by Address, performs a
 303   bitwise AND between the read result and the value specified by AndData, and
 304   writes the result to the 8-bit PCI configuration register specified by
 305   Address. The value written to the PCI configuration register is returned.
 306   This function must guarantee that all PCI read and write operations are
 307   serialized. Extra left bits in AndData are stripped.
 308
 309   If Address > 0x0FFFFFFF, then ASSERT().
 310   If the register specified by Address >= 0x100, then ASSERT().
 311   If StartBit is greater than 7, then ASSERT().
 312   If EndBit is greater than 7, then ASSERT().
 313   If EndBit is less than StartBit, then ASSERT().
 314   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 315
 316   @param  Address   PCI configuration register to write.
 317   @param  StartBit  The ordinal of the least significant bit in the bit field.
 318                     Range 0..7.
 319   @param  EndBit    The ordinal of the most significant bit in the bit field.
 320                     Range 0..7.
 321   @param  AndData   The value to AND with the PCI configuration register.
 322
 323   @return The value written back to the PCI configuration register.
 324
 325 **/
 326 UINT8
 327 EFIAPI
 328 PciCf8BitFieldAnd8 (
 329   IN      UINTN                     Address,
 330   IN      UINTN                     StartBit,
 331   IN      UINTN                     EndBit,
 332   IN      UINT8                     AndData
 333   );
 334
 335 /**
 336   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 337   bitwise OR, and writes the result back to the bit field in the
 338   8-bit port.
 339
 340   Reads the 8-bit PCI configuration register specified by Address, performs a
 341   bitwise AND followed by a bitwise OR between the read result and
 342   the value specified by AndData, and writes the result to the 8-bit PCI
 343   configuration register specified by Address. The value written to the PCI
 344   configuration register is returned. This function must guarantee that all PCI
 345   read and write operations are serialized. Extra left bits in both AndData and
 346   OrData are stripped.
 347
 348   If Address > 0x0FFFFFFF, then ASSERT().
 349   If the register specified by Address >= 0x100, then ASSERT().
 350   If StartBit is greater than 7, then ASSERT().
 351   If EndBit is greater than 7, then ASSERT().
 352   If EndBit is less than StartBit, then ASSERT().
 353   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 354   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 355
 356   @param  Address   PCI configuration register to write.
 357   @param  StartBit  The ordinal of the least significant bit in the bit field.
 358                     Range 0..7.
 359   @param  EndBit    The ordinal of the most significant bit in the bit field.
 360                     Range 0..7.
 361   @param  AndData   The value to AND with the PCI configuration register.
 362   @param  OrData    The value to OR with the result of the AND operation.
 363
 364   @return The value written back to the PCI configuration register.
 365
 366 **/
 367 UINT8
 368 EFIAPI
 369 PciCf8BitFieldAndThenOr8 (
 370   IN      UINTN                     Address,
 371   IN      UINTN                     StartBit,
 372   IN      UINTN                     EndBit,
 373   IN      UINT8                     AndData,
 374   IN      UINT8                     OrData
 375   );
 376
 377 /**
 378   Reads a 16-bit PCI configuration register.
 379
 380   Reads and returns the 16-bit PCI configuration register specified by Address.
 381   This function must guarantee that all PCI read and write operations are
 382   serialized.
 383
 384   If Address > 0x0FFFFFFF, then ASSERT().
 385   If Address is not aligned on a 16-bit boundary, then ASSERT().
 386   If the register specified by Address >= 0x100, then ASSERT().
 387
 388   @param  Address Address that encodes the PCI Bus, Device, Function and
 389                   Register.
 390
 391   @return The read value from the PCI configuration register.
 392
 393 **/
 394 UINT16
 395 EFIAPI
 396 PciCf8Read16 (
 397   IN      UINTN                     Address
 398   );
 399
 400 /**
 401   Writes a 16-bit PCI configuration register.
 402
 403   Writes the 16-bit PCI configuration register specified by Address with the
 404   value specified by Value. Value is returned. This function must guarantee
 405   that all PCI read and write operations are serialized.
 406
 407   If Address > 0x0FFFFFFF, then ASSERT().
 408   If Address is not aligned on a 16-bit boundary, then ASSERT().
 409   If the register specified by Address >= 0x100, then ASSERT().
 410
 411   @param  Address Address that encodes the PCI Bus, Device, Function and
 412                   Register.
 413   @param  Value   The value to write.
 414
 415   @return The value written to the PCI configuration register.
 416
 417 **/
 418 UINT16
 419 EFIAPI
 420 PciCf8Write16 (
 421   IN      UINTN                     Address,
 422   IN      UINT16                    Value
 423   );
 424
 425 /**
 426   Performs a bitwise OR of a 16-bit PCI configuration register with
 427   a 16-bit value.
 428
 429   Reads the 16-bit PCI configuration register specified by Address, performs a
 430   bitwise OR between the read result and the value specified by
 431   OrData, and writes the result to the 16-bit PCI configuration register
 432   specified by Address. The value written to the PCI configuration register is
 433   returned. This function must guarantee that all PCI read and write operations
 434   are serialized.
 435
 436   If Address > 0x0FFFFFFF, then ASSERT().
 437   If Address is not aligned on a 16-bit boundary, then ASSERT().
 438   If the register specified by Address >= 0x100, then ASSERT().
 439
 440   @param  Address Address that encodes the PCI Bus, Device, Function and
 441                   Register.
 442   @param  OrData  The value to OR with the PCI configuration register.
 443
 444   @return The value written back to the PCI configuration register.
 445
 446 **/
 447 UINT16
 448 EFIAPI
 449 PciCf8Or16 (
 450   IN      UINTN                     Address,
 451   IN      UINT16                    OrData
 452   );
 453
 454 /**
 455   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 456   value.
 457
 458   Reads the 16-bit PCI configuration register specified by Address, performs a
 459   bitwise AND between the read result and the value specified by AndData, and
 460   writes the result to the 16-bit PCI configuration register specified by
 461   Address. The value written to the PCI configuration register is returned.
 462   This function must guarantee that all PCI read and write operations are
 463   serialized.
 464
 465   If Address > 0x0FFFFFFF, then ASSERT().
 466   If Address is not aligned on a 16-bit boundary, then ASSERT().
 467   If the register specified by Address >= 0x100, then ASSERT().
 468
 469   @param  Address Address that encodes the PCI Bus, Device, Function and
 470                   Register.
 471   @param  AndData The value to AND with the PCI configuration register.
 472
 473   @return The value written back to the PCI configuration register.
 474
 475 **/
 476 UINT16
 477 EFIAPI
 478 PciCf8And16 (
 479   IN      UINTN                     Address,
 480   IN      UINT16                    AndData
 481   );
 482
 483 /**
 484   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 485   value, followed a  bitwise OR with another 16-bit value.
 486
 487   Reads the 16-bit PCI configuration register specified by Address, performs a
 488   bitwise AND between the read result and the value specified by AndData,
 489   performs a bitwise OR between the result of the AND operation and
 490   the value specified by OrData, and writes the result to the 16-bit PCI
 491   configuration register specified by Address. The value written to the PCI
 492   configuration register is returned. This function must guarantee that all PCI
 493   read and write operations are serialized.
 494
 495   If Address > 0x0FFFFFFF, then ASSERT().
 496   If Address is not aligned on a 16-bit boundary, then ASSERT().
 497   If the register specified by Address >= 0x100, then ASSERT().
 498
 499   @param  Address Address that encodes the PCI Bus, Device, Function and
 500                   Register.
 501   @param  AndData The value to AND with the PCI configuration register.
 502   @param  OrData  The value to OR with the result of the AND operation.
 503
 504   @return The value written back to the PCI configuration register.
 505
 506 **/
 507 UINT16
 508 EFIAPI
 509 PciCf8AndThenOr16 (
 510   IN      UINTN                     Address,
 511   IN      UINT16                    AndData,
 512   IN      UINT16                    OrData
 513   );
 514
 515 /**
 516   Reads a bit field of a PCI configuration register.
 517
 518   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 519   specified by the StartBit and the EndBit. The value of the bit field is
 520   returned.
 521
 522   If Address > 0x0FFFFFFF, then ASSERT().
 523   If Address is not aligned on a 16-bit boundary, then ASSERT().
 524   If the register specified by Address >= 0x100, then ASSERT().
 525   If StartBit is greater than 15, then ASSERT().
 526   If EndBit is greater than 15, then ASSERT().
 527   If EndBit is less than StartBit, then ASSERT().
 528
 529   @param  Address   PCI configuration register to read.
 530   @param  StartBit  The ordinal of the least significant bit in the bit field.
 531                     Range 0..15.
 532   @param  EndBit    The ordinal of the most significant bit in the bit field.
 533                     Range 0..15.
 534
 535   @return The value of the bit field read from the PCI configuration register.
 536
 537 **/
 538 UINT16
 539 EFIAPI
 540 PciCf8BitFieldRead16 (
 541   IN      UINTN                     Address,
 542   IN      UINTN                     StartBit,
 543   IN      UINTN                     EndBit
 544   );
 545
 546 /**
 547   Writes a bit field to a PCI configuration register.
 548
 549   Writes Value to the bit field of the PCI configuration register. The bit
 550   field is specified by the StartBit and the EndBit. All other bits in the
 551   destination PCI configuration register are preserved. The new value of the
 552   16-bit register is returned.
 553
 554   If Address > 0x0FFFFFFF, then ASSERT().
 555   If Address is not aligned on a 16-bit boundary, then ASSERT().
 556   If the register specified by Address >= 0x100, then ASSERT().
 557   If StartBit is greater than 15, then ASSERT().
 558   If EndBit is greater than 15, then ASSERT().
 559   If EndBit is less than StartBit, then ASSERT().
 560   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 561
 562   @param  Address   PCI configuration register to write.
 563   @param  StartBit  The ordinal of the least significant bit in the bit field.
 564                     Range 0..15.
 565   @param  EndBit    The ordinal of the most significant bit in the bit field.
 566                     Range 0..15.
 567   @param  Value     New value of the bit field.
 568
 569   @return The value written back to the PCI configuration register.
 570
 571 **/
 572 UINT16
 573 EFIAPI
 574 PciCf8BitFieldWrite16 (
 575   IN      UINTN                     Address,
 576   IN      UINTN                     StartBit,
 577   IN      UINTN                     EndBit,
 578   IN      UINT16                    Value
 579   );
 580
 581 /**
 582   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 583   writes the result back to the bit field in the 16-bit port.
 584
 585   Reads the 16-bit PCI configuration register specified by Address, performs a
 586   bitwise OR between the read result and the value specified by
 587   OrData, and writes the result to the 16-bit PCI configuration register
 588   specified by Address. The value written to the PCI configuration register is
 589   returned. This function must guarantee that all PCI read and write operations
 590   are serialized. Extra left bits in OrData are stripped.
 591
 592   If Address > 0x0FFFFFFF, then ASSERT().
 593   If Address is not aligned on a 16-bit boundary, then ASSERT().
 594   If the register specified by Address >= 0x100, then ASSERT().
 595   If StartBit is greater than 15, then ASSERT().
 596   If EndBit is greater than 15, then ASSERT().
 597   If EndBit is less than StartBit, then ASSERT().
 598   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 599
 600   @param  Address   PCI configuration register to write.
 601   @param  StartBit  The ordinal of the least significant bit in the bit field.
 602                     Range 0..15.
 603   @param  EndBit    The ordinal of the most significant bit in the bit field.
 604                     Range 0..15.
 605   @param  OrData    The value to OR with the PCI configuration register.
 606
 607   @return The value written back to the PCI configuration register.
 608
 609 **/
 610 UINT16
 611 EFIAPI
 612 PciCf8BitFieldOr16 (
 613   IN      UINTN                     Address,
 614   IN      UINTN                     StartBit,
 615   IN      UINTN                     EndBit,
 616   IN      UINT16                    OrData
 617   );
 618
 619 /**
 620   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 621   AND, and writes the result back to the bit field in the 16-bit register.
 622
 623   Reads the 16-bit PCI configuration register specified by Address, performs a
 624   bitwise AND between the read result and the value specified by AndData, and
 625   writes the result to the 16-bit PCI configuration register specified by
 626   Address. The value written to the PCI configuration register is returned.
 627   This function must guarantee that all PCI read and write operations are
 628   serialized. Extra left bits in AndData are stripped.
 629
 630   If Address > 0x0FFFFFFF, then ASSERT().
 631   If Address is not aligned on a 16-bit boundary, then ASSERT().
 632   If the register specified by Address >= 0x100, then ASSERT().
 633   If StartBit is greater than 15, then ASSERT().
 634   If EndBit is greater than 15, then ASSERT().
 635   If EndBit is less than StartBit, then ASSERT().
 636   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 637
 638   @param  Address   PCI configuration register to write.
 639   @param  StartBit  The ordinal of the least significant bit in the bit field.
 640                     Range 0..15.
 641   @param  EndBit    The ordinal of the most significant bit in the bit field.
 642                     Range 0..15.
 643   @param  AndData   The value to AND with the PCI configuration register.
 644
 645   @return The value written back to the PCI configuration register.
 646
 647 **/
 648 UINT16
 649 EFIAPI
 650 PciCf8BitFieldAnd16 (
 651   IN      UINTN                     Address,
 652   IN      UINTN                     StartBit,
 653   IN      UINTN                     EndBit,
 654   IN      UINT16                    AndData
 655   );
 656
 657 /**
 658   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 659   bitwise OR, and writes the result back to the bit field in the
 660   16-bit port.
 661
 662   Reads the 16-bit PCI configuration register specified by Address, performs a
 663   bitwise AND followed by a bitwise OR between the read result and
 664   the value specified by AndData, and writes the result to the 16-bit PCI
 665   configuration register specified by Address. The value written to the PCI
 666   configuration register is returned. This function must guarantee that all PCI
 667   read and write operations are serialized. Extra left bits in both AndData and
 668   OrData are stripped.
 669
 670   If Address > 0x0FFFFFFF, then ASSERT().
 671   If Address is not aligned on a 16-bit boundary, then ASSERT().
 672   If the register specified by Address >= 0x100, then ASSERT().
 673   If StartBit is greater than 15, then ASSERT().
 674   If EndBit is greater than 15, then ASSERT().
 675   If EndBit is less than StartBit, then ASSERT().
 676   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 677   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 678
 679   @param  Address   PCI configuration register to write.
 680   @param  StartBit  The ordinal of the least significant bit in the bit field.
 681                     Range 0..15.
 682   @param  EndBit    The ordinal of the most significant bit in the bit field.
 683                     Range 0..15.
 684   @param  AndData   The value to AND with the PCI configuration register.
 685   @param  OrData    The value to OR with the result of the AND operation.
 686
 687   @return The value written back to the PCI configuration register.
 688
 689 **/
 690 UINT16
 691 EFIAPI
 692 PciCf8BitFieldAndThenOr16 (
 693   IN      UINTN                     Address,
 694   IN      UINTN                     StartBit,
 695   IN      UINTN                     EndBit,
 696   IN      UINT16                    AndData,
 697   IN      UINT16                    OrData
 698   );
 699
 700 /**
 701   Reads a 32-bit PCI configuration register.
 702
 703   Reads and returns the 32-bit PCI configuration register specified by Address.
 704   This function must guarantee that all PCI read and write operations are
 705   serialized.
 706
 707   If Address > 0x0FFFFFFF, then ASSERT().
 708   If Address is not aligned on a 32-bit boundary, then ASSERT().
 709   If the register specified by Address >= 0x100, then ASSERT().
 710
 711   @param  Address Address that encodes the PCI Bus, Device, Function and
 712                   Register.
 713
 714   @return The read value from the PCI configuration register.
 715
 716 **/
 717 UINT32
 718 EFIAPI
 719 PciCf8Read32 (
 720   IN      UINTN                     Address
 721   );
 722
 723 /**
 724   Writes a 32-bit PCI configuration register.
 725
 726   Writes the 32-bit PCI configuration register specified by Address with the
 727   value specified by Value. Value is returned. This function must guarantee
 728   that all PCI read and write operations are serialized.
 729
 730   If Address > 0x0FFFFFFF, then ASSERT().
 731   If Address is not aligned on a 32-bit boundary, then ASSERT().
 732   If the register specified by Address >= 0x100, then ASSERT().
 733
 734   @param  Address Address that encodes the PCI Bus, Device, Function and
 735                   Register.
 736   @param  Value   The value to write.
 737
 738   @return The value written to the PCI configuration register.
 739
 740 **/
 741 UINT32
 742 EFIAPI
 743 PciCf8Write32 (
 744   IN      UINTN                     Address,
 745   IN      UINT32                    Value
 746   );
 747
 748 /**
 749   Performs a bitwise OR of a 32-bit PCI configuration register with
 750   a 32-bit value.
 751
 752   Reads the 32-bit PCI configuration register specified by Address, performs a
 753   bitwise OR between the read result and the value specified by
 754   OrData, and writes the result to the 32-bit PCI configuration register
 755   specified by Address. The value written to the PCI configuration register is
 756   returned. This function must guarantee that all PCI read and write operations
 757   are serialized.
 758
 759   If Address > 0x0FFFFFFF, then ASSERT().
 760   If Address is not aligned on a 32-bit boundary, then ASSERT().
 761   If the register specified by Address >= 0x100, then ASSERT().
 762
 763   @param  Address Address that encodes the PCI Bus, Device, Function and
 764                   Register.
 765   @param  OrData  The value to OR with the PCI configuration register.
 766
 767   @return The value written back to the PCI configuration register.
 768
 769 **/
 770 UINT32
 771 EFIAPI
 772 PciCf8Or32 (
 773   IN      UINTN                     Address,
 774   IN      UINT32                    OrData
 775   );
 776
 777 /**
 778   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 779   value.
 780
 781   Reads the 32-bit PCI configuration register specified by Address, performs a
 782   bitwise AND between the read result and the value specified by AndData, and
 783   writes the result to the 32-bit PCI configuration register specified by
 784   Address. The value written to the PCI configuration register is returned.
 785   This function must guarantee that all PCI read and write operations are
 786   serialized.
 787
 788   If Address > 0x0FFFFFFF, then ASSERT().
 789   If Address is not aligned on a 32-bit boundary, then ASSERT().
 790   If the register specified by Address >= 0x100, then ASSERT().
 791
 792   @param  Address Address that encodes the PCI Bus, Device, Function and
 793                   Register.
 794   @param  AndData The value to AND with the PCI configuration register.
 795
 796   @return The value written back to the PCI configuration register.
 797
 798 **/
 799 UINT32
 800 EFIAPI
 801 PciCf8And32 (
 802   IN      UINTN                     Address,
 803   IN      UINT32                    AndData
 804   );
 805
 806 /**
 807   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 808   value, followed a  bitwise OR with another 32-bit value.
 809
 810   Reads the 32-bit PCI configuration register specified by Address, performs a
 811   bitwise AND between the read result and the value specified by AndData,
 812   performs a bitwise OR between the result of the AND operation and
 813   the value specified by OrData, and writes the result to the 32-bit PCI
 814   configuration register specified by Address. The value written to the PCI
 815   configuration register is returned. This function must guarantee that all PCI
 816   read and write operations are serialized.
 817
 818   If Address > 0x0FFFFFFF, then ASSERT().
 819   If Address is not aligned on a 32-bit boundary, then ASSERT().
 820   If the register specified by Address >= 0x100, then ASSERT().
 821
 822   @param  Address Address that encodes the PCI Bus, Device, Function and
 823                   Register.
 824   @param  AndData The value to AND with the PCI configuration register.
 825   @param  OrData  The value to OR with the result of the AND operation.
 826
 827   @return The value written back to the PCI configuration register.
 828
 829 **/
 830 UINT32
 831 EFIAPI
 832 PciCf8AndThenOr32 (
 833   IN      UINTN                     Address,
 834   IN      UINT32                    AndData,
 835   IN      UINT32                    OrData
 836   );
 837
 838 /**
 839   Reads a bit field of a PCI configuration register.
 840
 841   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 842   specified by the StartBit and the EndBit. The value of the bit field is
 843   returned.
 844
 845   If Address > 0x0FFFFFFF, then ASSERT().
 846   If Address is not aligned on a 32-bit boundary, then ASSERT().
 847   If the register specified by Address >= 0x100, then ASSERT().
 848   If StartBit is greater than 31, then ASSERT().
 849   If EndBit is greater than 31, then ASSERT().
 850   If EndBit is less than StartBit, then ASSERT().
 851
 852   @param  Address   PCI configuration register to read.
 853   @param  StartBit  The ordinal of the least significant bit in the bit field.
 854                     Range 0..31.
 855   @param  EndBit    The ordinal of the most significant bit in the bit field.
 856                     Range 0..31.
 857
 858   @return The value of the bit field read from the PCI configuration register.
 859
 860 **/
 861 UINT32
 862 EFIAPI
 863 PciCf8BitFieldRead32 (
 864   IN      UINTN                     Address,
 865   IN      UINTN                     StartBit,
 866   IN      UINTN                     EndBit
 867   );
 868
 869 /**
 870   Writes a bit field to a PCI configuration register.
 871
 872   Writes Value to the bit field of the PCI configuration register. The bit
 873   field is specified by the StartBit and the EndBit. All other bits in the
 874   destination PCI configuration register are preserved. The new value of the
 875   32-bit register is returned.
 876
 877   If Address > 0x0FFFFFFF, then ASSERT().
 878   If Address is not aligned on a 32-bit boundary, then ASSERT().
 879   If the register specified by Address >= 0x100, then ASSERT().
 880   If StartBit is greater than 31, then ASSERT().
 881   If EndBit is greater than 31, then ASSERT().
 882   If EndBit is less than StartBit, then ASSERT().
 883   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 884
 885   @param  Address   PCI configuration register to write.
 886   @param  StartBit  The ordinal of the least significant bit in the bit field.
 887                     Range 0..31.
 888   @param  EndBit    The ordinal of the most significant bit in the bit field.
 889                     Range 0..31.
 890   @param  Value     New value of the bit field.
 891
 892   @return The value written back to the PCI configuration register.
 893
 894 **/
 895 UINT32
 896 EFIAPI
 897 PciCf8BitFieldWrite32 (
 898   IN      UINTN                     Address,
 899   IN      UINTN                     StartBit,
 900   IN      UINTN                     EndBit,
 901   IN      UINT32                    Value
 902   );
 903
 904 /**
 905   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 906   writes the result back to the bit field in the 32-bit port.
 907
 908   Reads the 32-bit PCI configuration register specified by Address, performs a
 909   bitwise OR between the read result and the value specified by
 910   OrData, and writes the result to the 32-bit PCI configuration register
 911   specified by Address. The value written to the PCI configuration register is
 912   returned. This function must guarantee that all PCI read and write operations
 913   are serialized. Extra left bits in OrData are stripped.
 914
 915   If Address > 0x0FFFFFFF, then ASSERT().
 916   If Address is not aligned on a 32-bit boundary, then ASSERT().
 917   If the register specified by Address >= 0x100, then ASSERT().
 918   If StartBit is greater than 31, then ASSERT().
 919   If EndBit is greater than 31, then ASSERT().
 920   If EndBit is less than StartBit, then ASSERT().
 921   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 922
 923   @param  Address   PCI configuration register to write.
 924   @param  StartBit  The ordinal of the least significant bit in the bit field.
 925                     Range 0..31.
 926   @param  EndBit    The ordinal of the most significant bit in the bit field.
 927                     Range 0..31.
 928   @param  OrData    The value to OR with the PCI configuration register.
 929
 930   @return The value written back to the PCI configuration register.
 931
 932 **/
 933 UINT32
 934 EFIAPI
 935 PciCf8BitFieldOr32 (
 936   IN      UINTN                     Address,
 937   IN      UINTN                     StartBit,
 938   IN      UINTN                     EndBit,
 939   IN      UINT32                    OrData
 940   );
 941
 942 /**
 943   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 944   AND, and writes the result back to the bit field in the 32-bit register.
 945
 946   Reads the 32-bit PCI configuration register specified by Address, performs a
 947   bitwise AND between the read result and the value specified by AndData, and
 948   writes the result to the 32-bit PCI configuration register specified by
 949   Address. The value written to the PCI configuration register is returned.
 950   This function must guarantee that all PCI read and write operations are
 951   serialized. Extra left bits in AndData are stripped.
 952
 953   If Address > 0x0FFFFFFF, then ASSERT().
 954   If Address is not aligned on a 32-bit boundary, then ASSERT().
 955   If the register specified by Address >= 0x100, then ASSERT().
 956   If StartBit is greater than 31, then ASSERT().
 957   If EndBit is greater than 31, then ASSERT().
 958   If EndBit is less than StartBit, then ASSERT().
 959   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 960
 961   @param  Address   PCI configuration register to write.
 962   @param  StartBit  The ordinal of the least significant bit in the bit field.
 963                     Range 0..31.
 964   @param  EndBit    The ordinal of the most significant bit in the bit field.
 965                     Range 0..31.
 966   @param  AndData   The value to AND with the PCI configuration register.
 967
 968   @return The value written back to the PCI configuration register.
 969
 970 **/
 971 UINT32
 972 EFIAPI
 973 PciCf8BitFieldAnd32 (
 974   IN      UINTN                     Address,
 975   IN      UINTN                     StartBit,
 976   IN      UINTN                     EndBit,
 977   IN      UINT32                    AndData
 978   );
 979
 980 /**
 981   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 982   bitwise OR, and writes the result back to the bit field in the
 983   32-bit port.
 984
 985   Reads the 32-bit PCI configuration register specified by Address, performs a
 986   bitwise AND followed by a bitwise OR between the read result and
 987   the value specified by AndData, and writes the result to the 32-bit PCI
 988   configuration register specified by Address. The value written to the PCI
 989   configuration register is returned. This function must guarantee that all PCI
 990   read and write operations are serialized. Extra left bits in both AndData and
 991   OrData are stripped.
 992
 993   If Address > 0x0FFFFFFF, then ASSERT().
 994   If Address is not aligned on a 32-bit boundary, then ASSERT().
 995   If the register specified by Address >= 0x100, then ASSERT().
 996   If StartBit is greater than 31, then ASSERT().
 997   If EndBit is greater than 31, then ASSERT().
 998   If EndBit is less than StartBit, then ASSERT().
 999   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1000   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1001
1002   @param  Address   PCI configuration register to write.
1003   @param  StartBit  The ordinal of the least significant bit in the bit field.
1004                     Range 0..31.
1005   @param  EndBit    The ordinal of the most significant bit in the bit field.
1006                     Range 0..31.
1007   @param  AndData   The value to AND with the PCI configuration register.
1008   @param  OrData    The value to OR with the result of the AND operation.
1009
1010   @return The value written back to the PCI configuration register.
1011
1012 **/
1013 UINT32
1014 EFIAPI
1015 PciCf8BitFieldAndThenOr32 (
1016   IN      UINTN                     Address,
1017   IN      UINTN                     StartBit,
1018   IN      UINTN                     EndBit,
1019   IN      UINT32                    AndData,
1020   IN      UINT32                    OrData
1021   );
1022
1023 /**
1024   Reads a range of PCI configuration registers into a caller supplied buffer.
1025
1026   Reads the range of PCI configuration registers specified by StartAddress and
1027   Size into the buffer specified by Buffer. This function only allows the PCI
1028   configuration registers from a single PCI function to be read. Size is
1029   returned. When possible 32-bit PCI configuration read cycles are used to read
1030   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1031   and 16-bit PCI configuration read cycles may be used at the beginning and the
1032   end of the range.
1033
1034   If StartAddress > 0x0FFFFFFF, then ASSERT().
1035   If the register specified by StartAddress >= 0x100, then ASSERT().
1036   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1037   If Size > 0 and Buffer is NULL, then ASSERT().
1038
1039   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1040                         Function and Register.
1041   @param  Size          Size in bytes of the transfer.
1042   @param  Buffer        Pointer to a buffer receiving the data read.
1043
1044   @return Size read from StartAddress.
1045
1046 **/
1047 UINTN
1048 EFIAPI
1049 PciCf8ReadBuffer (
1050   IN      UINTN                     StartAddress,
1051   IN      UINTN                     Size,
1052   OUT     VOID                      *Buffer
1053   );
1054
1055 /**
1056   Copies the data in a caller supplied buffer to a specified range of PCI
1057   configuration space.
1058
1059   Writes the range of PCI configuration registers specified by StartAddress and
1060   Size from the buffer specified by Buffer. This function only allows the PCI
1061   configuration registers from a single PCI function to be written. Size is
1062   returned. When possible 32-bit PCI configuration write cycles are used to
1063   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1064   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1065   and the end of the range.
1066
1067   If StartAddress > 0x0FFFFFFF, then ASSERT().
1068   If the register specified by StartAddress >= 0x100, then ASSERT().
1069   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1070   If Size > 0 and Buffer is NULL, then ASSERT().
1071
1072   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1073                         Function and Register.
1074   @param  Size          Size in bytes of the transfer.
1075   @param  Buffer        Pointer to a buffer containing the data to write.
1076
1077   @return Size written to StartAddress.
1078
1079 **/
1080 UINTN
1081 EFIAPI
1082 PciCf8WriteBuffer (
1083   IN      UINTN                     StartAddress,
1084   IN      UINTN                     Size,
1085   IN      VOID                      *Buffer
1086   );
1087
1088 #endif