MdePkg/Include/Library/PciCf8Lib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
   3
   4   This library is identical to the PCI Library, except the access method for performing PCI
   5   configuration cycles must be though I/O ports 0xCF8 and 0xCFC.  This library only allows
   6   access to PCI Segment #0.
   7
   8 Copyright (c) 2006 - 2008, Intel Corporation<BR>
   9 All rights reserved. This program and the accompanying materials
  10 are licensed and made available under the terms and conditions of the BSD License
  11 which accompanies this distribution.  The full text of the license may be found at
  12 http://opensource.org/licenses/bsd-license.php
  13
  14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  16
  17 **/
  18
  19 #ifndef __PCI_CF8_LIB_H__
  20 #define __PCI_CF8_LIB_H__
  21
  22
  23 /**
  24   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  25   address that can be passed to the PCI Library functions.
  26
  27   Computes an address that is compatible with the PCI Library functions. The
  28   unused upper bits of Bus, Device, Function and Register are stripped prior to
  29   the generation of the address.
  30
  31   @param  Bus       PCI Bus number. Range 0..255.
  32   @param  Device    PCI Device number. Range 0..31.
  33   @param  Function  PCI Function number. Range 0..7.
  34   @param  Register  PCI Register number. Range 0..255.
  35
  36   @return The encode PCI address.
  37
  38 **/
  39 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
  40   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  41
  42 /**
  43   Registers a PCI device so PCI configuration registers may be accessed after
  44   SetVirtualAddressMap().
  45
  46   Registers the PCI device specified by Address so all the PCI configuration registers
  47   associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
  48
  49   If Address > 0x0FFFFFFF, then ASSERT().
  50
  51   @param  Address Address that encodes the PCI Bus, Device, Function and
  52                   Register.
  53
  54   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  55   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  56                                    after ExitBootServices().
  57   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  58                                    at runtime could not be mapped.
  59   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  60                                    complete the registration.
  61
  62 **/
  63 RETURN_STATUS
  64 EFIAPI
  65 PciCf8RegisterForRuntimeAccess (
  66   IN UINTN  Address
  67   );
  68
  69 /**
  70   Reads an 8-bit PCI configuration register.
  71
  72   Reads and returns the 8-bit PCI configuration register specified by Address.
  73   This function must guarantee that all PCI read and write operations are
  74   serialized.
  75
  76   If Address > 0x0FFFFFFF, then ASSERT().
  77   If the register specified by Address >= 0x100, then ASSERT().
  78
  79   @param  Address Address that encodes the PCI Bus, Device, Function and
  80                   Register.
  81
  82   @return The read value from the PCI configuration register.
  83
  84 **/
  85 UINT8
  86 EFIAPI
  87 PciCf8Read8 (
  88   IN      UINTN                     Address
  89   );
  90
  91 /**
  92   Writes an 8-bit PCI configuration register.
  93
  94   Writes the 8-bit PCI configuration register specified by Address with the
  95   value specified by Value. Value is returned. This function must guarantee
  96   that all PCI read and write operations are serialized.
  97
  98   If Address > 0x0FFFFFFF, then ASSERT().
  99   If the register specified by Address >= 0x100, then ASSERT().
 100
 101   @param  Address Address that encodes the PCI Bus, Device, Function and
 102                   Register.
 103   @param  Value   The value to write.
 104
 105   @return The value written to the PCI configuration register.
 106
 107 **/
 108 UINT8
 109 EFIAPI
 110 PciCf8Write8 (
 111   IN      UINTN                     Address,
 112   IN      UINT8                     Value
 113   );
 114
 115 /**
 116   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
 117   an 8-bit value.
 118
 119   Reads the 8-bit PCI configuration register specified by Address, performs a
 120   bitwise inclusive OR between the read result and the value specified by
 121   OrData, and writes the result to the 8-bit PCI configuration register
 122   specified by Address. The value written to the PCI configuration register is
 123   returned. This function must guarantee that all PCI read and write operations
 124   are serialized.
 125
 126   If Address > 0x0FFFFFFF, then ASSERT().
 127   If the register specified by Address >= 0x100, then ASSERT().
 128
 129   @param  Address Address that encodes the PCI Bus, Device, Function and
 130                   Register.
 131   @param  OrData  The value to OR with the PCI configuration register.
 132
 133   @return The value written back to the PCI configuration register.
 134
 135 **/
 136 UINT8
 137 EFIAPI
 138 PciCf8Or8 (
 139   IN      UINTN                     Address,
 140   IN      UINT8                     OrData
 141   );
 142
 143 /**
 144   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 145   value.
 146
 147   Reads the 8-bit PCI configuration register specified by Address, performs a
 148   bitwise AND between the read result and the value specified by AndData, and
 149   writes the result to the 8-bit PCI configuration register specified by
 150   Address. The value written to the PCI configuration register is returned.
 151   This function must guarantee that all PCI read and write operations are
 152   serialized.
 153
 154   If Address > 0x0FFFFFFF, then ASSERT().
 155   If the register specified by Address >= 0x100, then ASSERT().
 156
 157   @param  Address Address that encodes the PCI Bus, Device, Function and
 158                   Register.
 159   @param  AndData The value to AND with the PCI configuration register.
 160
 161   @return The value written back to the PCI configuration register.
 162
 163 **/
 164 UINT8
 165 EFIAPI
 166 PciCf8And8 (
 167   IN      UINTN                     Address,
 168   IN      UINT8                     AndData
 169   );
 170
 171 /**
 172   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 173   value, followed a  bitwise inclusive OR with another 8-bit value.
 174
 175   Reads the 8-bit PCI configuration register specified by Address, performs a
 176   bitwise AND between the read result and the value specified by AndData,
 177   performs a bitwise inclusive OR between the result of the AND operation and
 178   the value specified by OrData, and writes the result to the 8-bit PCI
 179   configuration register specified by Address. The value written to the PCI
 180   configuration register is returned. This function must guarantee that all PCI
 181   read and write operations are serialized.
 182
 183   If Address > 0x0FFFFFFF, then ASSERT().
 184   If the register specified by Address >= 0x100, then ASSERT().
 185
 186   @param  Address Address that encodes the PCI Bus, Device, Function and
 187                   Register.
 188   @param  AndData The value to AND with the PCI configuration register.
 189   @param  OrData  The value to OR with the result of the AND operation.
 190
 191   @return The value written back to the PCI configuration register.
 192
 193 **/
 194 UINT8
 195 EFIAPI
 196 PciCf8AndThenOr8 (
 197   IN      UINTN                     Address,
 198   IN      UINT8                     AndData,
 199   IN      UINT8                     OrData
 200   );
 201
 202 /**
 203   Reads a bit field of a PCI configuration register.
 204
 205   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 206   specified by the StartBit and the EndBit. The value of the bit field is
 207   returned.
 208
 209   If Address > 0x0FFFFFFF, then ASSERT().
 210   If the register specified by Address >= 0x100, then ASSERT().
 211   If StartBit is greater than 7, then ASSERT().
 212   If EndBit is greater than 7, then ASSERT().
 213   If EndBit is less than StartBit, then ASSERT().
 214
 215   @param  Address   PCI configuration register to read.
 216   @param  StartBit  The ordinal of the least significant bit in the bit field.
 217                     Range 0..7.
 218   @param  EndBit    The ordinal of the most significant bit in the bit field.
 219                     Range 0..7.
 220
 221   @return The value of the bit field read from the PCI configuration register.
 222
 223 **/
 224 UINT8
 225 EFIAPI
 226 PciCf8BitFieldRead8 (
 227   IN      UINTN                     Address,
 228   IN      UINTN                     StartBit,
 229   IN      UINTN                     EndBit
 230   );
 231
 232 /**
 233   Writes a bit field to a PCI configuration register.
 234
 235   Writes Value to the bit field of the PCI configuration register. The bit
 236   field is specified by the StartBit and the EndBit. All other bits in the
 237   destination PCI configuration register are preserved. The new value of the
 238   8-bit register is returned.
 239
 240   If Address > 0x0FFFFFFF, then ASSERT().
 241   If the register specified by Address >= 0x100, then ASSERT().
 242   If StartBit is greater than 7, then ASSERT().
 243   If EndBit is greater than 7, then ASSERT().
 244   If EndBit is less than StartBit, then ASSERT().
 245
 246   @param  Address   PCI configuration register to write.
 247   @param  StartBit  The ordinal of the least significant bit in the bit field.
 248                     Range 0..7.
 249   @param  EndBit    The ordinal of the most significant bit in the bit field.
 250                     Range 0..7.
 251   @param  Value     New value of the bit field.
 252
 253   @return The value written back to the PCI configuration register.
 254
 255 **/
 256 UINT8
 257 EFIAPI
 258 PciCf8BitFieldWrite8 (
 259   IN      UINTN                     Address,
 260   IN      UINTN                     StartBit,
 261   IN      UINTN                     EndBit,
 262   IN      UINT8                     Value
 263   );
 264
 265 /**
 266   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 267   writes the result back to the bit field in the 8-bit port.
 268
 269   Reads the 8-bit PCI configuration register specified by Address, performs a
 270   bitwise inclusive OR between the read result and the value specified by
 271   OrData, and writes the result to the 8-bit PCI configuration register
 272   specified by Address. The value written to the PCI configuration register is
 273   returned. This function must guarantee that all PCI read and write operations
 274   are serialized. Extra left bits in OrData are stripped.
 275
 276   If Address > 0x0FFFFFFF, then ASSERT().
 277   If the register specified by Address >= 0x100, then ASSERT().
 278   If StartBit is greater than 7, then ASSERT().
 279   If EndBit is greater than 7, then ASSERT().
 280   If EndBit is less than StartBit, then ASSERT().
 281
 282   @param  Address   PCI configuration register to write.
 283   @param  StartBit  The ordinal of the least significant bit in the bit field.
 284                     Range 0..7.
 285   @param  EndBit    The ordinal of the most significant bit in the bit field.
 286                     Range 0..7.
 287   @param  OrData    The value to OR with the PCI configuration register.
 288
 289   @return The value written back to the PCI configuration register.
 290
 291 **/
 292 UINT8
 293 EFIAPI
 294 PciCf8BitFieldOr8 (
 295   IN      UINTN                     Address,
 296   IN      UINTN                     StartBit,
 297   IN      UINTN                     EndBit,
 298   IN      UINT8                     OrData
 299   );
 300
 301 /**
 302   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 303   AND, and writes the result back to the bit field in the 8-bit register.
 304
 305   Reads the 8-bit PCI configuration register specified by Address, performs a
 306   bitwise AND between the read result and the value specified by AndData, and
 307   writes the result to the 8-bit PCI configuration register specified by
 308   Address. The value written to the PCI configuration register is returned.
 309   This function must guarantee that all PCI read and write operations are
 310   serialized. Extra left bits in AndData are stripped.
 311
 312   If Address > 0x0FFFFFFF, then ASSERT().
 313   If the register specified by Address >= 0x100, then ASSERT().
 314   If StartBit is greater than 7, then ASSERT().
 315   If EndBit is greater than 7, then ASSERT().
 316   If EndBit is less than StartBit, then ASSERT().
 317
 318   @param  Address   PCI configuration register to write.
 319   @param  StartBit  The ordinal of the least significant bit in the bit field.
 320                     Range 0..7.
 321   @param  EndBit    The ordinal of the most significant bit in the bit field.
 322                     Range 0..7.
 323   @param  AndData   The value to AND with the PCI configuration register.
 324
 325   @return The value written back to the PCI configuration register.
 326
 327 **/
 328 UINT8
 329 EFIAPI
 330 PciCf8BitFieldAnd8 (
 331   IN      UINTN                     Address,
 332   IN      UINTN                     StartBit,
 333   IN      UINTN                     EndBit,
 334   IN      UINT8                     AndData
 335   );
 336
 337 /**
 338   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 339   bitwise inclusive OR, and writes the result back to the bit field in the
 340   8-bit port.
 341
 342   Reads the 8-bit PCI configuration register specified by Address, performs a
 343   bitwise AND followed by a bitwise inclusive OR between the read result and
 344   the value specified by AndData, and writes the result to the 8-bit PCI
 345   configuration register specified by Address. The value written to the PCI
 346   configuration register is returned. This function must guarantee that all PCI
 347   read and write operations are serialized. Extra left bits in both AndData and
 348   OrData are stripped.
 349
 350   If Address > 0x0FFFFFFF, then ASSERT().
 351   If the register specified by Address >= 0x100, then ASSERT().
 352   If StartBit is greater than 7, then ASSERT().
 353   If EndBit is greater than 7, then ASSERT().
 354   If EndBit is less than StartBit, then ASSERT().
 355
 356   @param  Address   PCI configuration register to write.
 357   @param  StartBit  The ordinal of the least significant bit in the bit field.
 358                     Range 0..7.
 359   @param  EndBit    The ordinal of the most significant bit in the bit field.
 360                     Range 0..7.
 361   @param  AndData   The value to AND with the PCI configuration register.
 362   @param  OrData    The value to OR with the result of the AND operation.
 363
 364   @return The value written back to the PCI configuration register.
 365
 366 **/
 367 UINT8
 368 EFIAPI
 369 PciCf8BitFieldAndThenOr8 (
 370   IN      UINTN                     Address,
 371   IN      UINTN                     StartBit,
 372   IN      UINTN                     EndBit,
 373   IN      UINT8                     AndData,
 374   IN      UINT8                     OrData
 375   );
 376
 377 /**
 378   Reads a 16-bit PCI configuration register.
 379
 380   Reads and returns the 16-bit PCI configuration register specified by Address.
 381   This function must guarantee that all PCI read and write operations are
 382   serialized.
 383
 384   If Address > 0x0FFFFFFF, then ASSERT().
 385   If Address is not aligned on a 16-bit boundary, then ASSERT().
 386   If the register specified by Address >= 0x100, then ASSERT().
 387
 388   @param  Address Address that encodes the PCI Bus, Device, Function and
 389                   Register.
 390
 391   @return The read value from the PCI configuration register.
 392
 393 **/
 394 UINT16
 395 EFIAPI
 396 PciCf8Read16 (
 397   IN      UINTN                     Address
 398   );
 399
 400 /**
 401   Writes a 16-bit PCI configuration register.
 402
 403   Writes the 16-bit PCI configuration register specified by Address with the
 404   value specified by Value. Value is returned. This function must guarantee
 405   that all PCI read and write operations are serialized.
 406
 407   If Address > 0x0FFFFFFF, then ASSERT().
 408   If Address is not aligned on a 16-bit boundary, then ASSERT().
 409   If the register specified by Address >= 0x100, then ASSERT().
 410
 411   @param  Address Address that encodes the PCI Bus, Device, Function and
 412                   Register.
 413   @param  Value   The value to write.
 414
 415   @return The value written to the PCI configuration register.
 416
 417 **/
 418 UINT16
 419 EFIAPI
 420 PciCf8Write16 (
 421   IN      UINTN                     Address,
 422   IN      UINT16                    Value
 423   );
 424
 425 /**
 426   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 427   a 16-bit value.
 428
 429   Reads the 16-bit PCI configuration register specified by Address, performs a
 430   bitwise inclusive OR between the read result and the value specified by
 431   OrData, and writes the result to the 16-bit PCI configuration register
 432   specified by Address. The value written to the PCI configuration register is
 433   returned. This function must guarantee that all PCI read and write operations
 434   are serialized.
 435
 436   If Address > 0x0FFFFFFF, then ASSERT().
 437   If Address is not aligned on a 16-bit boundary, then ASSERT().
 438   If the register specified by Address >= 0x100, then ASSERT().
 439
 440   @param  Address Address that encodes the PCI Bus, Device, Function and
 441                   Register.
 442   @param  OrData  The value to OR with the PCI configuration register.
 443
 444   @return The value written back to the PCI configuration register.
 445
 446 **/
 447 UINT16
 448 EFIAPI
 449 PciCf8Or16 (
 450   IN      UINTN                     Address,
 451   IN      UINT16                    OrData
 452   );
 453
 454 /**
 455   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 456   value.
 457
 458   Reads the 16-bit PCI configuration register specified by Address, performs a
 459   bitwise AND between the read result and the value specified by AndData, and
 460   writes the result to the 16-bit PCI configuration register specified by
 461   Address. The value written to the PCI configuration register is returned.
 462   This function must guarantee that all PCI read and write operations are
 463   serialized.
 464
 465   If Address > 0x0FFFFFFF, then ASSERT().
 466   If Address is not aligned on a 16-bit boundary, then ASSERT().
 467   If the register specified by Address >= 0x100, then ASSERT().
 468
 469   @param  Address Address that encodes the PCI Bus, Device, Function and
 470                   Register.
 471   @param  AndData The value to AND with the PCI configuration register.
 472
 473   @return The value written back to the PCI configuration register.
 474
 475 **/
 476 UINT16
 477 EFIAPI
 478 PciCf8And16 (
 479   IN      UINTN                     Address,
 480   IN      UINT16                    AndData
 481   );
 482
 483 /**
 484   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 485   value, followed a  bitwise inclusive OR with another 16-bit value.
 486
 487   Reads the 16-bit PCI configuration register specified by Address, performs a
 488   bitwise AND between the read result and the value specified by AndData,
 489   performs a bitwise inclusive OR between the result of the AND operation and
 490   the value specified by OrData, and writes the result to the 16-bit PCI
 491   configuration register specified by Address. The value written to the PCI
 492   configuration register is returned. This function must guarantee that all PCI
 493   read and write operations are serialized.
 494
 495   If Address > 0x0FFFFFFF, then ASSERT().
 496   If Address is not aligned on a 16-bit boundary, then ASSERT().
 497   If the register specified by Address >= 0x100, then ASSERT().
 498
 499   @param  Address Address that encodes the PCI Bus, Device, Function and
 500                   Register.
 501   @param  AndData The value to AND with the PCI configuration register.
 502   @param  OrData  The value to OR with the result of the AND operation.
 503
 504   @return The value written back to the PCI configuration register.
 505
 506 **/
 507 UINT16
 508 EFIAPI
 509 PciCf8AndThenOr16 (
 510   IN      UINTN                     Address,
 511   IN      UINT16                    AndData,
 512   IN      UINT16                    OrData
 513   );
 514
 515 /**
 516   Reads a bit field of a PCI configuration register.
 517
 518   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 519   specified by the StartBit and the EndBit. The value of the bit field is
 520   returned.
 521
 522   If Address > 0x0FFFFFFF, then ASSERT().
 523   If Address is not aligned on a 16-bit boundary, then ASSERT().
 524   If the register specified by Address >= 0x100, then ASSERT().
 525   If StartBit is greater than 15, then ASSERT().
 526   If EndBit is greater than 15, then ASSERT().
 527   If EndBit is less than StartBit, then ASSERT().
 528
 529   @param  Address   PCI configuration register to read.
 530   @param  StartBit  The ordinal of the least significant bit in the bit field.
 531                     Range 0..15.
 532   @param  EndBit    The ordinal of the most significant bit in the bit field.
 533                     Range 0..15.
 534
 535   @return The value of the bit field read from the PCI configuration register.
 536
 537 **/
 538 UINT16
 539 EFIAPI
 540 PciCf8BitFieldRead16 (
 541   IN      UINTN                     Address,
 542   IN      UINTN                     StartBit,
 543   IN      UINTN                     EndBit
 544   );
 545
 546 /**
 547   Writes a bit field to a PCI configuration register.
 548
 549   Writes Value to the bit field of the PCI configuration register. The bit
 550   field is specified by the StartBit and the EndBit. All other bits in the
 551   destination PCI configuration register are preserved. The new value of the
 552   16-bit register is returned.
 553
 554   If Address > 0x0FFFFFFF, then ASSERT().
 555   If Address is not aligned on a 16-bit boundary, then ASSERT().
 556   If the register specified by Address >= 0x100, then ASSERT().
 557   If StartBit is greater than 15, then ASSERT().
 558   If EndBit is greater than 15, then ASSERT().
 559   If EndBit is less than StartBit, then ASSERT().
 560
 561   @param  Address   PCI configuration register to write.
 562   @param  StartBit  The ordinal of the least significant bit in the bit field.
 563                     Range 0..15.
 564   @param  EndBit    The ordinal of the most significant bit in the bit field.
 565                     Range 0..15.
 566   @param  Value     New value of the bit field.
 567
 568   @return The value written back to the PCI configuration register.
 569
 570 **/
 571 UINT16
 572 EFIAPI
 573 PciCf8BitFieldWrite16 (
 574   IN      UINTN                     Address,
 575   IN      UINTN                     StartBit,
 576   IN      UINTN                     EndBit,
 577   IN      UINT16                    Value
 578   );
 579
 580 /**
 581   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 582   writes the result back to the bit field in the 16-bit port.
 583
 584   Reads the 16-bit PCI configuration register specified by Address, performs a
 585   bitwise inclusive OR between the read result and the value specified by
 586   OrData, and writes the result to the 16-bit PCI configuration register
 587   specified by Address. The value written to the PCI configuration register is
 588   returned. This function must guarantee that all PCI read and write operations
 589   are serialized. Extra left bits in OrData are stripped.
 590
 591   If Address > 0x0FFFFFFF, then ASSERT().
 592   If Address is not aligned on a 16-bit boundary, then ASSERT().
 593   If the register specified by Address >= 0x100, then ASSERT().
 594   If StartBit is greater than 15, then ASSERT().
 595   If EndBit is greater than 15, then ASSERT().
 596   If EndBit is less than StartBit, then ASSERT().
 597
 598   @param  Address   PCI configuration register to write.
 599   @param  StartBit  The ordinal of the least significant bit in the bit field.
 600                     Range 0..15.
 601   @param  EndBit    The ordinal of the most significant bit in the bit field.
 602                     Range 0..15.
 603   @param  OrData    The value to OR with the PCI configuration register.
 604
 605   @return The value written back to the PCI configuration register.
 606
 607 **/
 608 UINT16
 609 EFIAPI
 610 PciCf8BitFieldOr16 (
 611   IN      UINTN                     Address,
 612   IN      UINTN                     StartBit,
 613   IN      UINTN                     EndBit,
 614   IN      UINT16                    OrData
 615   );
 616
 617 /**
 618   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 619   AND, and writes the result back to the bit field in the 16-bit register.
 620
 621   Reads the 16-bit PCI configuration register specified by Address, performs a
 622   bitwise AND between the read result and the value specified by AndData, and
 623   writes the result to the 16-bit PCI configuration register specified by
 624   Address. The value written to the PCI configuration register is returned.
 625   This function must guarantee that all PCI read and write operations are
 626   serialized. Extra left bits in AndData are stripped.
 627
 628   If Address > 0x0FFFFFFF, then ASSERT().
 629   If Address is not aligned on a 16-bit boundary, then ASSERT().
 630   If the register specified by Address >= 0x100, then ASSERT().
 631   If StartBit is greater than 15, then ASSERT().
 632   If EndBit is greater than 15, then ASSERT().
 633   If EndBit is less than StartBit, then ASSERT().
 634
 635   @param  Address   PCI configuration register to write.
 636   @param  StartBit  The ordinal of the least significant bit in the bit field.
 637                     Range 0..15.
 638   @param  EndBit    The ordinal of the most significant bit in the bit field.
 639                     Range 0..15.
 640   @param  AndData   The value to AND with the PCI configuration register.
 641
 642   @return The value written back to the PCI configuration register.
 643
 644 **/
 645 UINT16
 646 EFIAPI
 647 PciCf8BitFieldAnd16 (
 648   IN      UINTN                     Address,
 649   IN      UINTN                     StartBit,
 650   IN      UINTN                     EndBit,
 651   IN      UINT16                    AndData
 652   );
 653
 654 /**
 655   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 656   bitwise inclusive OR, and writes the result back to the bit field in the
 657   16-bit port.
 658
 659   Reads the 16-bit PCI configuration register specified by Address, performs a
 660   bitwise AND followed by a bitwise inclusive OR between the read result and
 661   the value specified by AndData, and writes the result to the 16-bit PCI
 662   configuration register specified by Address. The value written to the PCI
 663   configuration register is returned. This function must guarantee that all PCI
 664   read and write operations are serialized. Extra left bits in both AndData and
 665   OrData are stripped.
 666
 667   If Address > 0x0FFFFFFF, then ASSERT().
 668   If Address is not aligned on a 16-bit boundary, then ASSERT().
 669   If the register specified by Address >= 0x100, then ASSERT().
 670   If StartBit is greater than 15, then ASSERT().
 671   If EndBit is greater than 15, then ASSERT().
 672   If EndBit is less than StartBit, then ASSERT().
 673
 674   @param  Address   PCI configuration register to write.
 675   @param  StartBit  The ordinal of the least significant bit in the bit field.
 676                     Range 0..15.
 677   @param  EndBit    The ordinal of the most significant bit in the bit field.
 678                     Range 0..15.
 679   @param  AndData   The value to AND with the PCI configuration register.
 680   @param  OrData    The value to OR with the result of the AND operation.
 681
 682   @return The value written back to the PCI configuration register.
 683
 684 **/
 685 UINT16
 686 EFIAPI
 687 PciCf8BitFieldAndThenOr16 (
 688   IN      UINTN                     Address,
 689   IN      UINTN                     StartBit,
 690   IN      UINTN                     EndBit,
 691   IN      UINT16                    AndData,
 692   IN      UINT16                    OrData
 693   );
 694
 695 /**
 696   Reads a 32-bit PCI configuration register.
 697
 698   Reads and returns the 32-bit PCI configuration register specified by Address.
 699   This function must guarantee that all PCI read and write operations are
 700   serialized.
 701
 702   If Address > 0x0FFFFFFF, then ASSERT().
 703   If Address is not aligned on a 32-bit boundary, then ASSERT().
 704   If the register specified by Address >= 0x100, then ASSERT().
 705
 706   @param  Address Address that encodes the PCI Bus, Device, Function and
 707                   Register.
 708
 709   @return The read value from the PCI configuration register.
 710
 711 **/
 712 UINT32
 713 EFIAPI
 714 PciCf8Read32 (
 715   IN      UINTN                     Address
 716   );
 717
 718 /**
 719   Writes a 32-bit PCI configuration register.
 720
 721   Writes the 32-bit PCI configuration register specified by Address with the
 722   value specified by Value. Value is returned. This function must guarantee
 723   that all PCI read and write operations are serialized.
 724
 725   If Address > 0x0FFFFFFF, then ASSERT().
 726   If Address is not aligned on a 32-bit boundary, then ASSERT().
 727   If the register specified by Address >= 0x100, then ASSERT().
 728
 729   @param  Address Address that encodes the PCI Bus, Device, Function and
 730                   Register.
 731   @param  Value   The value to write.
 732
 733   @return The value written to the PCI configuration register.
 734
 735 **/
 736 UINT32
 737 EFIAPI
 738 PciCf8Write32 (
 739   IN      UINTN                     Address,
 740   IN      UINT32                    Value
 741   );
 742
 743 /**
 744   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 745   a 32-bit value.
 746
 747   Reads the 32-bit PCI configuration register specified by Address, performs a
 748   bitwise inclusive OR between the read result and the value specified by
 749   OrData, and writes the result to the 32-bit PCI configuration register
 750   specified by Address. The value written to the PCI configuration register is
 751   returned. This function must guarantee that all PCI read and write operations
 752   are serialized.
 753
 754   If Address > 0x0FFFFFFF, then ASSERT().
 755   If Address is not aligned on a 32-bit boundary, then ASSERT().
 756   If the register specified by Address >= 0x100, then ASSERT().
 757
 758   @param  Address Address that encodes the PCI Bus, Device, Function and
 759                   Register.
 760   @param  OrData  The value to OR with the PCI configuration register.
 761
 762   @return The value written back to the PCI configuration register.
 763
 764 **/
 765 UINT32
 766 EFIAPI
 767 PciCf8Or32 (
 768   IN      UINTN                     Address,
 769   IN      UINT32                    OrData
 770   );
 771
 772 /**
 773   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 774   value.
 775
 776   Reads the 32-bit PCI configuration register specified by Address, performs a
 777   bitwise AND between the read result and the value specified by AndData, and
 778   writes the result to the 32-bit PCI configuration register specified by
 779   Address. The value written to the PCI configuration register is returned.
 780   This function must guarantee that all PCI read and write operations are
 781   serialized.
 782
 783   If Address > 0x0FFFFFFF, then ASSERT().
 784   If Address is not aligned on a 32-bit boundary, then ASSERT().
 785   If the register specified by Address >= 0x100, then ASSERT().
 786
 787   @param  Address Address that encodes the PCI Bus, Device, Function and
 788                   Register.
 789   @param  AndData The value to AND with the PCI configuration register.
 790
 791   @return The value written back to the PCI configuration register.
 792
 793 **/
 794 UINT32
 795 EFIAPI
 796 PciCf8And32 (
 797   IN      UINTN                     Address,
 798   IN      UINT32                    AndData
 799   );
 800
 801 /**
 802   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 803   value, followed a  bitwise inclusive OR with another 32-bit value.
 804
 805   Reads the 32-bit PCI configuration register specified by Address, performs a
 806   bitwise AND between the read result and the value specified by AndData,
 807   performs a bitwise inclusive OR between the result of the AND operation and
 808   the value specified by OrData, and writes the result to the 32-bit PCI
 809   configuration register specified by Address. The value written to the PCI
 810   configuration register is returned. This function must guarantee that all PCI
 811   read and write operations are serialized.
 812
 813   If Address > 0x0FFFFFFF, then ASSERT().
 814   If Address is not aligned on a 32-bit boundary, then ASSERT().
 815   If the register specified by Address >= 0x100, then ASSERT().
 816
 817   @param  Address Address that encodes the PCI Bus, Device, Function and
 818                   Register.
 819   @param  AndData The value to AND with the PCI configuration register.
 820   @param  OrData  The value to OR with the result of the AND operation.
 821
 822   @return The value written back to the PCI configuration register.
 823
 824 **/
 825 UINT32
 826 EFIAPI
 827 PciCf8AndThenOr32 (
 828   IN      UINTN                     Address,
 829   IN      UINT32                    AndData,
 830   IN      UINT32                    OrData
 831   );
 832
 833 /**
 834   Reads a bit field of a PCI configuration register.
 835
 836   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 837   specified by the StartBit and the EndBit. The value of the bit field is
 838   returned.
 839
 840   If Address > 0x0FFFFFFF, then ASSERT().
 841   If Address is not aligned on a 32-bit boundary, then ASSERT().
 842   If the register specified by Address >= 0x100, then ASSERT().
 843   If StartBit is greater than 31, then ASSERT().
 844   If EndBit is greater than 31, then ASSERT().
 845   If EndBit is less than StartBit, then ASSERT().
 846
 847   @param  Address   PCI configuration register to read.
 848   @param  StartBit  The ordinal of the least significant bit in the bit field.
 849                     Range 0..31.
 850   @param  EndBit    The ordinal of the most significant bit in the bit field.
 851                     Range 0..31.
 852
 853   @return The value of the bit field read from the PCI configuration register.
 854
 855 **/
 856 UINT32
 857 EFIAPI
 858 PciCf8BitFieldRead32 (
 859   IN      UINTN                     Address,
 860   IN      UINTN                     StartBit,
 861   IN      UINTN                     EndBit
 862   );
 863
 864 /**
 865   Writes a bit field to a PCI configuration register.
 866
 867   Writes Value to the bit field of the PCI configuration register. The bit
 868   field is specified by the StartBit and the EndBit. All other bits in the
 869   destination PCI configuration register are preserved. The new value of the
 870   32-bit register is returned.
 871
 872   If Address > 0x0FFFFFFF, then ASSERT().
 873   If Address is not aligned on a 32-bit boundary, then ASSERT().
 874   If the register specified by Address >= 0x100, then ASSERT().
 875   If StartBit is greater than 31, then ASSERT().
 876   If EndBit is greater than 31, then ASSERT().
 877   If EndBit is less than StartBit, then ASSERT().
 878
 879   @param  Address   PCI configuration register to write.
 880   @param  StartBit  The ordinal of the least significant bit in the bit field.
 881                     Range 0..31.
 882   @param  EndBit    The ordinal of the most significant bit in the bit field.
 883                     Range 0..31.
 884   @param  Value     New value of the bit field.
 885
 886   @return The value written back to the PCI configuration register.
 887
 888 **/
 889 UINT32
 890 EFIAPI
 891 PciCf8BitFieldWrite32 (
 892   IN      UINTN                     Address,
 893   IN      UINTN                     StartBit,
 894   IN      UINTN                     EndBit,
 895   IN      UINT32                    Value
 896   );
 897
 898 /**
 899   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 900   writes the result back to the bit field in the 32-bit port.
 901
 902   Reads the 32-bit PCI configuration register specified by Address, performs a
 903   bitwise inclusive OR between the read result and the value specified by
 904   OrData, and writes the result to the 32-bit PCI configuration register
 905   specified by Address. The value written to the PCI configuration register is
 906   returned. This function must guarantee that all PCI read and write operations
 907   are serialized. Extra left bits in OrData are stripped.
 908
 909   If Address > 0x0FFFFFFF, then ASSERT().
 910   If Address is not aligned on a 32-bit boundary, then ASSERT().
 911   If the register specified by Address >= 0x100, then ASSERT().
 912   If StartBit is greater than 31, then ASSERT().
 913   If EndBit is greater than 31, then ASSERT().
 914   If EndBit is less than StartBit, then ASSERT().
 915
 916   @param  Address   PCI configuration register to write.
 917   @param  StartBit  The ordinal of the least significant bit in the bit field.
 918                     Range 0..31.
 919   @param  EndBit    The ordinal of the most significant bit in the bit field.
 920                     Range 0..31.
 921   @param  OrData    The value to OR with the PCI configuration register.
 922
 923   @return The value written back to the PCI configuration register.
 924
 925 **/
 926 UINT32
 927 EFIAPI
 928 PciCf8BitFieldOr32 (
 929   IN      UINTN                     Address,
 930   IN      UINTN                     StartBit,
 931   IN      UINTN                     EndBit,
 932   IN      UINT32                    OrData
 933   );
 934
 935 /**
 936   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 937   AND, and writes the result back to the bit field in the 32-bit register.
 938
 939   Reads the 32-bit PCI configuration register specified by Address, performs a
 940   bitwise AND between the read result and the value specified by AndData, and
 941   writes the result to the 32-bit PCI configuration register specified by
 942   Address. The value written to the PCI configuration register is returned.
 943   This function must guarantee that all PCI read and write operations are
 944   serialized. Extra left bits in AndData are stripped.
 945
 946   If Address > 0x0FFFFFFF, then ASSERT().
 947   If Address is not aligned on a 32-bit boundary, then ASSERT().
 948   If the register specified by Address >= 0x100, then ASSERT().
 949   If StartBit is greater than 31, then ASSERT().
 950   If EndBit is greater than 31, then ASSERT().
 951   If EndBit is less than StartBit, then ASSERT().
 952
 953   @param  Address   PCI configuration register to write.
 954   @param  StartBit  The ordinal of the least significant bit in the bit field.
 955                     Range 0..31.
 956   @param  EndBit    The ordinal of the most significant bit in the bit field.
 957                     Range 0..31.
 958   @param  AndData   The value to AND with the PCI configuration register.
 959
 960   @return The value written back to the PCI configuration register.
 961
 962 **/
 963 UINT32
 964 EFIAPI
 965 PciCf8BitFieldAnd32 (
 966   IN      UINTN                     Address,
 967   IN      UINTN                     StartBit,
 968   IN      UINTN                     EndBit,
 969   IN      UINT32                    AndData
 970   );
 971
 972 /**
 973   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 974   bitwise inclusive OR, and writes the result back to the bit field in the
 975   32-bit port.
 976
 977   Reads the 32-bit PCI configuration register specified by Address, performs a
 978   bitwise AND followed by a bitwise inclusive OR between the read result and
 979   the value specified by AndData, and writes the result to the 32-bit PCI
 980   configuration register specified by Address. The value written to the PCI
 981   configuration register is returned. This function must guarantee that all PCI
 982   read and write operations are serialized. Extra left bits in both AndData and
 983   OrData are stripped.
 984
 985   If Address > 0x0FFFFFFF, then ASSERT().
 986   If Address is not aligned on a 32-bit boundary, then ASSERT().
 987   If the register specified by Address >= 0x100, then ASSERT().
 988   If StartBit is greater than 31, then ASSERT().
 989   If EndBit is greater than 31, then ASSERT().
 990   If EndBit is less than StartBit, then ASSERT().
 991
 992   @param  Address   PCI configuration register to write.
 993   @param  StartBit  The ordinal of the least significant bit in the bit field.
 994                     Range 0..31.
 995   @param  EndBit    The ordinal of the most significant bit in the bit field.
 996                     Range 0..31.
 997   @param  AndData   The value to AND with the PCI configuration register.
 998   @param  OrData    The value to OR with the result of the AND operation.
 999
1000   @return The value written back to the PCI configuration register.
1001
1002 **/
1003 UINT32
1004 EFIAPI
1005 PciCf8BitFieldAndThenOr32 (
1006   IN      UINTN                     Address,
1007   IN      UINTN                     StartBit,
1008   IN      UINTN                     EndBit,
1009   IN      UINT32                    AndData,
1010   IN      UINT32                    OrData
1011   );
1012
1013 /**
1014   Reads a range of PCI configuration registers into a caller supplied buffer.
1015
1016   Reads the range of PCI configuration registers specified by StartAddress and
1017   Size into the buffer specified by Buffer. This function only allows the PCI
1018   configuration registers from a single PCI function to be read. Size is
1019   returned. When possible 32-bit PCI configuration read cycles are used to read
1020   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1021   and 16-bit PCI configuration read cycles may be used at the beginning and the
1022   end of the range.
1023
1024   If StartAddress > 0x0FFFFFFF, then ASSERT().
1025   If the register specified by StartAddress >= 0x100, then ASSERT().
1026   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1027   If Size > 0 and Buffer is NULL, then ASSERT().
1028
1029   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1030                         Function and Register.
1031   @param  Size          Size in bytes of the transfer.
1032   @param  Buffer        Pointer to a buffer receiving the data read.
1033
1034   @return Size read from StartAddress.
1035
1036 **/
1037 UINTN
1038 EFIAPI
1039 PciCf8ReadBuffer (
1040   IN      UINTN                     StartAddress,
1041   IN      UINTN                     Size,
1042   OUT     VOID                      *Buffer
1043   );
1044
1045 /**
1046   Copies the data in a caller supplied buffer to a specified range of PCI
1047   configuration space.
1048
1049   Writes the range of PCI configuration registers specified by StartAddress and
1050   Size from the buffer specified by Buffer. This function only allows the PCI
1051   configuration registers from a single PCI function to be written. Size is
1052   returned. When possible 32-bit PCI configuration write cycles are used to
1053   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1054   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1055   and the end of the range.
1056
1057   If StartAddress > 0x0FFFFFFF, then ASSERT().
1058   If the register specified by StartAddress >= 0x100, then ASSERT().
1059   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1060   If Size > 0 and Buffer is NULL, then ASSERT().
1061
1062   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1063                         Function and Register.
1064   @param  Size          Size in bytes of the transfer.
1065   @param  Buffer        Pointer to a buffer containing the data to write.
1066
1067   @return Size written to StartAddress.
1068
1069 **/
1070 UINTN
1071 EFIAPI
1072 PciCf8WriteBuffer (
1073   IN      UINTN                     StartAddress,
1074   IN      UINTN                     Size,
1075   IN      VOID                      *Buffer
1076   );
1077
1078 #endif