MdePkg/Include/Library/PciCf8Lib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
   3
   4   This library is identical to the PCI Library, except the access method for performing PCI
   5   configuration cycles must be though I/O ports 0xCF8 and 0xCFC.  This library only allows
   6   access to PCI Segment #0.
   7
   8 Copyright (c) 2006 - 2008, Intel Corporation
   9 All rights reserved. This program and the accompanying materials
  10 are licensed and made available under the terms and conditions of the BSD License
  11 which accompanies this distribution.  The full text of the license may be found at
  12 http://opensource.org/licenses/bsd-license.php
  13
  14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  16
  17 **/
  18
  19 #ifndef __PCI_CF8_LIB_H__
  20 #define __PCI_CF8_LIB_H__
  21
  22
  23 /**
  24   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  25   address that can be passed to the PCI Library functions.
  26
  27   Computes an address that is compatible with the PCI Library functions. The
  28   unused upper bits of Bus, Device, Function and Register are stripped prior to
  29   the generation of the address.
  30
  31   @param  Bus       PCI Bus number. Range 0..255.
  32   @param  Device    PCI Device number. Range 0..31.
  33   @param  Function  PCI Function number. Range 0..7.
  34   @param  Register  PCI Register number. Range 0..255.
  35
  36   @return The encode PCI address.
  37
  38 **/
  39 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
  40   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  41
  42 /**
  43   Register a PCI device so PCI configuration registers may be accessed after
  44   SetVirtualAddressMap().
  45
  46   If Address > 0x0FFFFFFF, then ASSERT().
  47
  48   @param  Address Address that encodes the PCI Bus, Device, Function and
  49                   Register.
  50
  51   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  52   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  53                                    after ExitBootServices().
  54   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  55                                    at runtime could not be mapped.
  56   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  57                                    complete the registration.
  58
  59 **/
  60 RETURN_STATUS
  61 EFIAPI
  62 PciCf8RegisterForRuntimeAccess (
  63   IN UINTN  Address
  64   );
  65
  66 /**
  67   Reads an 8-bit PCI configuration register.
  68
  69   Reads and returns the 8-bit PCI configuration register specified by Address.
  70   This function must guarantee that all PCI read and write operations are
  71   serialized.
  72
  73   If Address > 0x0FFFFFFF, then ASSERT().
  74   If the register specified by Address >= 0x100, then ASSERT().
  75
  76   @param  Address Address that encodes the PCI Bus, Device, Function and
  77                   Register.
  78
  79   @return The read value from the PCI configuration register.
  80
  81 **/
  82 UINT8
  83 EFIAPI
  84 PciCf8Read8 (
  85   IN      UINTN                     Address
  86   );
  87
  88 /**
  89   Writes an 8-bit PCI configuration register.
  90
  91   Writes the 8-bit PCI configuration register specified by Address with the
  92   value specified by Value. Value is returned. This function must guarantee
  93   that all PCI read and write operations are serialized.
  94
  95   If Address > 0x0FFFFFFF, then ASSERT().
  96   If the register specified by Address >= 0x100, then ASSERT().
  97
  98   @param  Address Address that encodes the PCI Bus, Device, Function and
  99                   Register.
 100   @param  Value   The value to write.
 101
 102   @return The value written to the PCI configuration register.
 103
 104 **/
 105 UINT8
 106 EFIAPI
 107 PciCf8Write8 (
 108   IN      UINTN                     Address,
 109   IN      UINT8                     Value
 110   );
 111
 112 /**
 113   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
 114   an 8-bit value.
 115
 116   Reads the 8-bit PCI configuration register specified by Address, performs a
 117   bitwise inclusive OR between the read result and the value specified by
 118   OrData, and writes the result to the 8-bit PCI configuration register
 119   specified by Address. The value written to the PCI configuration register is
 120   returned. This function must guarantee that all PCI read and write operations
 121   are serialized.
 122
 123   If Address > 0x0FFFFFFF, then ASSERT().
 124   If the register specified by Address >= 0x100, then ASSERT().
 125
 126   @param  Address Address that encodes the PCI Bus, Device, Function and
 127                   Register.
 128   @param  OrData  The value to OR with the PCI configuration register.
 129
 130   @return The value written back to the PCI configuration register.
 131
 132 **/
 133 UINT8
 134 EFIAPI
 135 PciCf8Or8 (
 136   IN      UINTN                     Address,
 137   IN      UINT8                     OrData
 138   );
 139
 140 /**
 141   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 142   value.
 143
 144   Reads the 8-bit PCI configuration register specified by Address, performs a
 145   bitwise AND between the read result and the value specified by AndData, and
 146   writes the result to the 8-bit PCI configuration register specified by
 147   Address. The value written to the PCI configuration register is returned.
 148   This function must guarantee that all PCI read and write operations are
 149   serialized.
 150
 151   If Address > 0x0FFFFFFF, then ASSERT().
 152   If the register specified by Address >= 0x100, then ASSERT().
 153
 154   @param  Address Address that encodes the PCI Bus, Device, Function and
 155                   Register.
 156   @param  AndData The value to AND with the PCI configuration register.
 157
 158   @return The value written back to the PCI configuration register.
 159
 160 **/
 161 UINT8
 162 EFIAPI
 163 PciCf8And8 (
 164   IN      UINTN                     Address,
 165   IN      UINT8                     AndData
 166   );
 167
 168 /**
 169   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 170   value, followed a  bitwise inclusive OR with another 8-bit value.
 171
 172   Reads the 8-bit PCI configuration register specified by Address, performs a
 173   bitwise AND between the read result and the value specified by AndData,
 174   performs a bitwise inclusive OR between the result of the AND operation and
 175   the value specified by OrData, and writes the result to the 8-bit PCI
 176   configuration register specified by Address. The value written to the PCI
 177   configuration register is returned. This function must guarantee that all PCI
 178   read and write operations are serialized.
 179
 180   If Address > 0x0FFFFFFF, then ASSERT().
 181   If the register specified by Address >= 0x100, then ASSERT().
 182
 183   @param  Address Address that encodes the PCI Bus, Device, Function and
 184                   Register.
 185   @param  AndData The value to AND with the PCI configuration register.
 186   @param  OrData  The value to OR with the result of the AND operation.
 187
 188   @return The value written back to the PCI configuration register.
 189
 190 **/
 191 UINT8
 192 EFIAPI
 193 PciCf8AndThenOr8 (
 194   IN      UINTN                     Address,
 195   IN      UINT8                     AndData,
 196   IN      UINT8                     OrData
 197   );
 198
 199 /**
 200   Reads a bit field of a PCI configuration register.
 201
 202   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 203   specified by the StartBit and the EndBit. The value of the bit field is
 204   returned.
 205
 206   If Address > 0x0FFFFFFF, then ASSERT().
 207   If the register specified by Address >= 0x100, then ASSERT().
 208   If StartBit is greater than 7, then ASSERT().
 209   If EndBit is greater than 7, then ASSERT().
 210   If EndBit is less than StartBit, then ASSERT().
 211
 212   @param  Address   PCI configuration register to read.
 213   @param  StartBit  The ordinal of the least significant bit in the bit field.
 214                     Range 0..7.
 215   @param  EndBit    The ordinal of the most significant bit in the bit field.
 216                     Range 0..7.
 217
 218   @return The value of the bit field read from the PCI configuration register.
 219
 220 **/
 221 UINT8
 222 EFIAPI
 223 PciCf8BitFieldRead8 (
 224   IN      UINTN                     Address,
 225   IN      UINTN                     StartBit,
 226   IN      UINTN                     EndBit
 227   );
 228
 229 /**
 230   Writes a bit field to a PCI configuration register.
 231
 232   Writes Value to the bit field of the PCI configuration register. The bit
 233   field is specified by the StartBit and the EndBit. All other bits in the
 234   destination PCI configuration register are preserved. The new value of the
 235   8-bit register is returned.
 236
 237   If Address > 0x0FFFFFFF, then ASSERT().
 238   If the register specified by Address >= 0x100, then ASSERT().
 239   If StartBit is greater than 7, then ASSERT().
 240   If EndBit is greater than 7, then ASSERT().
 241   If EndBit is less than StartBit, then ASSERT().
 242
 243   @param  Address   PCI configuration register to write.
 244   @param  StartBit  The ordinal of the least significant bit in the bit field.
 245                     Range 0..7.
 246   @param  EndBit    The ordinal of the most significant bit in the bit field.
 247                     Range 0..7.
 248   @param  Value     New value of the bit field.
 249
 250   @return The value written back to the PCI configuration register.
 251
 252 **/
 253 UINT8
 254 EFIAPI
 255 PciCf8BitFieldWrite8 (
 256   IN      UINTN                     Address,
 257   IN      UINTN                     StartBit,
 258   IN      UINTN                     EndBit,
 259   IN      UINT8                     Value
 260   );
 261
 262 /**
 263   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 264   writes the result back to the bit field in the 8-bit port.
 265
 266   Reads the 8-bit PCI configuration register specified by Address, performs a
 267   bitwise inclusive OR between the read result and the value specified by
 268   OrData, and writes the result to the 8-bit PCI configuration register
 269   specified by Address. The value written to the PCI configuration register is
 270   returned. This function must guarantee that all PCI read and write operations
 271   are serialized. Extra left bits in OrData are stripped.
 272
 273   If Address > 0x0FFFFFFF, then ASSERT().
 274   If the register specified by Address >= 0x100, then ASSERT().
 275   If StartBit is greater than 7, then ASSERT().
 276   If EndBit is greater than 7, then ASSERT().
 277   If EndBit is less than StartBit, then ASSERT().
 278
 279   @param  Address   PCI configuration register to write.
 280   @param  StartBit  The ordinal of the least significant bit in the bit field.
 281                     Range 0..7.
 282   @param  EndBit    The ordinal of the most significant bit in the bit field.
 283                     Range 0..7.
 284   @param  OrData    The value to OR with the PCI configuration register.
 285
 286   @return The value written back to the PCI configuration register.
 287
 288 **/
 289 UINT8
 290 EFIAPI
 291 PciCf8BitFieldOr8 (
 292   IN      UINTN                     Address,
 293   IN      UINTN                     StartBit,
 294   IN      UINTN                     EndBit,
 295   IN      UINT8                     OrData
 296   );
 297
 298 /**
 299   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 300   AND, and writes the result back to the bit field in the 8-bit register.
 301
 302   Reads the 8-bit PCI configuration register specified by Address, performs a
 303   bitwise AND between the read result and the value specified by AndData, and
 304   writes the result to the 8-bit PCI configuration register specified by
 305   Address. The value written to the PCI configuration register is returned.
 306   This function must guarantee that all PCI read and write operations are
 307   serialized. Extra left bits in AndData are stripped.
 308
 309   If Address > 0x0FFFFFFF, then ASSERT().
 310   If the register specified by Address >= 0x100, then ASSERT().
 311   If StartBit is greater than 7, then ASSERT().
 312   If EndBit is greater than 7, then ASSERT().
 313   If EndBit is less than StartBit, then ASSERT().
 314
 315   @param  Address   PCI configuration register to write.
 316   @param  StartBit  The ordinal of the least significant bit in the bit field.
 317                     Range 0..7.
 318   @param  EndBit    The ordinal of the most significant bit in the bit field.
 319                     Range 0..7.
 320   @param  AndData   The value to AND with the PCI configuration register.
 321
 322   @return The value written back to the PCI configuration register.
 323
 324 **/
 325 UINT8
 326 EFIAPI
 327 PciCf8BitFieldAnd8 (
 328   IN      UINTN                     Address,
 329   IN      UINTN                     StartBit,
 330   IN      UINTN                     EndBit,
 331   IN      UINT8                     AndData
 332   );
 333
 334 /**
 335   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 336   bitwise inclusive OR, and writes the result back to the bit field in the
 337   8-bit port.
 338
 339   Reads the 8-bit PCI configuration register specified by Address, performs a
 340   bitwise AND followed by a bitwise inclusive OR between the read result and
 341   the value specified by AndData, and writes the result to the 8-bit PCI
 342   configuration register specified by Address. The value written to the PCI
 343   configuration register is returned. This function must guarantee that all PCI
 344   read and write operations are serialized. Extra left bits in both AndData and
 345   OrData are stripped.
 346
 347   If Address > 0x0FFFFFFF, then ASSERT().
 348   If the register specified by Address >= 0x100, then ASSERT().
 349   If StartBit is greater than 7, then ASSERT().
 350   If EndBit is greater than 7, then ASSERT().
 351   If EndBit is less than StartBit, then ASSERT().
 352
 353   @param  Address   PCI configuration register to write.
 354   @param  StartBit  The ordinal of the least significant bit in the bit field.
 355                     Range 0..7.
 356   @param  EndBit    The ordinal of the most significant bit in the bit field.
 357                     Range 0..7.
 358   @param  AndData   The value to AND with the PCI configuration register.
 359   @param  OrData    The value to OR with the result of the AND operation.
 360
 361   @return The value written back to the PCI configuration register.
 362
 363 **/
 364 UINT8
 365 EFIAPI
 366 PciCf8BitFieldAndThenOr8 (
 367   IN      UINTN                     Address,
 368   IN      UINTN                     StartBit,
 369   IN      UINTN                     EndBit,
 370   IN      UINT8                     AndData,
 371   IN      UINT8                     OrData
 372   );
 373
 374 /**
 375   Reads a 16-bit PCI configuration register.
 376
 377   Reads and returns the 16-bit PCI configuration register specified by Address.
 378   This function must guarantee that all PCI read and write operations are
 379   serialized.
 380
 381   If Address > 0x0FFFFFFF, then ASSERT().
 382   If Address is not aligned on a 16-bit boundary, then ASSERT().
 383   If the register specified by Address >= 0x100, then ASSERT().
 384
 385   @param  Address Address that encodes the PCI Bus, Device, Function and
 386                   Register.
 387
 388   @return The read value from the PCI configuration register.
 389
 390 **/
 391 UINT16
 392 EFIAPI
 393 PciCf8Read16 (
 394   IN      UINTN                     Address
 395   );
 396
 397 /**
 398   Writes a 16-bit PCI configuration register.
 399
 400   Writes the 16-bit PCI configuration register specified by Address with the
 401   value specified by Value. Value is returned. This function must guarantee
 402   that all PCI read and write operations are serialized.
 403
 404   If Address > 0x0FFFFFFF, then ASSERT().
 405   If Address is not aligned on a 16-bit boundary, then ASSERT().
 406   If the register specified by Address >= 0x100, then ASSERT().
 407
 408   @param  Address Address that encodes the PCI Bus, Device, Function and
 409                   Register.
 410   @param  Value   The value to write.
 411
 412   @return The value written to the PCI configuration register.
 413
 414 **/
 415 UINT16
 416 EFIAPI
 417 PciCf8Write16 (
 418   IN      UINTN                     Address,
 419   IN      UINT16                    Value
 420   );
 421
 422 /**
 423   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 424   a 16-bit value.
 425
 426   Reads the 16-bit PCI configuration register specified by Address, performs a
 427   bitwise inclusive OR between the read result and the value specified by
 428   OrData, and writes the result to the 16-bit PCI configuration register
 429   specified by Address. The value written to the PCI configuration register is
 430   returned. This function must guarantee that all PCI read and write operations
 431   are serialized.
 432
 433   If Address > 0x0FFFFFFF, then ASSERT().
 434   If Address is not aligned on a 16-bit boundary, then ASSERT().
 435   If the register specified by Address >= 0x100, then ASSERT().
 436
 437   @param  Address Address that encodes the PCI Bus, Device, Function and
 438                   Register.
 439   @param  OrData  The value to OR with the PCI configuration register.
 440
 441   @return The value written back to the PCI configuration register.
 442
 443 **/
 444 UINT16
 445 EFIAPI
 446 PciCf8Or16 (
 447   IN      UINTN                     Address,
 448   IN      UINT16                    OrData
 449   );
 450
 451 /**
 452   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 453   value.
 454
 455   Reads the 16-bit PCI configuration register specified by Address, performs a
 456   bitwise AND between the read result and the value specified by AndData, and
 457   writes the result to the 16-bit PCI configuration register specified by
 458   Address. The value written to the PCI configuration register is returned.
 459   This function must guarantee that all PCI read and write operations are
 460   serialized.
 461
 462   If Address > 0x0FFFFFFF, then ASSERT().
 463   If Address is not aligned on a 16-bit boundary, then ASSERT().
 464   If the register specified by Address >= 0x100, then ASSERT().
 465
 466   @param  Address Address that encodes the PCI Bus, Device, Function and
 467                   Register.
 468   @param  AndData The value to AND with the PCI configuration register.
 469
 470   @return The value written back to the PCI configuration register.
 471
 472 **/
 473 UINT16
 474 EFIAPI
 475 PciCf8And16 (
 476   IN      UINTN                     Address,
 477   IN      UINT16                    AndData
 478   );
 479
 480 /**
 481   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 482   value, followed a  bitwise inclusive OR with another 16-bit value.
 483
 484   Reads the 16-bit PCI configuration register specified by Address, performs a
 485   bitwise AND between the read result and the value specified by AndData,
 486   performs a bitwise inclusive OR between the result of the AND operation and
 487   the value specified by OrData, and writes the result to the 16-bit PCI
 488   configuration register specified by Address. The value written to the PCI
 489   configuration register is returned. This function must guarantee that all PCI
 490   read and write operations are serialized.
 491
 492   If Address > 0x0FFFFFFF, then ASSERT().
 493   If Address is not aligned on a 16-bit boundary, then ASSERT().
 494   If the register specified by Address >= 0x100, then ASSERT().
 495
 496   @param  Address Address that encodes the PCI Bus, Device, Function and
 497                   Register.
 498   @param  AndData The value to AND with the PCI configuration register.
 499   @param  OrData  The value to OR with the result of the AND operation.
 500
 501   @return The value written back to the PCI configuration register.
 502
 503 **/
 504 UINT16
 505 EFIAPI
 506 PciCf8AndThenOr16 (
 507   IN      UINTN                     Address,
 508   IN      UINT16                    AndData,
 509   IN      UINT16                    OrData
 510   );
 511
 512 /**
 513   Reads a bit field of a PCI configuration register.
 514
 515   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 516   specified by the StartBit and the EndBit. The value of the bit field is
 517   returned.
 518
 519   If Address > 0x0FFFFFFF, then ASSERT().
 520   If Address is not aligned on a 16-bit boundary, then ASSERT().
 521   If the register specified by Address >= 0x100, then ASSERT().
 522   If StartBit is greater than 15, then ASSERT().
 523   If EndBit is greater than 15, then ASSERT().
 524   If EndBit is less than StartBit, then ASSERT().
 525
 526   @param  Address   PCI configuration register to read.
 527   @param  StartBit  The ordinal of the least significant bit in the bit field.
 528                     Range 0..15.
 529   @param  EndBit    The ordinal of the most significant bit in the bit field.
 530                     Range 0..15.
 531
 532   @return The value of the bit field read from the PCI configuration register.
 533
 534 **/
 535 UINT16
 536 EFIAPI
 537 PciCf8BitFieldRead16 (
 538   IN      UINTN                     Address,
 539   IN      UINTN                     StartBit,
 540   IN      UINTN                     EndBit
 541   );
 542
 543 /**
 544   Writes a bit field to a PCI configuration register.
 545
 546   Writes Value to the bit field of the PCI configuration register. The bit
 547   field is specified by the StartBit and the EndBit. All other bits in the
 548   destination PCI configuration register are preserved. The new value of the
 549   16-bit register is returned.
 550
 551   If Address > 0x0FFFFFFF, then ASSERT().
 552   If Address is not aligned on a 16-bit boundary, then ASSERT().
 553   If the register specified by Address >= 0x100, then ASSERT().
 554   If StartBit is greater than 15, then ASSERT().
 555   If EndBit is greater than 15, then ASSERT().
 556   If EndBit is less than StartBit, then ASSERT().
 557
 558   @param  Address   PCI configuration register to write.
 559   @param  StartBit  The ordinal of the least significant bit in the bit field.
 560                     Range 0..15.
 561   @param  EndBit    The ordinal of the most significant bit in the bit field.
 562                     Range 0..15.
 563   @param  Value     New value of the bit field.
 564
 565   @return The value written back to the PCI configuration register.
 566
 567 **/
 568 UINT16
 569 EFIAPI
 570 PciCf8BitFieldWrite16 (
 571   IN      UINTN                     Address,
 572   IN      UINTN                     StartBit,
 573   IN      UINTN                     EndBit,
 574   IN      UINT16                    Value
 575   );
 576
 577 /**
 578   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 579   writes the result back to the bit field in the 16-bit port.
 580
 581   Reads the 16-bit PCI configuration register specified by Address, performs a
 582   bitwise inclusive OR between the read result and the value specified by
 583   OrData, and writes the result to the 16-bit PCI configuration register
 584   specified by Address. The value written to the PCI configuration register is
 585   returned. This function must guarantee that all PCI read and write operations
 586   are serialized. Extra left bits in OrData are stripped.
 587
 588   If Address > 0x0FFFFFFF, then ASSERT().
 589   If Address is not aligned on a 16-bit boundary, then ASSERT().
 590   If the register specified by Address >= 0x100, then ASSERT().
 591   If StartBit is greater than 15, then ASSERT().
 592   If EndBit is greater than 15, then ASSERT().
 593   If EndBit is less than StartBit, then ASSERT().
 594
 595   @param  Address   PCI configuration register to write.
 596   @param  StartBit  The ordinal of the least significant bit in the bit field.
 597                     Range 0..15.
 598   @param  EndBit    The ordinal of the most significant bit in the bit field.
 599                     Range 0..15.
 600   @param  OrData    The value to OR with the PCI configuration register.
 601
 602   @return The value written back to the PCI configuration register.
 603
 604 **/
 605 UINT16
 606 EFIAPI
 607 PciCf8BitFieldOr16 (
 608   IN      UINTN                     Address,
 609   IN      UINTN                     StartBit,
 610   IN      UINTN                     EndBit,
 611   IN      UINT16                    OrData
 612   );
 613
 614 /**
 615   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 616   AND, and writes the result back to the bit field in the 16-bit register.
 617
 618   Reads the 16-bit PCI configuration register specified by Address, performs a
 619   bitwise AND between the read result and the value specified by AndData, and
 620   writes the result to the 16-bit PCI configuration register specified by
 621   Address. The value written to the PCI configuration register is returned.
 622   This function must guarantee that all PCI read and write operations are
 623   serialized. Extra left bits in AndData are stripped.
 624
 625   If Address > 0x0FFFFFFF, then ASSERT().
 626   If Address is not aligned on a 16-bit boundary, then ASSERT().
 627   If the register specified by Address >= 0x100, then ASSERT().
 628   If StartBit is greater than 15, then ASSERT().
 629   If EndBit is greater than 15, then ASSERT().
 630   If EndBit is less than StartBit, then ASSERT().
 631
 632   @param  Address   PCI configuration register to write.
 633   @param  StartBit  The ordinal of the least significant bit in the bit field.
 634                     Range 0..15.
 635   @param  EndBit    The ordinal of the most significant bit in the bit field.
 636                     Range 0..15.
 637   @param  AndData   The value to AND with the PCI configuration register.
 638
 639   @return The value written back to the PCI configuration register.
 640
 641 **/
 642 UINT16
 643 EFIAPI
 644 PciCf8BitFieldAnd16 (
 645   IN      UINTN                     Address,
 646   IN      UINTN                     StartBit,
 647   IN      UINTN                     EndBit,
 648   IN      UINT16                    AndData
 649   );
 650
 651 /**
 652   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 653   bitwise inclusive OR, and writes the result back to the bit field in the
 654   16-bit port.
 655
 656   Reads the 16-bit PCI configuration register specified by Address, performs a
 657   bitwise AND followed by a bitwise inclusive OR between the read result and
 658   the value specified by AndData, and writes the result to the 16-bit PCI
 659   configuration register specified by Address. The value written to the PCI
 660   configuration register is returned. This function must guarantee that all PCI
 661   read and write operations are serialized. Extra left bits in both AndData and
 662   OrData are stripped.
 663
 664   If Address > 0x0FFFFFFF, then ASSERT().
 665   If Address is not aligned on a 16-bit boundary, then ASSERT().
 666   If the register specified by Address >= 0x100, then ASSERT().
 667   If StartBit is greater than 15, then ASSERT().
 668   If EndBit is greater than 15, then ASSERT().
 669   If EndBit is less than StartBit, then ASSERT().
 670
 671   @param  Address   PCI configuration register to write.
 672   @param  StartBit  The ordinal of the least significant bit in the bit field.
 673                     Range 0..15.
 674   @param  EndBit    The ordinal of the most significant bit in the bit field.
 675                     Range 0..15.
 676   @param  AndData   The value to AND with the PCI configuration register.
 677   @param  OrData    The value to OR with the result of the AND operation.
 678
 679   @return The value written back to the PCI configuration register.
 680
 681 **/
 682 UINT16
 683 EFIAPI
 684 PciCf8BitFieldAndThenOr16 (
 685   IN      UINTN                     Address,
 686   IN      UINTN                     StartBit,
 687   IN      UINTN                     EndBit,
 688   IN      UINT16                    AndData,
 689   IN      UINT16                    OrData
 690   );
 691
 692 /**
 693   Reads a 32-bit PCI configuration register.
 694
 695   Reads and returns the 32-bit PCI configuration register specified by Address.
 696   This function must guarantee that all PCI read and write operations are
 697   serialized.
 698
 699   If Address > 0x0FFFFFFF, then ASSERT().
 700   If Address is not aligned on a 32-bit boundary, then ASSERT().
 701   If the register specified by Address >= 0x100, then ASSERT().
 702
 703   @param  Address Address that encodes the PCI Bus, Device, Function and
 704                   Register.
 705
 706   @return The read value from the PCI configuration register.
 707
 708 **/
 709 UINT32
 710 EFIAPI
 711 PciCf8Read32 (
 712   IN      UINTN                     Address
 713   );
 714
 715 /**
 716   Writes a 32-bit PCI configuration register.
 717
 718   Writes the 32-bit PCI configuration register specified by Address with the
 719   value specified by Value. Value is returned. This function must guarantee
 720   that all PCI read and write operations are serialized.
 721
 722   If Address > 0x0FFFFFFF, then ASSERT().
 723   If Address is not aligned on a 32-bit boundary, then ASSERT().
 724   If the register specified by Address >= 0x100, then ASSERT().
 725
 726   @param  Address Address that encodes the PCI Bus, Device, Function and
 727                   Register.
 728   @param  Value   The value to write.
 729
 730   @return The value written to the PCI configuration register.
 731
 732 **/
 733 UINT32
 734 EFIAPI
 735 PciCf8Write32 (
 736   IN      UINTN                     Address,
 737   IN      UINT32                    Value
 738   );
 739
 740 /**
 741   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 742   a 32-bit value.
 743
 744   Reads the 32-bit PCI configuration register specified by Address, performs a
 745   bitwise inclusive OR between the read result and the value specified by
 746   OrData, and writes the result to the 32-bit PCI configuration register
 747   specified by Address. The value written to the PCI configuration register is
 748   returned. This function must guarantee that all PCI read and write operations
 749   are serialized.
 750
 751   If Address > 0x0FFFFFFF, then ASSERT().
 752   If Address is not aligned on a 32-bit boundary, then ASSERT().
 753   If the register specified by Address >= 0x100, then ASSERT().
 754
 755   @param  Address Address that encodes the PCI Bus, Device, Function and
 756                   Register.
 757   @param  OrData  The value to OR with the PCI configuration register.
 758
 759   @return The value written back to the PCI configuration register.
 760
 761 **/
 762 UINT32
 763 EFIAPI
 764 PciCf8Or32 (
 765   IN      UINTN                     Address,
 766   IN      UINT32                    OrData
 767   );
 768
 769 /**
 770   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 771   value.
 772
 773   Reads the 32-bit PCI configuration register specified by Address, performs a
 774   bitwise AND between the read result and the value specified by AndData, and
 775   writes the result to the 32-bit PCI configuration register specified by
 776   Address. The value written to the PCI configuration register is returned.
 777   This function must guarantee that all PCI read and write operations are
 778   serialized.
 779
 780   If Address > 0x0FFFFFFF, then ASSERT().
 781   If Address is not aligned on a 32-bit boundary, then ASSERT().
 782   If the register specified by Address >= 0x100, then ASSERT().
 783
 784   @param  Address Address that encodes the PCI Bus, Device, Function and
 785                   Register.
 786   @param  AndData The value to AND with the PCI configuration register.
 787
 788   @return The value written back to the PCI configuration register.
 789
 790 **/
 791 UINT32
 792 EFIAPI
 793 PciCf8And32 (
 794   IN      UINTN                     Address,
 795   IN      UINT32                    AndData
 796   );
 797
 798 /**
 799   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 800   value, followed a  bitwise inclusive OR with another 32-bit value.
 801
 802   Reads the 32-bit PCI configuration register specified by Address, performs a
 803   bitwise AND between the read result and the value specified by AndData,
 804   performs a bitwise inclusive OR between the result of the AND operation and
 805   the value specified by OrData, and writes the result to the 32-bit PCI
 806   configuration register specified by Address. The value written to the PCI
 807   configuration register is returned. This function must guarantee that all PCI
 808   read and write operations are serialized.
 809
 810   If Address > 0x0FFFFFFF, then ASSERT().
 811   If Address is not aligned on a 32-bit boundary, then ASSERT().
 812   If the register specified by Address >= 0x100, then ASSERT().
 813
 814   @param  Address Address that encodes the PCI Bus, Device, Function and
 815                   Register.
 816   @param  AndData The value to AND with the PCI configuration register.
 817   @param  OrData  The value to OR with the result of the AND operation.
 818
 819   @return The value written back to the PCI configuration register.
 820
 821 **/
 822 UINT32
 823 EFIAPI
 824 PciCf8AndThenOr32 (
 825   IN      UINTN                     Address,
 826   IN      UINT32                    AndData,
 827   IN      UINT32                    OrData
 828   );
 829
 830 /**
 831   Reads a bit field of a PCI configuration register.
 832
 833   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 834   specified by the StartBit and the EndBit. The value of the bit field is
 835   returned.
 836
 837   If Address > 0x0FFFFFFF, then ASSERT().
 838   If Address is not aligned on a 32-bit boundary, then ASSERT().
 839   If the register specified by Address >= 0x100, then ASSERT().
 840   If StartBit is greater than 31, then ASSERT().
 841   If EndBit is greater than 31, then ASSERT().
 842   If EndBit is less than StartBit, then ASSERT().
 843
 844   @param  Address   PCI configuration register to read.
 845   @param  StartBit  The ordinal of the least significant bit in the bit field.
 846                     Range 0..31.
 847   @param  EndBit    The ordinal of the most significant bit in the bit field.
 848                     Range 0..31.
 849
 850   @return The value of the bit field read from the PCI configuration register.
 851
 852 **/
 853 UINT32
 854 EFIAPI
 855 PciCf8BitFieldRead32 (
 856   IN      UINTN                     Address,
 857   IN      UINTN                     StartBit,
 858   IN      UINTN                     EndBit
 859   );
 860
 861 /**
 862   Writes a bit field to a PCI configuration register.
 863
 864   Writes Value to the bit field of the PCI configuration register. The bit
 865   field is specified by the StartBit and the EndBit. All other bits in the
 866   destination PCI configuration register are preserved. The new value of the
 867   32-bit register is returned.
 868
 869   If Address > 0x0FFFFFFF, then ASSERT().
 870   If Address is not aligned on a 32-bit boundary, then ASSERT().
 871   If the register specified by Address >= 0x100, then ASSERT().
 872   If StartBit is greater than 31, then ASSERT().
 873   If EndBit is greater than 31, then ASSERT().
 874   If EndBit is less than StartBit, then ASSERT().
 875
 876   @param  Address   PCI configuration register to write.
 877   @param  StartBit  The ordinal of the least significant bit in the bit field.
 878                     Range 0..31.
 879   @param  EndBit    The ordinal of the most significant bit in the bit field.
 880                     Range 0..31.
 881   @param  Value     New value of the bit field.
 882
 883   @return The value written back to the PCI configuration register.
 884
 885 **/
 886 UINT32
 887 EFIAPI
 888 PciCf8BitFieldWrite32 (
 889   IN      UINTN                     Address,
 890   IN      UINTN                     StartBit,
 891   IN      UINTN                     EndBit,
 892   IN      UINT32                    Value
 893   );
 894
 895 /**
 896   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 897   writes the result back to the bit field in the 32-bit port.
 898
 899   Reads the 32-bit PCI configuration register specified by Address, performs a
 900   bitwise inclusive OR between the read result and the value specified by
 901   OrData, and writes the result to the 32-bit PCI configuration register
 902   specified by Address. The value written to the PCI configuration register is
 903   returned. This function must guarantee that all PCI read and write operations
 904   are serialized. Extra left bits in OrData are stripped.
 905
 906   If Address > 0x0FFFFFFF, then ASSERT().
 907   If Address is not aligned on a 32-bit boundary, then ASSERT().
 908   If the register specified by Address >= 0x100, then ASSERT().
 909   If StartBit is greater than 31, then ASSERT().
 910   If EndBit is greater than 31, then ASSERT().
 911   If EndBit is less than StartBit, then ASSERT().
 912
 913   @param  Address   PCI configuration register to write.
 914   @param  StartBit  The ordinal of the least significant bit in the bit field.
 915                     Range 0..31.
 916   @param  EndBit    The ordinal of the most significant bit in the bit field.
 917                     Range 0..31.
 918   @param  OrData    The value to OR with the PCI configuration register.
 919
 920   @return The value written back to the PCI configuration register.
 921
 922 **/
 923 UINT32
 924 EFIAPI
 925 PciCf8BitFieldOr32 (
 926   IN      UINTN                     Address,
 927   IN      UINTN                     StartBit,
 928   IN      UINTN                     EndBit,
 929   IN      UINT32                    OrData
 930   );
 931
 932 /**
 933   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 934   AND, and writes the result back to the bit field in the 32-bit register.
 935
 936   Reads the 32-bit PCI configuration register specified by Address, performs a
 937   bitwise AND between the read result and the value specified by AndData, and
 938   writes the result to the 32-bit PCI configuration register specified by
 939   Address. The value written to the PCI configuration register is returned.
 940   This function must guarantee that all PCI read and write operations are
 941   serialized. Extra left bits in AndData are stripped.
 942
 943   If Address > 0x0FFFFFFF, then ASSERT().
 944   If Address is not aligned on a 32-bit boundary, then ASSERT().
 945   If the register specified by Address >= 0x100, then ASSERT().
 946   If StartBit is greater than 31, then ASSERT().
 947   If EndBit is greater than 31, then ASSERT().
 948   If EndBit is less than StartBit, then ASSERT().
 949
 950   @param  Address   PCI configuration register to write.
 951   @param  StartBit  The ordinal of the least significant bit in the bit field.
 952                     Range 0..31.
 953   @param  EndBit    The ordinal of the most significant bit in the bit field.
 954                     Range 0..31.
 955   @param  AndData   The value to AND with the PCI configuration register.
 956
 957   @return The value written back to the PCI configuration register.
 958
 959 **/
 960 UINT32
 961 EFIAPI
 962 PciCf8BitFieldAnd32 (
 963   IN      UINTN                     Address,
 964   IN      UINTN                     StartBit,
 965   IN      UINTN                     EndBit,
 966   IN      UINT32                    AndData
 967   );
 968
 969 /**
 970   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 971   bitwise inclusive OR, and writes the result back to the bit field in the
 972   32-bit port.
 973
 974   Reads the 32-bit PCI configuration register specified by Address, performs a
 975   bitwise AND followed by a bitwise inclusive OR between the read result and
 976   the value specified by AndData, and writes the result to the 32-bit PCI
 977   configuration register specified by Address. The value written to the PCI
 978   configuration register is returned. This function must guarantee that all PCI
 979   read and write operations are serialized. Extra left bits in both AndData and
 980   OrData are stripped.
 981
 982   If Address > 0x0FFFFFFF, then ASSERT().
 983   If Address is not aligned on a 32-bit boundary, then ASSERT().
 984   If the register specified by Address >= 0x100, then ASSERT().
 985   If StartBit is greater than 31, then ASSERT().
 986   If EndBit is greater than 31, then ASSERT().
 987   If EndBit is less than StartBit, then ASSERT().
 988
 989   @param  Address   PCI configuration register to write.
 990   @param  StartBit  The ordinal of the least significant bit in the bit field.
 991                     Range 0..31.
 992   @param  EndBit    The ordinal of the most significant bit in the bit field.
 993                     Range 0..31.
 994   @param  AndData   The value to AND with the PCI configuration register.
 995   @param  OrData    The value to OR with the result of the AND operation.
 996
 997   @return The value written back to the PCI configuration register.
 998
 999 **/
1000 UINT32
1001 EFIAPI
1002 PciCf8BitFieldAndThenOr32 (
1003   IN      UINTN                     Address,
1004   IN      UINTN                     StartBit,
1005   IN      UINTN                     EndBit,
1006   IN      UINT32                    AndData,
1007   IN      UINT32                    OrData
1008   );
1009
1010 /**
1011   Reads a range of PCI configuration registers into a caller supplied buffer.
1012
1013   Reads the range of PCI configuration registers specified by StartAddress and
1014   Size into the buffer specified by Buffer. This function only allows the PCI
1015   configuration registers from a single PCI function to be read. Size is
1016   returned. When possible 32-bit PCI configuration read cycles are used to read
1017   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1018   and 16-bit PCI configuration read cycles may be used at the beginning and the
1019   end of the range.
1020
1021   If StartAddress > 0x0FFFFFFF, then ASSERT().
1022   If the register specified by StartAddress >= 0x100, then ASSERT().
1023   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1024   If Size > 0 and Buffer is NULL, then ASSERT().
1025
1026   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1027                         Function and Register.
1028   @param  Size          Size in bytes of the transfer.
1029   @param  Buffer        Pointer to a buffer receiving the data read.
1030
1031   @return Size read from StartAddress.
1032
1033 **/
1034 UINTN
1035 EFIAPI
1036 PciCf8ReadBuffer (
1037   IN      UINTN                     StartAddress,
1038   IN      UINTN                     Size,
1039   OUT     VOID                      *Buffer
1040   );
1041
1042 /**
1043   Copies the data in a caller supplied buffer to a specified range of PCI
1044   configuration space.
1045
1046   Writes the range of PCI configuration registers specified by StartAddress and
1047   Size from the buffer specified by Buffer. This function only allows the PCI
1048   configuration registers from a single PCI function to be written. Size is
1049   returned. When possible 32-bit PCI configuration write cycles are used to
1050   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1051   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1052   and the end of the range.
1053
1054   If StartAddress > 0x0FFFFFFF, then ASSERT().
1055   If the register specified by StartAddress >= 0x100, then ASSERT().
1056   If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1057   If Size > 0 and Buffer is NULL, then ASSERT().
1058
1059   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1060                         Function and Register.
1061   @param  Size          Size in bytes of the transfer.
1062   @param  Buffer        Pointer to a buffer containing the data to write.
1063
1064   @return Size written to StartAddress.
1065
1066 **/
1067 UINTN
1068 EFIAPI
1069 PciCf8WriteBuffer (
1070   IN      UINTN                     StartAddress,
1071   IN      UINTN                     Size,
1072   IN      VOID                      *Buffer
1073   );
1074
1075 #endif