MdePkg/Include/Library/PciExpressLib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space using the MMIO PCI Express window.
   3
   4   This library is identical to the PCI Library, except the access method for performing PCI
   5   configuration cycles must be though the 256 MB PCI Express MMIO window whose base address
   6   is defined by PcdPciExpressBaseAddress.
   7
   8 Copyright (c) 2006 - 2008, Intel Corporation<BR>
   9 All rights reserved. This program and the accompanying materials
  10 are licensed and made available under the terms and conditions of the BSD License
  11 which accompanies this distribution.  The full text of the license may be found at
  12 http://opensource.org/licenses/bsd-license.php
  13
  14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  16
  17 **/
  18
  19 #ifndef __PCI_EXPRESS_LIB_H__
  20 #define __PCI_EXPRESS_LIB_H__
  21
  22 /**
  23   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  24   address that can be passed to the PCI Library functions.
  25
  26   Computes an address that is compatible with the PCI Library functions. The
  27   unused upper bits of Bus, Device, Function and Register are stripped prior to
  28   the generation of the address.
  29
  30   @param  Bus       PCI Bus number. Range 0..255.
  31   @param  Device    PCI Device number. Range 0..31.
  32   @param  Function  PCI Function number. Range 0..7.
  33   @param  Register  PCI Register number. Range 0..4095.
  34
  35   @return The encode PCI address.
  36
  37 **/
  38 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
  39   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  40
  41 /**
  42   Register a PCI device so PCI configuration registers may be accessed after
  43   SetVirtualAddressMap().
  44
  45   If Address > 0x0FFFFFFF, then ASSERT().
  46
  47   @param  Address Address that encodes the PCI Bus, Device, Function and
  48                   Register.
  49
  50   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  51   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  52                                    after ExitBootServices().
  53   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  54                                    at runtime could not be mapped.
  55   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  56                                    complete the registration.
  57
  58 **/
  59 RETURN_STATUS
  60 EFIAPI
  61 PciExpressRegisterForRuntimeAccess (
  62   IN UINTN  Address
  63   );
  64
  65 /**
  66   Reads an 8-bit PCI configuration register.
  67
  68   Reads and returns the 8-bit PCI configuration register specified by Address.
  69   This function must guarantee that all PCI read and write operations are
  70   serialized.
  71
  72   If Address > 0x0FFFFFFF, then ASSERT().
  73
  74   @param  Address Address that encodes the PCI Bus, Device, Function and
  75                   Register.
  76
  77   @return The read value from the PCI configuration register.
  78
  79 **/
  80 UINT8
  81 EFIAPI
  82 PciExpressRead8 (
  83   IN      UINTN                     Address
  84   );
  85
  86 /**
  87   Writes an 8-bit PCI configuration register.
  88
  89   Writes the 8-bit PCI configuration register specified by Address with the
  90   value specified by Value. Value is returned. This function must guarantee
  91   that all PCI read and write operations are serialized.
  92
  93   If Address > 0x0FFFFFFF, then ASSERT().
  94
  95   @param  Address Address that encodes the PCI Bus, Device, Function and
  96                   Register.
  97   @param  Value   The value to write.
  98
  99   @return The value written to the PCI configuration register.
 100
 101 **/
 102 UINT8
 103 EFIAPI
 104 PciExpressWrite8 (
 105   IN      UINTN                     Address,
 106   IN      UINT8                     Value
 107   );
 108
 109 /**
 110   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
 111   an 8-bit value.
 112
 113   Reads the 8-bit PCI configuration register specified by Address, performs a
 114   bitwise inclusive OR between the read result and the value specified by
 115   OrData, and writes the result to the 8-bit PCI configuration register
 116   specified by Address. The value written to the PCI configuration register is
 117   returned. This function must guarantee that all PCI read and write operations
 118   are serialized.
 119
 120   If Address > 0x0FFFFFFF, then ASSERT().
 121
 122   @param  Address Address that encodes the PCI Bus, Device, Function and
 123                   Register.
 124   @param  OrData  The value to OR with the PCI configuration register.
 125
 126   @return The value written back to the PCI configuration register.
 127
 128 **/
 129 UINT8
 130 EFIAPI
 131 PciExpressOr8 (
 132   IN      UINTN                     Address,
 133   IN      UINT8                     OrData
 134   );
 135
 136 /**
 137   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 138   value.
 139
 140   Reads the 8-bit PCI configuration register specified by Address, performs a
 141   bitwise AND between the read result and the value specified by AndData, and
 142   writes the result to the 8-bit PCI configuration register specified by
 143   Address. The value written to the PCI configuration register is returned.
 144   This function must guarantee that all PCI read and write operations are
 145   serialized.
 146
 147   If Address > 0x0FFFFFFF, then ASSERT().
 148
 149   @param  Address Address that encodes the PCI Bus, Device, Function and
 150                   Register.
 151   @param  AndData The value to AND with the PCI configuration register.
 152
 153   @return The value written back to the PCI configuration register.
 154
 155 **/
 156 UINT8
 157 EFIAPI
 158 PciExpressAnd8 (
 159   IN      UINTN                     Address,
 160   IN      UINT8                     AndData
 161   );
 162
 163 /**
 164   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 165   value, followed a  bitwise inclusive OR with another 8-bit value.
 166
 167   Reads the 8-bit PCI configuration register specified by Address, performs a
 168   bitwise AND between the read result and the value specified by AndData,
 169   performs a bitwise inclusive OR between the result of the AND operation and
 170   the value specified by OrData, and writes the result to the 8-bit PCI
 171   configuration register specified by Address. The value written to the PCI
 172   configuration register is returned. This function must guarantee that all PCI
 173   read and write operations are serialized.
 174
 175   If Address > 0x0FFFFFFF, then ASSERT().
 176
 177   @param  Address Address that encodes the PCI Bus, Device, Function and
 178                   Register.
 179   @param  AndData The value to AND with the PCI configuration register.
 180   @param  OrData  The value to OR with the result of the AND operation.
 181
 182   @return The value written back to the PCI configuration register.
 183
 184 **/
 185 UINT8
 186 EFIAPI
 187 PciExpressAndThenOr8 (
 188   IN      UINTN                     Address,
 189   IN      UINT8                     AndData,
 190   IN      UINT8                     OrData
 191   );
 192
 193 /**
 194   Reads a bit field of a PCI configuration register.
 195
 196   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 197   specified by the StartBit and the EndBit. The value of the bit field is
 198   returned.
 199
 200   If Address > 0x0FFFFFFF, then ASSERT().
 201   If StartBit is greater than 7, then ASSERT().
 202   If EndBit is greater than 7, then ASSERT().
 203   If EndBit is less than StartBit, then ASSERT().
 204
 205   @param  Address   PCI configuration register to read.
 206   @param  StartBit  The ordinal of the least significant bit in the bit field.
 207                     Range 0..7.
 208   @param  EndBit    The ordinal of the most significant bit in the bit field.
 209                     Range 0..7.
 210
 211   @return The value of the bit field read from the PCI configuration register.
 212
 213 **/
 214 UINT8
 215 EFIAPI
 216 PciExpressBitFieldRead8 (
 217   IN      UINTN                     Address,
 218   IN      UINTN                     StartBit,
 219   IN      UINTN                     EndBit
 220   );
 221
 222 /**
 223   Writes a bit field to a PCI configuration register.
 224
 225   Writes Value to the bit field of the PCI configuration register. The bit
 226   field is specified by the StartBit and the EndBit. All other bits in the
 227   destination PCI configuration register are preserved. The new value of the
 228   8-bit register is returned.
 229
 230   If Address > 0x0FFFFFFF, then ASSERT().
 231   If StartBit is greater than 7, then ASSERT().
 232   If EndBit is greater than 7, then ASSERT().
 233   If EndBit is less than StartBit, then ASSERT().
 234
 235   @param  Address   PCI configuration register to write.
 236   @param  StartBit  The ordinal of the least significant bit in the bit field.
 237                     Range 0..7.
 238   @param  EndBit    The ordinal of the most significant bit in the bit field.
 239                     Range 0..7.
 240   @param  Value     New value of the bit field.
 241
 242   @return The value written back to the PCI configuration register.
 243
 244 **/
 245 UINT8
 246 EFIAPI
 247 PciExpressBitFieldWrite8 (
 248   IN      UINTN                     Address,
 249   IN      UINTN                     StartBit,
 250   IN      UINTN                     EndBit,
 251   IN      UINT8                     Value
 252   );
 253
 254 /**
 255   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 256   writes the result back to the bit field in the 8-bit port.
 257
 258   Reads the 8-bit PCI configuration register specified by Address, performs a
 259   bitwise inclusive OR between the read result and the value specified by
 260   OrData, and writes the result to the 8-bit PCI configuration register
 261   specified by Address. The value written to the PCI configuration register is
 262   returned. This function must guarantee that all PCI read and write operations
 263   are serialized. Extra left bits in OrData are stripped.
 264
 265   If Address > 0x0FFFFFFF, then ASSERT().
 266   If StartBit is greater than 7, then ASSERT().
 267   If EndBit is greater than 7, then ASSERT().
 268   If EndBit is less than StartBit, then ASSERT().
 269
 270   @param  Address   PCI configuration register to write.
 271   @param  StartBit  The ordinal of the least significant bit in the bit field.
 272                     Range 0..7.
 273   @param  EndBit    The ordinal of the most significant bit in the bit field.
 274                     Range 0..7.
 275   @param  OrData    The value to OR with the PCI configuration register.
 276
 277   @return The value written back to the PCI configuration register.
 278
 279 **/
 280 UINT8
 281 EFIAPI
 282 PciExpressBitFieldOr8 (
 283   IN      UINTN                     Address,
 284   IN      UINTN                     StartBit,
 285   IN      UINTN                     EndBit,
 286   IN      UINT8                     OrData
 287   );
 288
 289 /**
 290   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 291   AND, and writes the result back to the bit field in the 8-bit register.
 292
 293   Reads the 8-bit PCI configuration register specified by Address, performs a
 294   bitwise AND between the read result and the value specified by AndData, and
 295   writes the result to the 8-bit PCI configuration register specified by
 296   Address. The value written to the PCI configuration register is returned.
 297   This function must guarantee that all PCI read and write operations are
 298   serialized. Extra left bits in AndData are stripped.
 299
 300   If Address > 0x0FFFFFFF, then ASSERT().
 301   If StartBit is greater than 7, then ASSERT().
 302   If EndBit is greater than 7, then ASSERT().
 303   If EndBit is less than StartBit, then ASSERT().
 304
 305   @param  Address   PCI configuration register to write.
 306   @param  StartBit  The ordinal of the least significant bit in the bit field.
 307                     Range 0..7.
 308   @param  EndBit    The ordinal of the most significant bit in the bit field.
 309                     Range 0..7.
 310   @param  AndData   The value to AND with the PCI configuration register.
 311
 312   @return The value written back to the PCI configuration register.
 313
 314 **/
 315 UINT8
 316 EFIAPI
 317 PciExpressBitFieldAnd8 (
 318   IN      UINTN                     Address,
 319   IN      UINTN                     StartBit,
 320   IN      UINTN                     EndBit,
 321   IN      UINT8                     AndData
 322   );
 323
 324 /**
 325   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 326   bitwise inclusive OR, and writes the result back to the bit field in the
 327   8-bit port.
 328
 329   Reads the 8-bit PCI configuration register specified by Address, performs a
 330   bitwise AND followed by a bitwise inclusive OR between the read result and
 331   the value specified by AndData, and writes the result to the 8-bit PCI
 332   configuration register specified by Address. The value written to the PCI
 333   configuration register is returned. This function must guarantee that all PCI
 334   read and write operations are serialized. Extra left bits in both AndData and
 335   OrData are stripped.
 336
 337   If Address > 0x0FFFFFFF, then ASSERT().
 338   If StartBit is greater than 7, then ASSERT().
 339   If EndBit is greater than 7, then ASSERT().
 340   If EndBit is less than StartBit, then ASSERT().
 341
 342   @param  Address   PCI configuration register to write.
 343   @param  StartBit  The ordinal of the least significant bit in the bit field.
 344                     Range 0..7.
 345   @param  EndBit    The ordinal of the most significant bit in the bit field.
 346                     Range 0..7.
 347   @param  AndData   The value to AND with the PCI configuration register.
 348   @param  OrData    The value to OR with the result of the AND operation.
 349
 350   @return The value written back to the PCI configuration register.
 351
 352 **/
 353 UINT8
 354 EFIAPI
 355 PciExpressBitFieldAndThenOr8 (
 356   IN      UINTN                     Address,
 357   IN      UINTN                     StartBit,
 358   IN      UINTN                     EndBit,
 359   IN      UINT8                     AndData,
 360   IN      UINT8                     OrData
 361   );
 362
 363 /**
 364   Reads a 16-bit PCI configuration register.
 365
 366   Reads and returns the 16-bit PCI configuration register specified by Address.
 367   This function must guarantee that all PCI read and write operations are
 368   serialized.
 369
 370   If Address > 0x0FFFFFFF, then ASSERT().
 371   If Address is not aligned on a 16-bit boundary, then ASSERT().
 372
 373   @param  Address Address that encodes the PCI Bus, Device, Function and
 374                   Register.
 375
 376   @return The read value from the PCI configuration register.
 377
 378 **/
 379 UINT16
 380 EFIAPI
 381 PciExpressRead16 (
 382   IN      UINTN                     Address
 383   );
 384
 385 /**
 386   Writes a 16-bit PCI configuration register.
 387
 388   Writes the 16-bit PCI configuration register specified by Address with the
 389   value specified by Value. Value is returned. This function must guarantee
 390   that all PCI read and write operations are serialized.
 391
 392   If Address > 0x0FFFFFFF, then ASSERT().
 393   If Address is not aligned on a 16-bit boundary, then ASSERT().
 394
 395   @param  Address Address that encodes the PCI Bus, Device, Function and
 396                   Register.
 397   @param  Value   The value to write.
 398
 399   @return The value written to the PCI configuration register.
 400
 401 **/
 402 UINT16
 403 EFIAPI
 404 PciExpressWrite16 (
 405   IN      UINTN                     Address,
 406   IN      UINT16                    Value
 407   );
 408
 409 /**
 410   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 411   a 16-bit value.
 412
 413   Reads the 16-bit PCI configuration register specified by Address, performs a
 414   bitwise inclusive OR between the read result and the value specified by
 415   OrData, and writes the result to the 16-bit PCI configuration register
 416   specified by Address. The value written to the PCI configuration register is
 417   returned. This function must guarantee that all PCI read and write operations
 418   are serialized.
 419
 420   If Address > 0x0FFFFFFF, then ASSERT().
 421   If Address is not aligned on a 16-bit boundary, then ASSERT().
 422
 423   @param  Address Address that encodes the PCI Bus, Device, Function and
 424                   Register.
 425   @param  OrData  The value to OR with the PCI configuration register.
 426
 427   @return The value written back to the PCI configuration register.
 428
 429 **/
 430 UINT16
 431 EFIAPI
 432 PciExpressOr16 (
 433   IN      UINTN                     Address,
 434   IN      UINT16                    OrData
 435   );
 436
 437 /**
 438   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 439   value.
 440
 441   Reads the 16-bit PCI configuration register specified by Address, performs a
 442   bitwise AND between the read result and the value specified by AndData, and
 443   writes the result to the 16-bit PCI configuration register specified by
 444   Address. The value written to the PCI configuration register is returned.
 445   This function must guarantee that all PCI read and write operations are
 446   serialized.
 447
 448   If Address > 0x0FFFFFFF, then ASSERT().
 449   If Address is not aligned on a 16-bit boundary, then ASSERT().
 450
 451   @param  Address Address that encodes the PCI Bus, Device, Function and
 452                   Register.
 453   @param  AndData The value to AND with the PCI configuration register.
 454
 455   @return The value written back to the PCI configuration register.
 456
 457 **/
 458 UINT16
 459 EFIAPI
 460 PciExpressAnd16 (
 461   IN      UINTN                     Address,
 462   IN      UINT16                    AndData
 463   );
 464
 465 /**
 466   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 467   value, followed a  bitwise inclusive OR with another 16-bit value.
 468
 469   Reads the 16-bit PCI configuration register specified by Address, performs a
 470   bitwise AND between the read result and the value specified by AndData,
 471   performs a bitwise inclusive OR between the result of the AND operation and
 472   the value specified by OrData, and writes the result to the 16-bit PCI
 473   configuration register specified by Address. The value written to the PCI
 474   configuration register is returned. This function must guarantee that all PCI
 475   read and write operations are serialized.
 476
 477   If Address > 0x0FFFFFFF, then ASSERT().
 478   If Address is not aligned on a 16-bit boundary, then ASSERT().
 479
 480   @param  Address Address that encodes the PCI Bus, Device, Function and
 481                   Register.
 482   @param  AndData The value to AND with the PCI configuration register.
 483   @param  OrData  The value to OR with the result of the AND operation.
 484
 485   @return The value written back to the PCI configuration register.
 486
 487 **/
 488 UINT16
 489 EFIAPI
 490 PciExpressAndThenOr16 (
 491   IN      UINTN                     Address,
 492   IN      UINT16                    AndData,
 493   IN      UINT16                    OrData
 494   );
 495
 496 /**
 497   Reads a bit field of a PCI configuration register.
 498
 499   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 500   specified by the StartBit and the EndBit. The value of the bit field is
 501   returned.
 502
 503   If Address > 0x0FFFFFFF, then ASSERT().
 504   If Address is not aligned on a 16-bit boundary, then ASSERT().
 505   If StartBit is greater than 15, then ASSERT().
 506   If EndBit is greater than 15, then ASSERT().
 507   If EndBit is less than StartBit, then ASSERT().
 508
 509   @param  Address   PCI configuration register to read.
 510   @param  StartBit  The ordinal of the least significant bit in the bit field.
 511                     Range 0..15.
 512   @param  EndBit    The ordinal of the most significant bit in the bit field.
 513                     Range 0..15.
 514
 515   @return The value of the bit field read from the PCI configuration register.
 516
 517 **/
 518 UINT16
 519 EFIAPI
 520 PciExpressBitFieldRead16 (
 521   IN      UINTN                     Address,
 522   IN      UINTN                     StartBit,
 523   IN      UINTN                     EndBit
 524   );
 525
 526 /**
 527   Writes a bit field to a PCI configuration register.
 528
 529   Writes Value to the bit field of the PCI configuration register. The bit
 530   field is specified by the StartBit and the EndBit. All other bits in the
 531   destination PCI configuration register are preserved. The new value of the
 532   16-bit register is returned.
 533
 534   If Address > 0x0FFFFFFF, then ASSERT().
 535   If Address is not aligned on a 16-bit boundary, then ASSERT().
 536   If StartBit is greater than 15, then ASSERT().
 537   If EndBit is greater than 15, then ASSERT().
 538   If EndBit is less than StartBit, then ASSERT().
 539
 540   @param  Address   PCI configuration register to write.
 541   @param  StartBit  The ordinal of the least significant bit in the bit field.
 542                     Range 0..15.
 543   @param  EndBit    The ordinal of the most significant bit in the bit field.
 544                     Range 0..15.
 545   @param  Value     New value of the bit field.
 546
 547   @return The value written back to the PCI configuration register.
 548
 549 **/
 550 UINT16
 551 EFIAPI
 552 PciExpressBitFieldWrite16 (
 553   IN      UINTN                     Address,
 554   IN      UINTN                     StartBit,
 555   IN      UINTN                     EndBit,
 556   IN      UINT16                    Value
 557   );
 558
 559 /**
 560   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 561   writes the result back to the bit field in the 16-bit port.
 562
 563   Reads the 16-bit PCI configuration register specified by Address, performs a
 564   bitwise inclusive OR between the read result and the value specified by
 565   OrData, and writes the result to the 16-bit PCI configuration register
 566   specified by Address. The value written to the PCI configuration register is
 567   returned. This function must guarantee that all PCI read and write operations
 568   are serialized. Extra left bits in OrData are stripped.
 569
 570   If Address > 0x0FFFFFFF, then ASSERT().
 571   If Address is not aligned on a 16-bit boundary, then ASSERT().
 572   If StartBit is greater than 15, then ASSERT().
 573   If EndBit is greater than 15, then ASSERT().
 574   If EndBit is less than StartBit, then ASSERT().
 575
 576   @param  Address   PCI configuration register to write.
 577   @param  StartBit  The ordinal of the least significant bit in the bit field.
 578                     Range 0..15.
 579   @param  EndBit    The ordinal of the most significant bit in the bit field.
 580                     Range 0..15.
 581   @param  OrData    The value to OR with the PCI configuration register.
 582
 583   @return The value written back to the PCI configuration register.
 584
 585 **/
 586 UINT16
 587 EFIAPI
 588 PciExpressBitFieldOr16 (
 589   IN      UINTN                     Address,
 590   IN      UINTN                     StartBit,
 591   IN      UINTN                     EndBit,
 592   IN      UINT16                    OrData
 593   );
 594
 595 /**
 596   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 597   AND, and writes the result back to the bit field in the 16-bit register.
 598
 599   Reads the 16-bit PCI configuration register specified by Address, performs a
 600   bitwise AND between the read result and the value specified by AndData, and
 601   writes the result to the 16-bit PCI configuration register specified by
 602   Address. The value written to the PCI configuration register is returned.
 603   This function must guarantee that all PCI read and write operations are
 604   serialized. Extra left bits in AndData are stripped.
 605
 606   If Address > 0x0FFFFFFF, then ASSERT().
 607   If Address is not aligned on a 16-bit boundary, then ASSERT().
 608   If StartBit is greater than 15, then ASSERT().
 609   If EndBit is greater than 15, then ASSERT().
 610   If EndBit is less than StartBit, then ASSERT().
 611
 612   @param  Address   PCI configuration register to write.
 613   @param  StartBit  The ordinal of the least significant bit in the bit field.
 614                     Range 0..15.
 615   @param  EndBit    The ordinal of the most significant bit in the bit field.
 616                     Range 0..15.
 617   @param  AndData   The value to AND with the PCI configuration register.
 618
 619   @return The value written back to the PCI configuration register.
 620
 621 **/
 622 UINT16
 623 EFIAPI
 624 PciExpressBitFieldAnd16 (
 625   IN      UINTN                     Address,
 626   IN      UINTN                     StartBit,
 627   IN      UINTN                     EndBit,
 628   IN      UINT16                    AndData
 629   );
 630
 631 /**
 632   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 633   bitwise inclusive OR, and writes the result back to the bit field in the
 634   16-bit port.
 635
 636   Reads the 16-bit PCI configuration register specified by Address, performs a
 637   bitwise AND followed by a bitwise inclusive OR between the read result and
 638   the value specified by AndData, and writes the result to the 16-bit PCI
 639   configuration register specified by Address. The value written to the PCI
 640   configuration register is returned. This function must guarantee that all PCI
 641   read and write operations are serialized. Extra left bits in both AndData and
 642   OrData are stripped.
 643
 644   If Address > 0x0FFFFFFF, then ASSERT().
 645   If Address is not aligned on a 16-bit boundary, then ASSERT().
 646   If StartBit is greater than 15, then ASSERT().
 647   If EndBit is greater than 15, then ASSERT().
 648   If EndBit is less than StartBit, then ASSERT().
 649
 650   @param  Address   PCI configuration register to write.
 651   @param  StartBit  The ordinal of the least significant bit in the bit field.
 652                     Range 0..15.
 653   @param  EndBit    The ordinal of the most significant bit in the bit field.
 654                     Range 0..15.
 655   @param  AndData   The value to AND with the PCI configuration register.
 656   @param  OrData    The value to OR with the result of the AND operation.
 657
 658   @return The value written back to the PCI configuration register.
 659
 660 **/
 661 UINT16
 662 EFIAPI
 663 PciExpressBitFieldAndThenOr16 (
 664   IN      UINTN                     Address,
 665   IN      UINTN                     StartBit,
 666   IN      UINTN                     EndBit,
 667   IN      UINT16                    AndData,
 668   IN      UINT16                    OrData
 669   );
 670
 671 /**
 672   Reads a 32-bit PCI configuration register.
 673
 674   Reads and returns the 32-bit PCI configuration register specified by Address.
 675   This function must guarantee that all PCI read and write operations are
 676   serialized.
 677
 678   If Address > 0x0FFFFFFF, then ASSERT().
 679   If Address is not aligned on a 32-bit boundary, then ASSERT().
 680
 681   @param  Address Address that encodes the PCI Bus, Device, Function and
 682                   Register.
 683
 684   @return The read value from the PCI configuration register.
 685
 686 **/
 687 UINT32
 688 EFIAPI
 689 PciExpressRead32 (
 690   IN      UINTN                     Address
 691   );
 692
 693 /**
 694   Writes a 32-bit PCI configuration register.
 695
 696   Writes the 32-bit PCI configuration register specified by Address with the
 697   value specified by Value. Value is returned. This function must guarantee
 698   that all PCI read and write operations are serialized.
 699
 700   If Address > 0x0FFFFFFF, then ASSERT().
 701   If Address is not aligned on a 32-bit boundary, then ASSERT().
 702
 703   @param  Address Address that encodes the PCI Bus, Device, Function and
 704                   Register.
 705   @param  Value   The value to write.
 706
 707   @return The value written to the PCI configuration register.
 708
 709 **/
 710 UINT32
 711 EFIAPI
 712 PciExpressWrite32 (
 713   IN      UINTN                     Address,
 714   IN      UINT32                    Value
 715   );
 716
 717 /**
 718   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 719   a 32-bit value.
 720
 721   Reads the 32-bit PCI configuration register specified by Address, performs a
 722   bitwise inclusive OR between the read result and the value specified by
 723   OrData, and writes the result to the 32-bit PCI configuration register
 724   specified by Address. The value written to the PCI configuration register is
 725   returned. This function must guarantee that all PCI read and write operations
 726   are serialized.
 727
 728   If Address > 0x0FFFFFFF, then ASSERT().
 729   If Address is not aligned on a 32-bit boundary, then ASSERT().
 730
 731   @param  Address Address that encodes the PCI Bus, Device, Function and
 732                   Register.
 733   @param  OrData  The value to OR with the PCI configuration register.
 734
 735   @return The value written back to the PCI configuration register.
 736
 737 **/
 738 UINT32
 739 EFIAPI
 740 PciExpressOr32 (
 741   IN      UINTN                     Address,
 742   IN      UINT32                    OrData
 743   );
 744
 745 /**
 746   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 747   value.
 748
 749   Reads the 32-bit PCI configuration register specified by Address, performs a
 750   bitwise AND between the read result and the value specified by AndData, and
 751   writes the result to the 32-bit PCI configuration register specified by
 752   Address. The value written to the PCI configuration register is returned.
 753   This function must guarantee that all PCI read and write operations are
 754   serialized.
 755
 756   If Address > 0x0FFFFFFF, then ASSERT().
 757   If Address is not aligned on a 32-bit boundary, then ASSERT().
 758
 759   @param  Address Address that encodes the PCI Bus, Device, Function and
 760                   Register.
 761   @param  AndData The value to AND with the PCI configuration register.
 762
 763   @return The value written back to the PCI configuration register.
 764
 765 **/
 766 UINT32
 767 EFIAPI
 768 PciExpressAnd32 (
 769   IN      UINTN                     Address,
 770   IN      UINT32                    AndData
 771   );
 772
 773 /**
 774   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 775   value, followed a  bitwise inclusive OR with another 32-bit value.
 776
 777   Reads the 32-bit PCI configuration register specified by Address, performs a
 778   bitwise AND between the read result and the value specified by AndData,
 779   performs a bitwise inclusive OR between the result of the AND operation and
 780   the value specified by OrData, and writes the result to the 32-bit PCI
 781   configuration register specified by Address. The value written to the PCI
 782   configuration register is returned. This function must guarantee that all PCI
 783   read and write operations are serialized.
 784
 785   If Address > 0x0FFFFFFF, then ASSERT().
 786   If Address is not aligned on a 32-bit boundary, then ASSERT().
 787
 788   @param  Address Address that encodes the PCI Bus, Device, Function and
 789                   Register.
 790   @param  AndData The value to AND with the PCI configuration register.
 791   @param  OrData  The value to OR with the result of the AND operation.
 792
 793   @return The value written back to the PCI configuration register.
 794
 795 **/
 796 UINT32
 797 EFIAPI
 798 PciExpressAndThenOr32 (
 799   IN      UINTN                     Address,
 800   IN      UINT32                    AndData,
 801   IN      UINT32                    OrData
 802   );
 803
 804 /**
 805   Reads a bit field of a PCI configuration register.
 806
 807   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 808   specified by the StartBit and the EndBit. The value of the bit field is
 809   returned.
 810
 811   If Address > 0x0FFFFFFF, then ASSERT().
 812   If Address is not aligned on a 32-bit boundary, then ASSERT().
 813   If StartBit is greater than 31, then ASSERT().
 814   If EndBit is greater than 31, then ASSERT().
 815   If EndBit is less than StartBit, then ASSERT().
 816
 817   @param  Address   PCI configuration register to read.
 818   @param  StartBit  The ordinal of the least significant bit in the bit field.
 819                     Range 0..31.
 820   @param  EndBit    The ordinal of the most significant bit in the bit field.
 821                     Range 0..31.
 822
 823   @return The value of the bit field read from the PCI configuration register.
 824
 825 **/
 826 UINT32
 827 EFIAPI
 828 PciExpressBitFieldRead32 (
 829   IN      UINTN                     Address,
 830   IN      UINTN                     StartBit,
 831   IN      UINTN                     EndBit
 832   );
 833
 834 /**
 835   Writes a bit field to a PCI configuration register.
 836
 837   Writes Value to the bit field of the PCI configuration register. The bit
 838   field is specified by the StartBit and the EndBit. All other bits in the
 839   destination PCI configuration register are preserved. The new value of the
 840   32-bit register is returned.
 841
 842   If Address > 0x0FFFFFFF, then ASSERT().
 843   If Address is not aligned on a 32-bit boundary, then ASSERT().
 844   If StartBit is greater than 31, then ASSERT().
 845   If EndBit is greater than 31, then ASSERT().
 846   If EndBit is less than StartBit, then ASSERT().
 847
 848   @param  Address   PCI configuration register to write.
 849   @param  StartBit  The ordinal of the least significant bit in the bit field.
 850                     Range 0..31.
 851   @param  EndBit    The ordinal of the most significant bit in the bit field.
 852                     Range 0..31.
 853   @param  Value     New value of the bit field.
 854
 855   @return The value written back to the PCI configuration register.
 856
 857 **/
 858 UINT32
 859 EFIAPI
 860 PciExpressBitFieldWrite32 (
 861   IN      UINTN                     Address,
 862   IN      UINTN                     StartBit,
 863   IN      UINTN                     EndBit,
 864   IN      UINT32                    Value
 865   );
 866
 867 /**
 868   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 869   writes the result back to the bit field in the 32-bit port.
 870
 871   Reads the 32-bit PCI configuration register specified by Address, performs a
 872   bitwise inclusive OR between the read result and the value specified by
 873   OrData, and writes the result to the 32-bit PCI configuration register
 874   specified by Address. The value written to the PCI configuration register is
 875   returned. This function must guarantee that all PCI read and write operations
 876   are serialized. Extra left bits in OrData are stripped.
 877
 878   If Address > 0x0FFFFFFF, then ASSERT().
 879   If Address is not aligned on a 32-bit boundary, then ASSERT().
 880   If StartBit is greater than 31, then ASSERT().
 881   If EndBit is greater than 31, then ASSERT().
 882   If EndBit is less than StartBit, then ASSERT().
 883
 884   @param  Address   PCI configuration register to write.
 885   @param  StartBit  The ordinal of the least significant bit in the bit field.
 886                     Range 0..31.
 887   @param  EndBit    The ordinal of the most significant bit in the bit field.
 888                     Range 0..31.
 889   @param  OrData    The value to OR with the PCI configuration register.
 890
 891   @return The value written back to the PCI configuration register.
 892
 893 **/
 894 UINT32
 895 EFIAPI
 896 PciExpressBitFieldOr32 (
 897   IN      UINTN                     Address,
 898   IN      UINTN                     StartBit,
 899   IN      UINTN                     EndBit,
 900   IN      UINT32                    OrData
 901   );
 902
 903 /**
 904   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 905   AND, and writes the result back to the bit field in the 32-bit register.
 906
 907   Reads the 32-bit PCI configuration register specified by Address, performs a
 908   bitwise AND between the read result and the value specified by AndData, and
 909   writes the result to the 32-bit PCI configuration register specified by
 910   Address. The value written to the PCI configuration register is returned.
 911   This function must guarantee that all PCI read and write operations are
 912   serialized. Extra left bits in AndData are stripped.
 913
 914   If Address > 0x0FFFFFFF, then ASSERT().
 915   If Address is not aligned on a 32-bit boundary, then ASSERT().
 916   If StartBit is greater than 31, then ASSERT().
 917   If EndBit is greater than 31, then ASSERT().
 918   If EndBit is less than StartBit, then ASSERT().
 919
 920   @param  Address   PCI configuration register to write.
 921   @param  StartBit  The ordinal of the least significant bit in the bit field.
 922                     Range 0..31.
 923   @param  EndBit    The ordinal of the most significant bit in the bit field.
 924                     Range 0..31.
 925   @param  AndData   The value to AND with the PCI configuration register.
 926
 927   @return The value written back to the PCI configuration register.
 928
 929 **/
 930 UINT32
 931 EFIAPI
 932 PciExpressBitFieldAnd32 (
 933   IN      UINTN                     Address,
 934   IN      UINTN                     StartBit,
 935   IN      UINTN                     EndBit,
 936   IN      UINT32                    AndData
 937   );
 938
 939 /**
 940   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 941   bitwise inclusive OR, and writes the result back to the bit field in the
 942   32-bit port.
 943
 944   Reads the 32-bit PCI configuration register specified by Address, performs a
 945   bitwise AND followed by a bitwise inclusive OR between the read result and
 946   the value specified by AndData, and writes the result to the 32-bit PCI
 947   configuration register specified by Address. The value written to the PCI
 948   configuration register is returned. This function must guarantee that all PCI
 949   read and write operations are serialized. Extra left bits in both AndData and
 950   OrData are stripped.
 951
 952   If Address > 0x0FFFFFFF, then ASSERT().
 953   If Address is not aligned on a 32-bit boundary, then ASSERT().
 954   If StartBit is greater than 31, then ASSERT().
 955   If EndBit is greater than 31, then ASSERT().
 956   If EndBit is less than StartBit, then ASSERT().
 957
 958   @param  Address   PCI configuration register to write.
 959   @param  StartBit  The ordinal of the least significant bit in the bit field.
 960                     Range 0..31.
 961   @param  EndBit    The ordinal of the most significant bit in the bit field.
 962                     Range 0..31.
 963   @param  AndData   The value to AND with the PCI configuration register.
 964   @param  OrData    The value to OR with the result of the AND operation.
 965
 966   @return The value written back to the PCI configuration register.
 967
 968 **/
 969 UINT32
 970 EFIAPI
 971 PciExpressBitFieldAndThenOr32 (
 972   IN      UINTN                     Address,
 973   IN      UINTN                     StartBit,
 974   IN      UINTN                     EndBit,
 975   IN      UINT32                    AndData,
 976   IN      UINT32                    OrData
 977   );
 978
 979 /**
 980   Reads a range of PCI configuration registers into a caller supplied buffer.
 981
 982   Reads the range of PCI configuration registers specified by StartAddress and
 983   Size into the buffer specified by Buffer. This function only allows the PCI
 984   configuration registers from a single PCI function to be read. Size is
 985   returned. When possible 32-bit PCI configuration read cycles are used to read
 986   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 987   and 16-bit PCI configuration read cycles may be used at the beginning and the
 988   end of the range.
 989
 990   If StartAddress > 0x0FFFFFFF, then ASSERT().
 991   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 992   If Size > 0 and Buffer is NULL, then ASSERT().
 993
 994   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 995                         Function and Register.
 996   @param  Size          Size in bytes of the transfer.
 997   @param  Buffer        Pointer to a buffer receiving the data read.
 998
 999   @return Size read data from StartAddress.
1000
1001 **/
1002 UINTN
1003 EFIAPI
1004 PciExpressReadBuffer (
1005   IN      UINTN                     StartAddress,
1006   IN      UINTN                     Size,
1007   OUT     VOID                      *Buffer
1008   );
1009
1010 /**
1011   Copies the data in a caller supplied buffer to a specified range of PCI
1012   configuration space.
1013
1014   Writes the range of PCI configuration registers specified by StartAddress and
1015   Size from the buffer specified by Buffer. This function only allows the PCI
1016   configuration registers from a single PCI function to be written. Size is
1017   returned. When possible 32-bit PCI configuration write cycles are used to
1018   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1019   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1020   and the end of the range.
1021
1022   If StartAddress > 0x0FFFFFFF, then ASSERT().
1023   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1024   If Size > 0 and Buffer is NULL, then ASSERT().
1025
1026   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1027                         Function and Register.
1028   @param  Size          Size in bytes of the transfer.
1029   @param  Buffer        Pointer to a buffer containing the data to write.
1030
1031   @return Size written to StartAddress.
1032
1033 **/
1034 UINTN
1035 EFIAPI
1036 PciExpressWriteBuffer (
1037   IN      UINTN                     StartAddress,
1038   IN      UINTN                     Size,
1039   IN      VOID                      *Buffer
1040   );
1041
1042 #endif