MdePkg/Include/Library/PciExpressLib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space using the MMIO PCI Express window.
   3
   4 Copyright (c) 2006 - 2008, Intel Corporation
   5 All rights reserved. This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __PCI_EXPRESS_LIB_H__
  16 #define __PCI_EXPRESS_LIB_H__
  17
  18 /**
  19   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  20   address that can be passed to the PCI Library functions.
  21
  22   Computes an address that is compatible with the PCI Library functions. The
  23   unused upper bits of Bus, Device, Function and Register are stripped prior to
  24   the generation of the address.
  25
  26   @param  Bus       PCI Bus number. Range 0..255.
  27   @param  Device    PCI Device number. Range 0..31.
  28   @param  Function  PCI Function number. Range 0..7.
  29   @param  Register  PCI Register number. Range 0..4095.
  30
  31   @return The encode PCI address.
  32
  33 **/
  34 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
  35   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  36
  37 /**
  38   Reads an 8-bit PCI configuration register.
  39
  40   Reads and returns the 8-bit PCI configuration register specified by Address.
  41   This function must guarantee that all PCI read and write operations are
  42   serialized.
  43
  44   If Address > 0x0FFFFFFF, then ASSERT().
  45
  46   @param  Address Address that encodes the PCI Bus, Device, Function and
  47                   Register.
  48
  49   @return The read value from the PCI configuration register.
  50
  51 **/
  52 UINT8
  53 EFIAPI
  54 PciExpressRead8 (
  55   IN      UINTN                     Address
  56   );
  57
  58 /**
  59   Writes an 8-bit PCI configuration register.
  60
  61   Writes the 8-bit PCI configuration register specified by Address with the
  62   value specified by Value. Value is returned. This function must guarantee
  63   that all PCI read and write operations are serialized.
  64
  65   If Address > 0x0FFFFFFF, then ASSERT().
  66
  67   @param  Address Address that encodes the PCI Bus, Device, Function and
  68                   Register.
  69   @param  Value   The value to write.
  70
  71   @return The value written to the PCI configuration register.
  72
  73 **/
  74 UINT8
  75 EFIAPI
  76 PciExpressWrite8 (
  77   IN      UINTN                     Address,
  78   IN      UINT8                     Value
  79   );
  80
  81 /**
  82   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  83   an 8-bit value.
  84
  85   Reads the 8-bit PCI configuration register specified by Address, performs a
  86   bitwise inclusive OR between the read result and the value specified by
  87   OrData, and writes the result to the 8-bit PCI configuration register
  88   specified by Address. The value written to the PCI configuration register is
  89   returned. This function must guarantee that all PCI read and write operations
  90   are serialized.
  91
  92   If Address > 0x0FFFFFFF, then ASSERT().
  93
  94   @param  Address Address that encodes the PCI Bus, Device, Function and
  95                   Register.
  96   @param  OrData  The value to OR with the PCI configuration register.
  97
  98   @return The value written back to the PCI configuration register.
  99
 100 **/
 101 UINT8
 102 EFIAPI
 103 PciExpressOr8 (
 104   IN      UINTN                     Address,
 105   IN      UINT8                     OrData
 106   );
 107
 108 /**
 109   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 110   value.
 111
 112   Reads the 8-bit PCI configuration register specified by Address, performs a
 113   bitwise AND between the read result and the value specified by AndData, and
 114   writes the result to the 8-bit PCI configuration register specified by
 115   Address. The value written to the PCI configuration register is returned.
 116   This function must guarantee that all PCI read and write operations are
 117   serialized.
 118
 119   If Address > 0x0FFFFFFF, then ASSERT().
 120
 121   @param  Address Address that encodes the PCI Bus, Device, Function and
 122                   Register.
 123   @param  AndData The value to AND with the PCI configuration register.
 124
 125   @return The value written back to the PCI configuration register.
 126
 127 **/
 128 UINT8
 129 EFIAPI
 130 PciExpressAnd8 (
 131   IN      UINTN                     Address,
 132   IN      UINT8                     AndData
 133   );
 134
 135 /**
 136   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 137   value, followed a  bitwise inclusive OR with another 8-bit value.
 138
 139   Reads the 8-bit PCI configuration register specified by Address, performs a
 140   bitwise AND between the read result and the value specified by AndData,
 141   performs a bitwise inclusive OR between the result of the AND operation and
 142   the value specified by OrData, and writes the result to the 8-bit PCI
 143   configuration register specified by Address. The value written to the PCI
 144   configuration register is returned. This function must guarantee that all PCI
 145   read and write operations are serialized.
 146
 147   If Address > 0x0FFFFFFF, then ASSERT().
 148
 149   @param  Address Address that encodes the PCI Bus, Device, Function and
 150                   Register.
 151   @param  AndData The value to AND with the PCI configuration register.
 152   @param  OrData  The value to OR with the result of the AND operation.
 153
 154   @return The value written back to the PCI configuration register.
 155
 156 **/
 157 UINT8
 158 EFIAPI
 159 PciExpressAndThenOr8 (
 160   IN      UINTN                     Address,
 161   IN      UINT8                     AndData,
 162   IN      UINT8                     OrData
 163   );
 164
 165 /**
 166   Reads a bit field of a PCI configuration register.
 167
 168   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 169   specified by the StartBit and the EndBit. The value of the bit field is
 170   returned.
 171
 172   If Address > 0x0FFFFFFF, then ASSERT().
 173   If StartBit is greater than 7, then ASSERT().
 174   If EndBit is greater than 7, then ASSERT().
 175   If EndBit is less than StartBit, then ASSERT().
 176
 177   @param  Address   PCI configuration register to read.
 178   @param  StartBit  The ordinal of the least significant bit in the bit field.
 179                     Range 0..7.
 180   @param  EndBit    The ordinal of the most significant bit in the bit field.
 181                     Range 0..7.
 182
 183   @return The value of the bit field read from the PCI configuration register.
 184
 185 **/
 186 UINT8
 187 EFIAPI
 188 PciExpressBitFieldRead8 (
 189   IN      UINTN                     Address,
 190   IN      UINTN                     StartBit,
 191   IN      UINTN                     EndBit
 192   );
 193
 194 /**
 195   Writes a bit field to a PCI configuration register.
 196
 197   Writes Value to the bit field of the PCI configuration register. The bit
 198   field is specified by the StartBit and the EndBit. All other bits in the
 199   destination PCI configuration register are preserved. The new value of the
 200   8-bit register is returned.
 201
 202   If Address > 0x0FFFFFFF, then ASSERT().
 203   If StartBit is greater than 7, then ASSERT().
 204   If EndBit is greater than 7, then ASSERT().
 205   If EndBit is less than StartBit, then ASSERT().
 206
 207   @param  Address   PCI configuration register to write.
 208   @param  StartBit  The ordinal of the least significant bit in the bit field.
 209                     Range 0..7.
 210   @param  EndBit    The ordinal of the most significant bit in the bit field.
 211                     Range 0..7.
 212   @param  Value     New value of the bit field.
 213
 214   @return The value written back to the PCI configuration register.
 215
 216 **/
 217 UINT8
 218 EFIAPI
 219 PciExpressBitFieldWrite8 (
 220   IN      UINTN                     Address,
 221   IN      UINTN                     StartBit,
 222   IN      UINTN                     EndBit,
 223   IN      UINT8                     Value
 224   );
 225
 226 /**
 227   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 228   writes the result back to the bit field in the 8-bit port.
 229
 230   Reads the 8-bit PCI configuration register specified by Address, performs a
 231   bitwise inclusive OR between the read result and the value specified by
 232   OrData, and writes the result to the 8-bit PCI configuration register
 233   specified by Address. The value written to the PCI configuration register is
 234   returned. This function must guarantee that all PCI read and write operations
 235   are serialized. Extra left bits in OrData are stripped.
 236
 237   If Address > 0x0FFFFFFF, then ASSERT().
 238   If StartBit is greater than 7, then ASSERT().
 239   If EndBit is greater than 7, then ASSERT().
 240   If EndBit is less than StartBit, then ASSERT().
 241
 242   @param  Address   PCI configuration register to write.
 243   @param  StartBit  The ordinal of the least significant bit in the bit field.
 244                     Range 0..7.
 245   @param  EndBit    The ordinal of the most significant bit in the bit field.
 246                     Range 0..7.
 247   @param  OrData    The value to OR with the PCI configuration register.
 248
 249   @return The value written back to the PCI configuration register.
 250
 251 **/
 252 UINT8
 253 EFIAPI
 254 PciExpressBitFieldOr8 (
 255   IN      UINTN                     Address,
 256   IN      UINTN                     StartBit,
 257   IN      UINTN                     EndBit,
 258   IN      UINT8                     OrData
 259   );
 260
 261 /**
 262   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 263   AND, and writes the result back to the bit field in the 8-bit register.
 264
 265   Reads the 8-bit PCI configuration register specified by Address, performs a
 266   bitwise AND between the read result and the value specified by AndData, and
 267   writes the result to the 8-bit PCI configuration register specified by
 268   Address. The value written to the PCI configuration register is returned.
 269   This function must guarantee that all PCI read and write operations are
 270   serialized. Extra left bits in AndData are stripped.
 271
 272   If Address > 0x0FFFFFFF, then ASSERT().
 273   If StartBit is greater than 7, then ASSERT().
 274   If EndBit is greater than 7, then ASSERT().
 275   If EndBit is less than StartBit, then ASSERT().
 276
 277   @param  Address   PCI configuration register to write.
 278   @param  StartBit  The ordinal of the least significant bit in the bit field.
 279                     Range 0..7.
 280   @param  EndBit    The ordinal of the most significant bit in the bit field.
 281                     Range 0..7.
 282   @param  AndData   The value to AND with the PCI configuration register.
 283
 284   @return The value written back to the PCI configuration register.
 285
 286 **/
 287 UINT8
 288 EFIAPI
 289 PciExpressBitFieldAnd8 (
 290   IN      UINTN                     Address,
 291   IN      UINTN                     StartBit,
 292   IN      UINTN                     EndBit,
 293   IN      UINT8                     AndData
 294   );
 295
 296 /**
 297   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 298   bitwise inclusive OR, and writes the result back to the bit field in the
 299   8-bit port.
 300
 301   Reads the 8-bit PCI configuration register specified by Address, performs a
 302   bitwise AND followed by a bitwise inclusive OR between the read result and
 303   the value specified by AndData, and writes the result to the 8-bit PCI
 304   configuration register specified by Address. The value written to the PCI
 305   configuration register is returned. This function must guarantee that all PCI
 306   read and write operations are serialized. Extra left bits in both AndData and
 307   OrData are stripped.
 308
 309   If Address > 0x0FFFFFFF, then ASSERT().
 310   If StartBit is greater than 7, then ASSERT().
 311   If EndBit is greater than 7, then ASSERT().
 312   If EndBit is less than StartBit, then ASSERT().
 313
 314   @param  Address   PCI configuration register to write.
 315   @param  StartBit  The ordinal of the least significant bit in the bit field.
 316                     Range 0..7.
 317   @param  EndBit    The ordinal of the most significant bit in the bit field.
 318                     Range 0..7.
 319   @param  AndData   The value to AND with the PCI configuration register.
 320   @param  OrData    The value to OR with the result of the AND operation.
 321
 322   @return The value written back to the PCI configuration register.
 323
 324 **/
 325 UINT8
 326 EFIAPI
 327 PciExpressBitFieldAndThenOr8 (
 328   IN      UINTN                     Address,
 329   IN      UINTN                     StartBit,
 330   IN      UINTN                     EndBit,
 331   IN      UINT8                     AndData,
 332   IN      UINT8                     OrData
 333   );
 334
 335 /**
 336   Reads a 16-bit PCI configuration register.
 337
 338   Reads and returns the 16-bit PCI configuration register specified by Address.
 339   This function must guarantee that all PCI read and write operations are
 340   serialized.
 341
 342   If Address > 0x0FFFFFFF, then ASSERT().
 343   If Address is not aligned on a 16-bit boundary, then ASSERT().
 344
 345   @param  Address Address that encodes the PCI Bus, Device, Function and
 346                   Register.
 347
 348   @return The read value from the PCI configuration register.
 349
 350 **/
 351 UINT16
 352 EFIAPI
 353 PciExpressRead16 (
 354   IN      UINTN                     Address
 355   );
 356
 357 /**
 358   Writes a 16-bit PCI configuration register.
 359
 360   Writes the 16-bit PCI configuration register specified by Address with the
 361   value specified by Value. Value is returned. This function must guarantee
 362   that all PCI read and write operations are serialized.
 363
 364   If Address > 0x0FFFFFFF, then ASSERT().
 365   If Address is not aligned on a 16-bit boundary, then ASSERT().
 366
 367   @param  Address Address that encodes the PCI Bus, Device, Function and
 368                   Register.
 369   @param  Value   The value to write.
 370
 371   @return The value written to the PCI configuration register.
 372
 373 **/
 374 UINT16
 375 EFIAPI
 376 PciExpressWrite16 (
 377   IN      UINTN                     Address,
 378   IN      UINT16                    Value
 379   );
 380
 381 /**
 382   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 383   a 16-bit value.
 384
 385   Reads the 16-bit PCI configuration register specified by Address, performs a
 386   bitwise inclusive OR between the read result and the value specified by
 387   OrData, and writes the result to the 16-bit PCI configuration register
 388   specified by Address. The value written to the PCI configuration register is
 389   returned. This function must guarantee that all PCI read and write operations
 390   are serialized.
 391
 392   If Address > 0x0FFFFFFF, then ASSERT().
 393   If Address is not aligned on a 16-bit boundary, then ASSERT().
 394
 395   @param  Address Address that encodes the PCI Bus, Device, Function and
 396                   Register.
 397   @param  OrData  The value to OR with the PCI configuration register.
 398
 399   @return The value written back to the PCI configuration register.
 400
 401 **/
 402 UINT16
 403 EFIAPI
 404 PciExpressOr16 (
 405   IN      UINTN                     Address,
 406   IN      UINT16                    OrData
 407   );
 408
 409 /**
 410   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 411   value.
 412
 413   Reads the 16-bit PCI configuration register specified by Address, performs a
 414   bitwise AND between the read result and the value specified by AndData, and
 415   writes the result to the 16-bit PCI configuration register specified by
 416   Address. The value written to the PCI configuration register is returned.
 417   This function must guarantee that all PCI read and write operations are
 418   serialized.
 419
 420   If Address > 0x0FFFFFFF, then ASSERT().
 421   If Address is not aligned on a 16-bit boundary, then ASSERT().
 422
 423   @param  Address Address that encodes the PCI Bus, Device, Function and
 424                   Register.
 425   @param  AndData The value to AND with the PCI configuration register.
 426
 427   @return The value written back to the PCI configuration register.
 428
 429 **/
 430 UINT16
 431 EFIAPI
 432 PciExpressAnd16 (
 433   IN      UINTN                     Address,
 434   IN      UINT16                    AndData
 435   );
 436
 437 /**
 438   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 439   value, followed a  bitwise inclusive OR with another 16-bit value.
 440
 441   Reads the 16-bit PCI configuration register specified by Address, performs a
 442   bitwise AND between the read result and the value specified by AndData,
 443   performs a bitwise inclusive OR between the result of the AND operation and
 444   the value specified by OrData, and writes the result to the 16-bit PCI
 445   configuration register specified by Address. The value written to the PCI
 446   configuration register is returned. This function must guarantee that all PCI
 447   read and write operations are serialized.
 448
 449   If Address > 0x0FFFFFFF, then ASSERT().
 450   If Address is not aligned on a 16-bit boundary, then ASSERT().
 451
 452   @param  Address Address that encodes the PCI Bus, Device, Function and
 453                   Register.
 454   @param  AndData The value to AND with the PCI configuration register.
 455   @param  OrData  The value to OR with the result of the AND operation.
 456
 457   @return The value written back to the PCI configuration register.
 458
 459 **/
 460 UINT16
 461 EFIAPI
 462 PciExpressAndThenOr16 (
 463   IN      UINTN                     Address,
 464   IN      UINT16                    AndData,
 465   IN      UINT16                    OrData
 466   );
 467
 468 /**
 469   Reads a bit field of a PCI configuration register.
 470
 471   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 472   specified by the StartBit and the EndBit. The value of the bit field is
 473   returned.
 474
 475   If Address > 0x0FFFFFFF, then ASSERT().
 476   If Address is not aligned on a 16-bit boundary, then ASSERT().
 477   If StartBit is greater than 15, then ASSERT().
 478   If EndBit is greater than 15, then ASSERT().
 479   If EndBit is less than StartBit, then ASSERT().
 480
 481   @param  Address   PCI configuration register to read.
 482   @param  StartBit  The ordinal of the least significant bit in the bit field.
 483                     Range 0..15.
 484   @param  EndBit    The ordinal of the most significant bit in the bit field.
 485                     Range 0..15.
 486
 487   @return The value of the bit field read from the PCI configuration register.
 488
 489 **/
 490 UINT16
 491 EFIAPI
 492 PciExpressBitFieldRead16 (
 493   IN      UINTN                     Address,
 494   IN      UINTN                     StartBit,
 495   IN      UINTN                     EndBit
 496   );
 497
 498 /**
 499   Writes a bit field to a PCI configuration register.
 500
 501   Writes Value to the bit field of the PCI configuration register. The bit
 502   field is specified by the StartBit and the EndBit. All other bits in the
 503   destination PCI configuration register are preserved. The new value of the
 504   16-bit register is returned.
 505
 506   If Address > 0x0FFFFFFF, then ASSERT().
 507   If Address is not aligned on a 16-bit boundary, then ASSERT().
 508   If StartBit is greater than 15, then ASSERT().
 509   If EndBit is greater than 15, then ASSERT().
 510   If EndBit is less than StartBit, then ASSERT().
 511
 512   @param  Address   PCI configuration register to write.
 513   @param  StartBit  The ordinal of the least significant bit in the bit field.
 514                     Range 0..15.
 515   @param  EndBit    The ordinal of the most significant bit in the bit field.
 516                     Range 0..15.
 517   @param  Value     New value of the bit field.
 518
 519   @return The value written back to the PCI configuration register.
 520
 521 **/
 522 UINT16
 523 EFIAPI
 524 PciExpressBitFieldWrite16 (
 525   IN      UINTN                     Address,
 526   IN      UINTN                     StartBit,
 527   IN      UINTN                     EndBit,
 528   IN      UINT16                    Value
 529   );
 530
 531 /**
 532   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 533   writes the result back to the bit field in the 16-bit port.
 534
 535   Reads the 16-bit PCI configuration register specified by Address, performs a
 536   bitwise inclusive OR between the read result and the value specified by
 537   OrData, and writes the result to the 16-bit PCI configuration register
 538   specified by Address. The value written to the PCI configuration register is
 539   returned. This function must guarantee that all PCI read and write operations
 540   are serialized. Extra left bits in OrData are stripped.
 541
 542   If Address > 0x0FFFFFFF, then ASSERT().
 543   If Address is not aligned on a 16-bit boundary, then ASSERT().
 544   If StartBit is greater than 15, then ASSERT().
 545   If EndBit is greater than 15, then ASSERT().
 546   If EndBit is less than StartBit, then ASSERT().
 547
 548   @param  Address   PCI configuration register to write.
 549   @param  StartBit  The ordinal of the least significant bit in the bit field.
 550                     Range 0..15.
 551   @param  EndBit    The ordinal of the most significant bit in the bit field.
 552                     Range 0..15.
 553   @param  OrData    The value to OR with the PCI configuration register.
 554
 555   @return The value written back to the PCI configuration register.
 556
 557 **/
 558 UINT16
 559 EFIAPI
 560 PciExpressBitFieldOr16 (
 561   IN      UINTN                     Address,
 562   IN      UINTN                     StartBit,
 563   IN      UINTN                     EndBit,
 564   IN      UINT16                    OrData
 565   );
 566
 567 /**
 568   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 569   AND, and writes the result back to the bit field in the 16-bit register.
 570
 571   Reads the 16-bit PCI configuration register specified by Address, performs a
 572   bitwise AND between the read result and the value specified by AndData, and
 573   writes the result to the 16-bit PCI configuration register specified by
 574   Address. The value written to the PCI configuration register is returned.
 575   This function must guarantee that all PCI read and write operations are
 576   serialized. Extra left bits in AndData are stripped.
 577
 578   If Address > 0x0FFFFFFF, then ASSERT().
 579   If Address is not aligned on a 16-bit boundary, then ASSERT().
 580   If StartBit is greater than 15, then ASSERT().
 581   If EndBit is greater than 15, then ASSERT().
 582   If EndBit is less than StartBit, then ASSERT().
 583
 584   @param  Address   PCI configuration register to write.
 585   @param  StartBit  The ordinal of the least significant bit in the bit field.
 586                     Range 0..15.
 587   @param  EndBit    The ordinal of the most significant bit in the bit field.
 588                     Range 0..15.
 589   @param  AndData   The value to AND with the PCI configuration register.
 590
 591   @return The value written back to the PCI configuration register.
 592
 593 **/
 594 UINT16
 595 EFIAPI
 596 PciExpressBitFieldAnd16 (
 597   IN      UINTN                     Address,
 598   IN      UINTN                     StartBit,
 599   IN      UINTN                     EndBit,
 600   IN      UINT16                    AndData
 601   );
 602
 603 /**
 604   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 605   bitwise inclusive OR, and writes the result back to the bit field in the
 606   16-bit port.
 607
 608   Reads the 16-bit PCI configuration register specified by Address, performs a
 609   bitwise AND followed by a bitwise inclusive OR between the read result and
 610   the value specified by AndData, and writes the result to the 16-bit PCI
 611   configuration register specified by Address. The value written to the PCI
 612   configuration register is returned. This function must guarantee that all PCI
 613   read and write operations are serialized. Extra left bits in both AndData and
 614   OrData are stripped.
 615
 616   If Address > 0x0FFFFFFF, then ASSERT().
 617   If Address is not aligned on a 16-bit boundary, then ASSERT().
 618   If StartBit is greater than 15, then ASSERT().
 619   If EndBit is greater than 15, then ASSERT().
 620   If EndBit is less than StartBit, then ASSERT().
 621
 622   @param  Address   PCI configuration register to write.
 623   @param  StartBit  The ordinal of the least significant bit in the bit field.
 624                     Range 0..15.
 625   @param  EndBit    The ordinal of the most significant bit in the bit field.
 626                     Range 0..15.
 627   @param  AndData   The value to AND with the PCI configuration register.
 628   @param  OrData    The value to OR with the result of the AND operation.
 629
 630   @return The value written back to the PCI configuration register.
 631
 632 **/
 633 UINT16
 634 EFIAPI
 635 PciExpressBitFieldAndThenOr16 (
 636   IN      UINTN                     Address,
 637   IN      UINTN                     StartBit,
 638   IN      UINTN                     EndBit,
 639   IN      UINT16                    AndData,
 640   IN      UINT16                    OrData
 641   );
 642
 643 /**
 644   Reads a 32-bit PCI configuration register.
 645
 646   Reads and returns the 32-bit PCI configuration register specified by Address.
 647   This function must guarantee that all PCI read and write operations are
 648   serialized.
 649
 650   If Address > 0x0FFFFFFF, then ASSERT().
 651   If Address is not aligned on a 32-bit boundary, then ASSERT().
 652
 653   @param  Address Address that encodes the PCI Bus, Device, Function and
 654                   Register.
 655
 656   @return The read value from the PCI configuration register.
 657
 658 **/
 659 UINT32
 660 EFIAPI
 661 PciExpressRead32 (
 662   IN      UINTN                     Address
 663   );
 664
 665 /**
 666   Writes a 32-bit PCI configuration register.
 667
 668   Writes the 32-bit PCI configuration register specified by Address with the
 669   value specified by Value. Value is returned. This function must guarantee
 670   that all PCI read and write operations are serialized.
 671
 672   If Address > 0x0FFFFFFF, then ASSERT().
 673   If Address is not aligned on a 32-bit boundary, then ASSERT().
 674
 675   @param  Address Address that encodes the PCI Bus, Device, Function and
 676                   Register.
 677   @param  Value   The value to write.
 678
 679   @return The value written to the PCI configuration register.
 680
 681 **/
 682 UINT32
 683 EFIAPI
 684 PciExpressWrite32 (
 685   IN      UINTN                     Address,
 686   IN      UINT32                    Value
 687   );
 688
 689 /**
 690   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 691   a 32-bit value.
 692
 693   Reads the 32-bit PCI configuration register specified by Address, performs a
 694   bitwise inclusive OR between the read result and the value specified by
 695   OrData, and writes the result to the 32-bit PCI configuration register
 696   specified by Address. The value written to the PCI configuration register is
 697   returned. This function must guarantee that all PCI read and write operations
 698   are serialized.
 699
 700   If Address > 0x0FFFFFFF, then ASSERT().
 701   If Address is not aligned on a 32-bit boundary, then ASSERT().
 702
 703   @param  Address Address that encodes the PCI Bus, Device, Function and
 704                   Register.
 705   @param  OrData  The value to OR with the PCI configuration register.
 706
 707   @return The value written back to the PCI configuration register.
 708
 709 **/
 710 UINT32
 711 EFIAPI
 712 PciExpressOr32 (
 713   IN      UINTN                     Address,
 714   IN      UINT32                    OrData
 715   );
 716
 717 /**
 718   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 719   value.
 720
 721   Reads the 32-bit PCI configuration register specified by Address, performs a
 722   bitwise AND between the read result and the value specified by AndData, and
 723   writes the result to the 32-bit PCI configuration register specified by
 724   Address. The value written to the PCI configuration register is returned.
 725   This function must guarantee that all PCI read and write operations are
 726   serialized.
 727
 728   If Address > 0x0FFFFFFF, then ASSERT().
 729   If Address is not aligned on a 32-bit boundary, then ASSERT().
 730
 731   @param  Address Address that encodes the PCI Bus, Device, Function and
 732                   Register.
 733   @param  AndData The value to AND with the PCI configuration register.
 734
 735   @return The value written back to the PCI configuration register.
 736
 737 **/
 738 UINT32
 739 EFIAPI
 740 PciExpressAnd32 (
 741   IN      UINTN                     Address,
 742   IN      UINT32                    AndData
 743   );
 744
 745 /**
 746   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 747   value, followed a  bitwise inclusive OR with another 32-bit value.
 748
 749   Reads the 32-bit PCI configuration register specified by Address, performs a
 750   bitwise AND between the read result and the value specified by AndData,
 751   performs a bitwise inclusive OR between the result of the AND operation and
 752   the value specified by OrData, and writes the result to the 32-bit PCI
 753   configuration register specified by Address. The value written to the PCI
 754   configuration register is returned. This function must guarantee that all PCI
 755   read and write operations are serialized.
 756
 757   If Address > 0x0FFFFFFF, then ASSERT().
 758   If Address is not aligned on a 32-bit boundary, then ASSERT().
 759
 760   @param  Address Address that encodes the PCI Bus, Device, Function and
 761                   Register.
 762   @param  AndData The value to AND with the PCI configuration register.
 763   @param  OrData  The value to OR with the result of the AND operation.
 764
 765   @return The value written back to the PCI configuration register.
 766
 767 **/
 768 UINT32
 769 EFIAPI
 770 PciExpressAndThenOr32 (
 771   IN      UINTN                     Address,
 772   IN      UINT32                    AndData,
 773   IN      UINT32                    OrData
 774   );
 775
 776 /**
 777   Reads a bit field of a PCI configuration register.
 778
 779   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 780   specified by the StartBit and the EndBit. The value of the bit field is
 781   returned.
 782
 783   If Address > 0x0FFFFFFF, then ASSERT().
 784   If Address is not aligned on a 32-bit boundary, then ASSERT().
 785   If StartBit is greater than 31, then ASSERT().
 786   If EndBit is greater than 31, then ASSERT().
 787   If EndBit is less than StartBit, then ASSERT().
 788
 789   @param  Address   PCI configuration register to read.
 790   @param  StartBit  The ordinal of the least significant bit in the bit field.
 791                     Range 0..31.
 792   @param  EndBit    The ordinal of the most significant bit in the bit field.
 793                     Range 0..31.
 794
 795   @return The value of the bit field read from the PCI configuration register.
 796
 797 **/
 798 UINT32
 799 EFIAPI
 800 PciExpressBitFieldRead32 (
 801   IN      UINTN                     Address,
 802   IN      UINTN                     StartBit,
 803   IN      UINTN                     EndBit
 804   );
 805
 806 /**
 807   Writes a bit field to a PCI configuration register.
 808
 809   Writes Value to the bit field of the PCI configuration register. The bit
 810   field is specified by the StartBit and the EndBit. All other bits in the
 811   destination PCI configuration register are preserved. The new value of the
 812   32-bit register is returned.
 813
 814   If Address > 0x0FFFFFFF, then ASSERT().
 815   If Address is not aligned on a 32-bit boundary, then ASSERT().
 816   If StartBit is greater than 31, then ASSERT().
 817   If EndBit is greater than 31, then ASSERT().
 818   If EndBit is less than StartBit, then ASSERT().
 819
 820   @param  Address   PCI configuration register to write.
 821   @param  StartBit  The ordinal of the least significant bit in the bit field.
 822                     Range 0..31.
 823   @param  EndBit    The ordinal of the most significant bit in the bit field.
 824                     Range 0..31.
 825   @param  Value     New value of the bit field.
 826
 827   @return The value written back to the PCI configuration register.
 828
 829 **/
 830 UINT32
 831 EFIAPI
 832 PciExpressBitFieldWrite32 (
 833   IN      UINTN                     Address,
 834   IN      UINTN                     StartBit,
 835   IN      UINTN                     EndBit,
 836   IN      UINT32                    Value
 837   );
 838
 839 /**
 840   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 841   writes the result back to the bit field in the 32-bit port.
 842
 843   Reads the 32-bit PCI configuration register specified by Address, performs a
 844   bitwise inclusive OR between the read result and the value specified by
 845   OrData, and writes the result to the 32-bit PCI configuration register
 846   specified by Address. The value written to the PCI configuration register is
 847   returned. This function must guarantee that all PCI read and write operations
 848   are serialized. Extra left bits in OrData are stripped.
 849
 850   If Address > 0x0FFFFFFF, then ASSERT().
 851   If Address is not aligned on a 32-bit boundary, then ASSERT().
 852   If StartBit is greater than 31, then ASSERT().
 853   If EndBit is greater than 31, then ASSERT().
 854   If EndBit is less than StartBit, then ASSERT().
 855
 856   @param  Address   PCI configuration register to write.
 857   @param  StartBit  The ordinal of the least significant bit in the bit field.
 858                     Range 0..31.
 859   @param  EndBit    The ordinal of the most significant bit in the bit field.
 860                     Range 0..31.
 861   @param  OrData    The value to OR with the PCI configuration register.
 862
 863   @return The value written back to the PCI configuration register.
 864
 865 **/
 866 UINT32
 867 EFIAPI
 868 PciExpressBitFieldOr32 (
 869   IN      UINTN                     Address,
 870   IN      UINTN                     StartBit,
 871   IN      UINTN                     EndBit,
 872   IN      UINT32                    OrData
 873   );
 874
 875 /**
 876   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 877   AND, and writes the result back to the bit field in the 32-bit register.
 878
 879   Reads the 32-bit PCI configuration register specified by Address, performs a
 880   bitwise AND between the read result and the value specified by AndData, and
 881   writes the result to the 32-bit PCI configuration register specified by
 882   Address. The value written to the PCI configuration register is returned.
 883   This function must guarantee that all PCI read and write operations are
 884   serialized. Extra left bits in AndData are stripped.
 885
 886   If Address > 0x0FFFFFFF, then ASSERT().
 887   If Address is not aligned on a 32-bit boundary, then ASSERT().
 888   If StartBit is greater than 31, then ASSERT().
 889   If EndBit is greater than 31, then ASSERT().
 890   If EndBit is less than StartBit, then ASSERT().
 891
 892   @param  Address   PCI configuration register to write.
 893   @param  StartBit  The ordinal of the least significant bit in the bit field.
 894                     Range 0..31.
 895   @param  EndBit    The ordinal of the most significant bit in the bit field.
 896                     Range 0..31.
 897   @param  AndData   The value to AND with the PCI configuration register.
 898
 899   @return The value written back to the PCI configuration register.
 900
 901 **/
 902 UINT32
 903 EFIAPI
 904 PciExpressBitFieldAnd32 (
 905   IN      UINTN                     Address,
 906   IN      UINTN                     StartBit,
 907   IN      UINTN                     EndBit,
 908   IN      UINT32                    AndData
 909   );
 910
 911 /**
 912   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 913   bitwise inclusive OR, and writes the result back to the bit field in the
 914   32-bit port.
 915
 916   Reads the 32-bit PCI configuration register specified by Address, performs a
 917   bitwise AND followed by a bitwise inclusive OR between the read result and
 918   the value specified by AndData, and writes the result to the 32-bit PCI
 919   configuration register specified by Address. The value written to the PCI
 920   configuration register is returned. This function must guarantee that all PCI
 921   read and write operations are serialized. Extra left bits in both AndData and
 922   OrData are stripped.
 923
 924   If Address > 0x0FFFFFFF, then ASSERT().
 925   If Address is not aligned on a 32-bit boundary, then ASSERT().
 926   If StartBit is greater than 31, then ASSERT().
 927   If EndBit is greater than 31, then ASSERT().
 928   If EndBit is less than StartBit, then ASSERT().
 929
 930   @param  Address   PCI configuration register to write.
 931   @param  StartBit  The ordinal of the least significant bit in the bit field.
 932                     Range 0..31.
 933   @param  EndBit    The ordinal of the most significant bit in the bit field.
 934                     Range 0..31.
 935   @param  AndData   The value to AND with the PCI configuration register.
 936   @param  OrData    The value to OR with the result of the AND operation.
 937
 938   @return The value written back to the PCI configuration register.
 939
 940 **/
 941 UINT32
 942 EFIAPI
 943 PciExpressBitFieldAndThenOr32 (
 944   IN      UINTN                     Address,
 945   IN      UINTN                     StartBit,
 946   IN      UINTN                     EndBit,
 947   IN      UINT32                    AndData,
 948   IN      UINT32                    OrData
 949   );
 950
 951 /**
 952   Reads a range of PCI configuration registers into a caller supplied buffer.
 953
 954   Reads the range of PCI configuration registers specified by StartAddress and
 955   Size into the buffer specified by Buffer. This function only allows the PCI
 956   configuration registers from a single PCI function to be read. Size is
 957   returned. When possible 32-bit PCI configuration read cycles are used to read
 958   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 959   and 16-bit PCI configuration read cycles may be used at the beginning and the
 960   end of the range.
 961
 962   If StartAddress > 0x0FFFFFFF, then ASSERT().
 963   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 964   If Size > 0 and Buffer is NULL, then ASSERT().
 965
 966   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 967                         Function and Register.
 968   @param  Size          Size in bytes of the transfer.
 969   @param  Buffer        Pointer to a buffer receiving the data read.
 970
 971   @return Size read daata from StartAddress.
 972
 973 **/
 974 UINTN
 975 EFIAPI
 976 PciExpressReadBuffer (
 977   IN      UINTN                     StartAddress,
 978   IN      UINTN                     Size,
 979   OUT     VOID                      *Buffer
 980   );
 981
 982 /**
 983   Copies the data in a caller supplied buffer to a specified range of PCI
 984   configuration space.
 985
 986   Writes the range of PCI configuration registers specified by StartAddress and
 987   Size from the buffer specified by Buffer. This function only allows the PCI
 988   configuration registers from a single PCI function to be written. Size is
 989   returned. When possible 32-bit PCI configuration write cycles are used to
 990   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
 991   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
 992   and the end of the range.
 993
 994   If StartAddress > 0x0FFFFFFF, then ASSERT().
 995   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 996   If Size > 0 and Buffer is NULL, then ASSERT().
 997
 998   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 999                         Function and Register.
1000   @param  Size          Size in bytes of the transfer.
1001   @param  Buffer        Pointer to a buffer containing the data to write.
1002
1003   @return Size written to StartAddress.
1004
1005 **/
1006 UINTN
1007 EFIAPI
1008 PciExpressWriteBuffer (
1009   IN      UINTN                     StartAddress,
1010   IN      UINTN                     Size,
1011   IN      VOID                      *Buffer
1012   );
1013
1014 #endif