MdePkg/Include/Library/PciLib.h

   1 /** @file
   2   PCI Library Services for PCI Segment #0
   3
   4   Copyright (c) 2006 - 2008, Intel Corporation
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef __PCI_LIB_H__
  16 #define __PCI_LIB_H__
  17
  18 /**
  19   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  20   address that can be passed to the PCI Library functions.
  21
  22   @param  Bus       PCI Bus number. Range 0..255.
  23   @param  Device    PCI Device number. Range 0..31.
  24   @param  Function  PCI Function number. Range 0..7.
  25   @param  Register  PCI Register number. Range 0..255 for PCI. Range 0..4095
  26                     for PCI Express.
  27
  28   @return The encoded PCI address.
  29
  30 **/
  31 #define PCI_LIB_ADDRESS(Bus,Device,Function,Offset)   \
  32   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  33
  34 /**
  35   Reads an 8-bit PCI configuration register.
  36
  37   Reads and returns the 8-bit PCI configuration register specified by Address.
  38   This function must guarantee that all PCI read and write operations are
  39   serialized.
  40
  41   If Address > 0x0FFFFFFF, then ASSERT().
  42
  43   @param  Address Address that encodes the PCI Bus, Device, Function and
  44                   Register.
  45
  46   @return The read value from the PCI configuration register.
  47
  48 **/
  49 UINT8
  50 EFIAPI
  51 PciRead8 (
  52   IN      UINTN                     Address
  53   );
  54
  55 /**
  56   Writes an 8-bit PCI configuration register.
  57
  58   Writes the 8-bit PCI configuration register specified by Address with the
  59   value specified by Value. Value is returned. This function must guarantee
  60   that all PCI read and write operations are serialized.
  61
  62   If Address > 0x0FFFFFFF, then ASSERT().
  63
  64   @param  Address Address that encodes the PCI Bus, Device, Function and
  65                   Register.
  66   @param  Value   The value to write.
  67
  68   @return The value written to the PCI configuration register.
  69
  70 **/
  71 UINT8
  72 EFIAPI
  73 PciWrite8 (
  74   IN      UINTN                     Address,
  75   IN      UINT8                     Value
  76   );
  77
  78 /**
  79   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  80   an 8-bit value.
  81
  82   Reads the 8-bit PCI configuration register specified by Address, performs a
  83   bitwise inclusive OR between the read result and the value specified by
  84   OrData, and writes the result to the 8-bit PCI configuration register
  85   specified by Address. The value written to the PCI configuration register is
  86   returned. This function must guarantee that all PCI read and write operations
  87   are serialized.
  88
  89   If Address > 0x0FFFFFFF, then ASSERT().
  90
  91   @param  Address Address that encodes the PCI Bus, Device, Function and
  92                   Register.
  93   @param  OrData  The value to OR with the PCI configuration register.
  94
  95   @return The value written back to the PCI configuration register.
  96
  97 **/
  98 UINT8
  99 EFIAPI
 100 PciOr8 (
 101   IN      UINTN                     Address,
 102   IN      UINT8                     OrData
 103   );
 104
 105 /**
 106   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 107   value.
 108
 109   Reads the 8-bit PCI configuration register specified by Address, performs a
 110   bitwise AND between the read result and the value specified by AndData, and
 111   writes the result to the 8-bit PCI configuration register specified by
 112   Address. The value written to the PCI configuration register is returned.
 113   This function must guarantee that all PCI read and write operations are
 114   serialized.
 115
 116   If Address > 0x0FFFFFFF, then ASSERT().
 117
 118   @param  Address Address that encodes the PCI Bus, Device, Function and
 119                   Register.
 120   @param  AndData The value to AND with the PCI configuration register.
 121
 122   @return The value written back to the PCI configuration register.
 123
 124 **/
 125 UINT8
 126 EFIAPI
 127 PciAnd8 (
 128   IN      UINTN                     Address,
 129   IN      UINT8                     AndData
 130   );
 131
 132 /**
 133   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 134   value, followed a  bitwise inclusive OR with another 8-bit value.
 135
 136   Reads the 8-bit PCI configuration register specified by Address, performs a
 137   bitwise AND between the read result and the value specified by AndData,
 138   performs a bitwise inclusive OR between the result of the AND operation and
 139   the value specified by OrData, and writes the result to the 8-bit PCI
 140   configuration register specified by Address. The value written to the PCI
 141   configuration register is returned. This function must guarantee that all PCI
 142   read and write operations are serialized.
 143
 144   If Address > 0x0FFFFFFF, then ASSERT().
 145
 146   @param  Address Address that encodes the PCI Bus, Device, Function and
 147                   Register.
 148   @param  AndData The value to AND with the PCI configuration register.
 149   @param  OrData  The value to OR with the result of the AND operation.
 150
 151   @return The value written back to the PCI configuration register.
 152
 153 **/
 154 UINT8
 155 EFIAPI
 156 PciAndThenOr8 (
 157   IN      UINTN                     Address,
 158   IN      UINT8                     AndData,
 159   IN      UINT8                     OrData
 160   );
 161
 162 /**
 163   Reads a bit field of a PCI configuration register.
 164
 165   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 166   specified by the StartBit and the EndBit. The value of the bit field is
 167   returned.
 168
 169   If Address > 0x0FFFFFFF, then ASSERT().
 170   If StartBit is greater than 7, then ASSERT().
 171   If EndBit is greater than 7, then ASSERT().
 172   If EndBit is less than StartBit, then ASSERT().
 173
 174   @param  Address   PCI configuration register to read.
 175   @param  StartBit  The ordinal of the least significant bit in the bit field.
 176                     Range 0..7.
 177   @param  EndBit    The ordinal of the most significant bit in the bit field.
 178                     Range 0..7.
 179
 180   @return The value of the bit field read from the PCI configuration register.
 181
 182 **/
 183 UINT8
 184 EFIAPI
 185 PciBitFieldRead8 (
 186   IN      UINTN                     Address,
 187   IN      UINTN                     StartBit,
 188   IN      UINTN                     EndBit
 189   );
 190
 191 /**
 192   Writes a bit field to a PCI configuration register.
 193
 194   Writes Value to the bit field of the PCI configuration register. The bit
 195   field is specified by the StartBit and the EndBit. All other bits in the
 196   destination PCI configuration register are preserved. The new value of the
 197   8-bit register is returned.
 198
 199   If Address > 0x0FFFFFFF, then ASSERT().
 200   If StartBit is greater than 7, then ASSERT().
 201   If EndBit is greater than 7, then ASSERT().
 202   If EndBit is less than StartBit, then ASSERT().
 203
 204   @param  Address   PCI configuration register to write.
 205   @param  StartBit  The ordinal of the least significant bit in the bit field.
 206                     Range 0..7.
 207   @param  EndBit    The ordinal of the most significant bit in the bit field.
 208                     Range 0..7.
 209   @param  Value     New value of the bit field.
 210
 211   @return The value written back to the PCI configuration register.
 212
 213 **/
 214 UINT8
 215 EFIAPI
 216 PciBitFieldWrite8 (
 217   IN      UINTN                     Address,
 218   IN      UINTN                     StartBit,
 219   IN      UINTN                     EndBit,
 220   IN      UINT8                     Value
 221   );
 222
 223 /**
 224   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 225   writes the result back to the bit field in the 8-bit port.
 226
 227   Reads the 8-bit PCI configuration register specified by Address, performs a
 228   bitwise inclusive OR between the read result and the value specified by
 229   OrData, and writes the result to the 8-bit PCI configuration register
 230   specified by Address. The value written to the PCI configuration register is
 231   returned. This function must guarantee that all PCI read and write operations
 232   are serialized. Extra left bits in OrData are stripped.
 233
 234   If Address > 0x0FFFFFFF, then ASSERT().
 235   If StartBit is greater than 7, then ASSERT().
 236   If EndBit is greater than 7, then ASSERT().
 237   If EndBit is less than StartBit, then ASSERT().
 238
 239   @param  Address   PCI configuration register to write.
 240   @param  StartBit  The ordinal of the least significant bit in the bit field.
 241                     Range 0..7.
 242   @param  EndBit    The ordinal of the most significant bit in the bit field.
 243                     Range 0..7.
 244   @param  OrData    The value to OR with the PCI configuration register.
 245
 246   @return The value written back to the PCI configuration register.
 247
 248 **/
 249 UINT8
 250 EFIAPI
 251 PciBitFieldOr8 (
 252   IN      UINTN                     Address,
 253   IN      UINTN                     StartBit,
 254   IN      UINTN                     EndBit,
 255   IN      UINT8                     OrData
 256   );
 257
 258 /**
 259   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 260   AND, and writes the result back to the bit field in the 8-bit register.
 261
 262   Reads the 8-bit PCI configuration register specified by Address, performs a
 263   bitwise AND between the read result and the value specified by AndData, and
 264   writes the result to the 8-bit PCI configuration register specified by
 265   Address. The value written to the PCI configuration register is returned.
 266   This function must guarantee that all PCI read and write operations are
 267   serialized. Extra left bits in AndData are stripped.
 268
 269   If Address > 0x0FFFFFFF, then ASSERT().
 270   If StartBit is greater than 7, then ASSERT().
 271   If EndBit is greater than 7, then ASSERT().
 272   If EndBit is less than StartBit, then ASSERT().
 273
 274   @param  Address   PCI configuration register to write.
 275   @param  StartBit  The ordinal of the least significant bit in the bit field.
 276                     Range 0..7.
 277   @param  EndBit    The ordinal of the most significant bit in the bit field.
 278                     Range 0..7.
 279   @param  AndData   The value to AND with the PCI configuration register.
 280
 281   @return The value written back to the PCI configuration register.
 282
 283 **/
 284 UINT8
 285 EFIAPI
 286 PciBitFieldAnd8 (
 287   IN      UINTN                     Address,
 288   IN      UINTN                     StartBit,
 289   IN      UINTN                     EndBit,
 290   IN      UINT8                     AndData
 291   );
 292
 293 /**
 294   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 295   bitwise inclusive OR, and writes the result back to the bit field in the
 296   8-bit port.
 297
 298   Reads the 8-bit PCI configuration register specified by Address, performs a
 299   bitwise AND followed by a bitwise inclusive OR between the read result and
 300   the value specified by AndData, and writes the result to the 8-bit PCI
 301   configuration register specified by Address. The value written to the PCI
 302   configuration register is returned. This function must guarantee that all PCI
 303   read and write operations are serialized. Extra left bits in both AndData and
 304   OrData are stripped.
 305
 306   If Address > 0x0FFFFFFF, then ASSERT().
 307   If StartBit is greater than 7, then ASSERT().
 308   If EndBit is greater than 7, then ASSERT().
 309   If EndBit is less than StartBit, then ASSERT().
 310
 311   @param  Address   PCI configuration register to write.
 312   @param  StartBit  The ordinal of the least significant bit in the bit field.
 313                     Range 0..7.
 314   @param  EndBit    The ordinal of the most significant bit in the bit field.
 315                     Range 0..7.
 316   @param  AndData   The value to AND with the PCI configuration register.
 317   @param  OrData    The value to OR with the result of the AND operation.
 318
 319   @return The value written back to the PCI configuration register.
 320
 321 **/
 322 UINT8
 323 EFIAPI
 324 PciBitFieldAndThenOr8 (
 325   IN      UINTN                     Address,
 326   IN      UINTN                     StartBit,
 327   IN      UINTN                     EndBit,
 328   IN      UINT8                     AndData,
 329   IN      UINT8                     OrData
 330   );
 331
 332 /**
 333   Reads a 16-bit PCI configuration register.
 334
 335   Reads and returns the 16-bit PCI configuration register specified by Address.
 336   This function must guarantee that all PCI read and write operations are
 337   serialized.
 338
 339   If Address > 0x0FFFFFFF, then ASSERT().
 340   If Address is not aligned on a 16-bit boundary, then ASSERT().
 341
 342   @param  Address Address that encodes the PCI Bus, Device, Function and
 343                   Register.
 344
 345   @return The read value from the PCI configuration register.
 346
 347 **/
 348 UINT16
 349 EFIAPI
 350 PciRead16 (
 351   IN      UINTN                     Address
 352   );
 353
 354 /**
 355   Writes a 16-bit PCI configuration register.
 356
 357   Writes the 16-bit PCI configuration register specified by Address with the
 358   value specified by Value. Value is returned. This function must guarantee
 359   that all PCI read and write operations are serialized.
 360
 361   If Address > 0x0FFFFFFF, then ASSERT().
 362   If Address is not aligned on a 16-bit boundary, then ASSERT().
 363
 364   @param  Address Address that encodes the PCI Bus, Device, Function and
 365                   Register.
 366   @param  Value   The value to write.
 367
 368   @return The value written to the PCI configuration register.
 369
 370 **/
 371 UINT16
 372 EFIAPI
 373 PciWrite16 (
 374   IN      UINTN                     Address,
 375   IN      UINT16                    Value
 376   );
 377
 378 /**
 379   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 380   a 16-bit value.
 381
 382   Reads the 16-bit PCI configuration register specified by Address, performs a
 383   bitwise inclusive OR between the read result and the value specified by
 384   OrData, and writes the result to the 16-bit PCI configuration register
 385   specified by Address. The value written to the PCI configuration register is
 386   returned. This function must guarantee that all PCI read and write operations
 387   are serialized.
 388
 389   If Address > 0x0FFFFFFF, then ASSERT().
 390   If Address is not aligned on a 16-bit boundary, then ASSERT().
 391
 392   @param  Address Address that encodes the PCI Bus, Device, Function and
 393                   Register.
 394   @param  OrData  The value to OR with the PCI configuration register.
 395
 396   @return The value written back to the PCI configuration register.
 397
 398 **/
 399 UINT16
 400 EFIAPI
 401 PciOr16 (
 402   IN      UINTN                     Address,
 403   IN      UINT16                    OrData
 404   );
 405
 406 /**
 407   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 408   value.
 409
 410   Reads the 16-bit PCI configuration register specified by Address, performs a
 411   bitwise AND between the read result and the value specified by AndData, and
 412   writes the result to the 16-bit PCI configuration register specified by
 413   Address. The value written to the PCI configuration register is returned.
 414   This function must guarantee that all PCI read and write operations are
 415   serialized.
 416
 417   If Address > 0x0FFFFFFF, then ASSERT().
 418   If Address is not aligned on a 16-bit boundary, then ASSERT().
 419
 420   @param  Address Address that encodes the PCI Bus, Device, Function and
 421                   Register.
 422   @param  AndData The value to AND with the PCI configuration register.
 423
 424   @return The value written back to the PCI configuration register.
 425
 426 **/
 427 UINT16
 428 EFIAPI
 429 PciAnd16 (
 430   IN      UINTN                     Address,
 431   IN      UINT16                    AndData
 432   );
 433
 434 /**
 435   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 436   value, followed a  bitwise inclusive OR with another 16-bit value.
 437
 438   Reads the 16-bit PCI configuration register specified by Address, performs a
 439   bitwise AND between the read result and the value specified by AndData,
 440   performs a bitwise inclusive OR between the result of the AND operation and
 441   the value specified by OrData, and writes the result to the 16-bit PCI
 442   configuration register specified by Address. The value written to the PCI
 443   configuration register is returned. This function must guarantee that all PCI
 444   read and write operations are serialized.
 445
 446   If Address > 0x0FFFFFFF, then ASSERT().
 447   If Address is not aligned on a 16-bit boundary, then ASSERT().
 448
 449   @param  Address Address that encodes the PCI Bus, Device, Function and
 450                   Register.
 451   @param  AndData The value to AND with the PCI configuration register.
 452   @param  OrData  The value to OR with the result of the AND operation.
 453
 454   @return The value written back to the PCI configuration register.
 455
 456 **/
 457 UINT16
 458 EFIAPI
 459 PciAndThenOr16 (
 460   IN      UINTN                     Address,
 461   IN      UINT16                    AndData,
 462   IN      UINT16                    OrData
 463   );
 464
 465 /**
 466   Reads a bit field of a PCI configuration register.
 467
 468   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 469   specified by the StartBit and the EndBit. The value of the bit field is
 470   returned.
 471
 472   If Address > 0x0FFFFFFF, then ASSERT().
 473   If Address is not aligned on a 16-bit boundary, then ASSERT().
 474   If StartBit is greater than 15, then ASSERT().
 475   If EndBit is greater than 15, then ASSERT().
 476   If EndBit is less than StartBit, then ASSERT().
 477
 478   @param  Address   PCI configuration register to read.
 479   @param  StartBit  The ordinal of the least significant bit in the bit field.
 480                     Range 0..15.
 481   @param  EndBit    The ordinal of the most significant bit in the bit field.
 482                     Range 0..15.
 483
 484   @return The value of the bit field read from the PCI configuration register.
 485
 486 **/
 487 UINT16
 488 EFIAPI
 489 PciBitFieldRead16 (
 490   IN      UINTN                     Address,
 491   IN      UINTN                     StartBit,
 492   IN      UINTN                     EndBit
 493   );
 494
 495 /**
 496   Writes a bit field to a PCI configuration register.
 497
 498   Writes Value to the bit field of the PCI configuration register. The bit
 499   field is specified by the StartBit and the EndBit. All other bits in the
 500   destination PCI configuration register are preserved. The new value of the
 501   16-bit register is returned.
 502
 503   If Address > 0x0FFFFFFF, then ASSERT().
 504   If Address is not aligned on a 16-bit boundary, then ASSERT().
 505   If StartBit is greater than 15, then ASSERT().
 506   If EndBit is greater than 15, then ASSERT().
 507   If EndBit is less than StartBit, then ASSERT().
 508
 509   @param  Address   PCI configuration register to write.
 510   @param  StartBit  The ordinal of the least significant bit in the bit field.
 511                     Range 0..15.
 512   @param  EndBit    The ordinal of the most significant bit in the bit field.
 513                     Range 0..15.
 514   @param  Value     New value of the bit field.
 515
 516   @return The value written back to the PCI configuration register.
 517
 518 **/
 519 UINT16
 520 EFIAPI
 521 PciBitFieldWrite16 (
 522   IN      UINTN                     Address,
 523   IN      UINTN                     StartBit,
 524   IN      UINTN                     EndBit,
 525   IN      UINT16                    Value
 526   );
 527
 528 /**
 529   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 530   writes the result back to the bit field in the 16-bit port.
 531
 532   Reads the 16-bit PCI configuration register specified by Address, performs a
 533   bitwise inclusive OR between the read result and the value specified by
 534   OrData, and writes the result to the 16-bit PCI configuration register
 535   specified by Address. The value written to the PCI configuration register is
 536   returned. This function must guarantee that all PCI read and write operations
 537   are serialized. Extra left bits in OrData are stripped.
 538
 539   If Address > 0x0FFFFFFF, then ASSERT().
 540   If Address is not aligned on a 16-bit boundary, then ASSERT().
 541   If StartBit is greater than 15, then ASSERT().
 542   If EndBit is greater than 15, then ASSERT().
 543   If EndBit is less than StartBit, then ASSERT().
 544
 545   @param  Address   PCI configuration register to write.
 546   @param  StartBit  The ordinal of the least significant bit in the bit field.
 547                     Range 0..15.
 548   @param  EndBit    The ordinal of the most significant bit in the bit field.
 549                     Range 0..15.
 550   @param  OrData    The value to OR with the PCI configuration register.
 551
 552   @return The value written back to the PCI configuration register.
 553
 554 **/
 555 UINT16
 556 EFIAPI
 557 PciBitFieldOr16 (
 558   IN      UINTN                     Address,
 559   IN      UINTN                     StartBit,
 560   IN      UINTN                     EndBit,
 561   IN      UINT16                    OrData
 562   );
 563
 564 /**
 565   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 566   AND, and writes the result back to the bit field in the 16-bit register.
 567
 568   Reads the 16-bit PCI configuration register specified by Address, performs a
 569   bitwise AND between the read result and the value specified by AndData, and
 570   writes the result to the 16-bit PCI configuration register specified by
 571   Address. The value written to the PCI configuration register is returned.
 572   This function must guarantee that all PCI read and write operations are
 573   serialized. Extra left bits in AndData are stripped.
 574
 575   If Address > 0x0FFFFFFF, then ASSERT().
 576   If Address is not aligned on a 16-bit boundary, then ASSERT().
 577   If StartBit is greater than 15, then ASSERT().
 578   If EndBit is greater than 15, then ASSERT().
 579   If EndBit is less than StartBit, then ASSERT().
 580
 581   @param  Address   PCI configuration register to write.
 582   @param  StartBit  The ordinal of the least significant bit in the bit field.
 583                     Range 0..15.
 584   @param  EndBit    The ordinal of the most significant bit in the bit field.
 585                     Range 0..15.
 586   @param  AndData   The value to AND with the PCI configuration register.
 587
 588   @return The value written back to the PCI configuration register.
 589
 590 **/
 591 UINT16
 592 EFIAPI
 593 PciBitFieldAnd16 (
 594   IN      UINTN                     Address,
 595   IN      UINTN                     StartBit,
 596   IN      UINTN                     EndBit,
 597   IN      UINT16                    AndData
 598   );
 599
 600 /**
 601   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 602   bitwise inclusive OR, and writes the result back to the bit field in the
 603   16-bit port.
 604
 605   Reads the 16-bit PCI configuration register specified by Address, performs a
 606   bitwise AND followed by a bitwise inclusive OR between the read result and
 607   the value specified by AndData, and writes the result to the 16-bit PCI
 608   configuration register specified by Address. The value written to the PCI
 609   configuration register is returned. This function must guarantee that all PCI
 610   read and write operations are serialized. Extra left bits in both AndData and
 611   OrData are stripped.
 612
 613   If Address > 0x0FFFFFFF, then ASSERT().
 614   If Address is not aligned on a 16-bit boundary, then ASSERT().
 615   If StartBit is greater than 15, then ASSERT().
 616   If EndBit is greater than 15, then ASSERT().
 617   If EndBit is less than StartBit, then ASSERT().
 618
 619   @param  Address   PCI configuration register to write.
 620   @param  StartBit  The ordinal of the least significant bit in the bit field.
 621                     Range 0..15.
 622   @param  EndBit    The ordinal of the most significant bit in the bit field.
 623                     Range 0..15.
 624   @param  AndData   The value to AND with the PCI configuration register.
 625   @param  OrData    The value to OR with the result of the AND operation.
 626
 627   @return The value written back to the PCI configuration register.
 628
 629 **/
 630 UINT16
 631 EFIAPI
 632 PciBitFieldAndThenOr16 (
 633   IN      UINTN                     Address,
 634   IN      UINTN                     StartBit,
 635   IN      UINTN                     EndBit,
 636   IN      UINT16                    AndData,
 637   IN      UINT16                    OrData
 638   );
 639
 640 /**
 641   Reads a 32-bit PCI configuration register.
 642
 643   Reads and returns the 32-bit PCI configuration register specified by Address.
 644   This function must guarantee that all PCI read and write operations are
 645   serialized.
 646
 647   If Address > 0x0FFFFFFF, then ASSERT().
 648   If Address is not aligned on a 32-bit boundary, then ASSERT().
 649
 650   @param  Address Address that encodes the PCI Bus, Device, Function and
 651                   Register.
 652
 653   @return The read value from the PCI configuration register.
 654
 655 **/
 656 UINT32
 657 EFIAPI
 658 PciRead32 (
 659   IN      UINTN                     Address
 660   );
 661
 662 /**
 663   Writes a 32-bit PCI configuration register.
 664
 665   Writes the 32-bit PCI configuration register specified by Address with the
 666   value specified by Value. Value is returned. This function must guarantee
 667   that all PCI read and write operations are serialized.
 668
 669   If Address > 0x0FFFFFFF, then ASSERT().
 670   If Address is not aligned on a 32-bit boundary, then ASSERT().
 671
 672   @param  Address Address that encodes the PCI Bus, Device, Function and
 673                   Register.
 674   @param  Value   The value to write.
 675
 676   @return The value written to the PCI configuration register.
 677
 678 **/
 679 UINT32
 680 EFIAPI
 681 PciWrite32 (
 682   IN      UINTN                     Address,
 683   IN      UINT32                    Value
 684   );
 685
 686 /**
 687   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 688   a 32-bit value.
 689
 690   Reads the 32-bit PCI configuration register specified by Address, performs a
 691   bitwise inclusive OR between the read result and the value specified by
 692   OrData, and writes the result to the 32-bit PCI configuration register
 693   specified by Address. The value written to the PCI configuration register is
 694   returned. This function must guarantee that all PCI read and write operations
 695   are serialized.
 696
 697   If Address > 0x0FFFFFFF, then ASSERT().
 698   If Address is not aligned on a 32-bit boundary, then ASSERT().
 699
 700   @param  Address Address that encodes the PCI Bus, Device, Function and
 701                   Register.
 702   @param  OrData  The value to OR with the PCI configuration register.
 703
 704   @return The value written back to the PCI configuration register.
 705
 706 **/
 707 UINT32
 708 EFIAPI
 709 PciOr32 (
 710   IN      UINTN                     Address,
 711   IN      UINT32                    OrData
 712   );
 713
 714 /**
 715   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 716   value.
 717
 718   Reads the 32-bit PCI configuration register specified by Address, performs a
 719   bitwise AND between the read result and the value specified by AndData, and
 720   writes the result to the 32-bit PCI configuration register specified by
 721   Address. The value written to the PCI configuration register is returned.
 722   This function must guarantee that all PCI read and write operations are
 723   serialized.
 724
 725   If Address > 0x0FFFFFFF, then ASSERT().
 726   If Address is not aligned on a 32-bit boundary, then ASSERT().
 727
 728   @param  Address Address that encodes the PCI Bus, Device, Function and
 729                   Register.
 730   @param  AndData The value to AND with the PCI configuration register.
 731
 732   @return The value written back to the PCI configuration register.
 733
 734 **/
 735 UINT32
 736 EFIAPI
 737 PciAnd32 (
 738   IN      UINTN                     Address,
 739   IN      UINT32                    AndData
 740   );
 741
 742 /**
 743   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 744   value, followed a  bitwise inclusive OR with another 32-bit value.
 745
 746   Reads the 32-bit PCI configuration register specified by Address, performs a
 747   bitwise AND between the read result and the value specified by AndData,
 748   performs a bitwise inclusive OR between the result of the AND operation and
 749   the value specified by OrData, and writes the result to the 32-bit PCI
 750   configuration register specified by Address. The value written to the PCI
 751   configuration register is returned. This function must guarantee that all PCI
 752   read and write operations are serialized.
 753
 754   If Address > 0x0FFFFFFF, then ASSERT().
 755   If Address is not aligned on a 32-bit boundary, then ASSERT().
 756
 757   @param  Address Address that encodes the PCI Bus, Device, Function and
 758                   Register.
 759   @param  AndData The value to AND with the PCI configuration register.
 760   @param  OrData  The value to OR with the result of the AND operation.
 761
 762   @return The value written back to the PCI configuration register.
 763
 764 **/
 765 UINT32
 766 EFIAPI
 767 PciAndThenOr32 (
 768   IN      UINTN                     Address,
 769   IN      UINT32                    AndData,
 770   IN      UINT32                    OrData
 771   );
 772
 773 /**
 774   Reads a bit field of a PCI configuration register.
 775
 776   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 777   specified by the StartBit and the EndBit. The value of the bit field is
 778   returned.
 779
 780   If Address > 0x0FFFFFFF, then ASSERT().
 781   If Address is not aligned on a 32-bit boundary, then ASSERT().
 782   If StartBit is greater than 31, then ASSERT().
 783   If EndBit is greater than 31, then ASSERT().
 784   If EndBit is less than StartBit, then ASSERT().
 785
 786   @param  Address   PCI configuration register to read.
 787   @param  StartBit  The ordinal of the least significant bit in the bit field.
 788                     Range 0..31.
 789   @param  EndBit    The ordinal of the most significant bit in the bit field.
 790                     Range 0..31.
 791
 792   @return The value of the bit field read from the PCI configuration register.
 793
 794 **/
 795 UINT32
 796 EFIAPI
 797 PciBitFieldRead32 (
 798   IN      UINTN                     Address,
 799   IN      UINTN                     StartBit,
 800   IN      UINTN                     EndBit
 801   );
 802
 803 /**
 804   Writes a bit field to a PCI configuration register.
 805
 806   Writes Value to the bit field of the PCI configuration register. The bit
 807   field is specified by the StartBit and the EndBit. All other bits in the
 808   destination PCI configuration register are preserved. The new value of the
 809   32-bit register is returned.
 810
 811   If Address > 0x0FFFFFFF, then ASSERT().
 812   If Address is not aligned on a 32-bit boundary, then ASSERT().
 813   If StartBit is greater than 31, then ASSERT().
 814   If EndBit is greater than 31, then ASSERT().
 815   If EndBit is less than StartBit, then ASSERT().
 816
 817   @param  Address   PCI configuration register to write.
 818   @param  StartBit  The ordinal of the least significant bit in the bit field.
 819                     Range 0..31.
 820   @param  EndBit    The ordinal of the most significant bit in the bit field.
 821                     Range 0..31.
 822   @param  Value     New value of the bit field.
 823
 824   @return The value written back to the PCI configuration register.
 825
 826 **/
 827 UINT32
 828 EFIAPI
 829 PciBitFieldWrite32 (
 830   IN      UINTN                     Address,
 831   IN      UINTN                     StartBit,
 832   IN      UINTN                     EndBit,
 833   IN      UINT32                    Value
 834   );
 835
 836 /**
 837   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 838   writes the result back to the bit field in the 32-bit port.
 839
 840   Reads the 32-bit PCI configuration register specified by Address, performs a
 841   bitwise inclusive OR between the read result and the value specified by
 842   OrData, and writes the result to the 32-bit PCI configuration register
 843   specified by Address. The value written to the PCI configuration register is
 844   returned. This function must guarantee that all PCI read and write operations
 845   are serialized. Extra left bits in OrData are stripped.
 846
 847   If Address > 0x0FFFFFFF, then ASSERT().
 848   If Address is not aligned on a 32-bit boundary, then ASSERT().
 849   If StartBit is greater than 31, then ASSERT().
 850   If EndBit is greater than 31, then ASSERT().
 851   If EndBit is less than StartBit, then ASSERT().
 852
 853   @param  Address   PCI configuration register to write.
 854   @param  StartBit  The ordinal of the least significant bit in the bit field.
 855                     Range 0..31.
 856   @param  EndBit    The ordinal of the most significant bit in the bit field.
 857                     Range 0..31.
 858   @param  OrData    The value to OR with the PCI configuration register.
 859
 860   @return The value written back to the PCI configuration register.
 861
 862 **/
 863 UINT32
 864 EFIAPI
 865 PciBitFieldOr32 (
 866   IN      UINTN                     Address,
 867   IN      UINTN                     StartBit,
 868   IN      UINTN                     EndBit,
 869   IN      UINT32                    OrData
 870   );
 871
 872 /**
 873   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 874   AND, and writes the result back to the bit field in the 32-bit register.
 875
 876   Reads the 32-bit PCI configuration register specified by Address, performs a
 877   bitwise AND between the read result and the value specified by AndData, and
 878   writes the result to the 32-bit PCI configuration register specified by
 879   Address. The value written to the PCI configuration register is returned.
 880   This function must guarantee that all PCI read and write operations are
 881   serialized. Extra left bits in AndData are stripped.
 882
 883   If Address > 0x0FFFFFFF, then ASSERT().
 884   If Address is not aligned on a 32-bit boundary, then ASSERT().
 885   If StartBit is greater than 31, then ASSERT().
 886   If EndBit is greater than 31, then ASSERT().
 887   If EndBit is less than StartBit, then ASSERT().
 888
 889   @param  Address   PCI configuration register to write.
 890   @param  StartBit  The ordinal of the least significant bit in the bit field.
 891                     Range 0..31.
 892   @param  EndBit    The ordinal of the most significant bit in the bit field.
 893                     Range 0..31.
 894   @param  AndData   The value to AND with the PCI configuration register.
 895
 896   @return The value written back to the PCI configuration register.
 897
 898 **/
 899 UINT32
 900 EFIAPI
 901 PciBitFieldAnd32 (
 902   IN      UINTN                     Address,
 903   IN      UINTN                     StartBit,
 904   IN      UINTN                     EndBit,
 905   IN      UINT32                    AndData
 906   );
 907
 908 /**
 909   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 910   bitwise inclusive OR, and writes the result back to the bit field in the
 911   32-bit port.
 912
 913   Reads the 32-bit PCI configuration register specified by Address, performs a
 914   bitwise AND followed by a bitwise inclusive OR between the read result and
 915   the value specified by AndData, and writes the result to the 32-bit PCI
 916   configuration register specified by Address. The value written to the PCI
 917   configuration register is returned. This function must guarantee that all PCI
 918   read and write operations are serialized. Extra left bits in both AndData and
 919   OrData are stripped.
 920
 921   If Address > 0x0FFFFFFF, then ASSERT().
 922   If Address is not aligned on a 32-bit boundary, then ASSERT().
 923   If StartBit is greater than 31, then ASSERT().
 924   If EndBit is greater than 31, then ASSERT().
 925   If EndBit is less than StartBit, then ASSERT().
 926
 927   @param  Address   PCI configuration register to write.
 928   @param  StartBit  The ordinal of the least significant bit in the bit field.
 929                     Range 0..31.
 930   @param  EndBit    The ordinal of the most significant bit in the bit field.
 931                     Range 0..31.
 932   @param  AndData   The value to AND with the PCI configuration register.
 933   @param  OrData    The value to OR with the result of the AND operation.
 934
 935   @return The value written back to the PCI configuration register.
 936
 937 **/
 938 UINT32
 939 EFIAPI
 940 PciBitFieldAndThenOr32 (
 941   IN      UINTN                     Address,
 942   IN      UINTN                     StartBit,
 943   IN      UINTN                     EndBit,
 944   IN      UINT32                    AndData,
 945   IN      UINT32                    OrData
 946   );
 947
 948 /**
 949   Reads a range of PCI configuration registers into a caller supplied buffer.
 950
 951   Reads the range of PCI configuration registers specified by StartAddress and
 952   Size into the buffer specified by Buffer. This function only allows the PCI
 953   configuration registers from a single PCI function to be read. Size is
 954   returned. When possible 32-bit PCI configuration read cycles are used to read
 955   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 956   and 16-bit PCI configuration read cycles may be used at the beginning and the
 957   end of the range.
 958
 959   If StartAddress > 0x0FFFFFFF, then ASSERT().
 960   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 961   If Size > 0 and Buffer is NULL, then ASSERT().
 962
 963   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 964                         Function and Register.
 965   @param  Size          Size in bytes of the transfer.
 966   @param  Buffer        Pointer to a buffer receiving the data read.
 967
 968   @return Size
 969
 970 **/
 971 UINTN
 972 EFIAPI
 973 PciReadBuffer (
 974   IN      UINTN                     StartAddress,
 975   IN      UINTN                     Size,
 976   OUT     VOID                      *Buffer
 977   );
 978
 979 /**
 980   Copies the data in a caller supplied buffer to a specified range of PCI
 981   configuration space.
 982
 983   Writes the range of PCI configuration registers specified by StartAddress and
 984   Size from the buffer specified by Buffer. This function only allows the PCI
 985   configuration registers from a single PCI function to be written. Size is
 986   returned. When possible 32-bit PCI configuration write cycles are used to
 987   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
 988   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
 989   and the end of the range.
 990
 991   If StartAddress > 0x0FFFFFFF, then ASSERT().
 992   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 993   If Size > 0 and Buffer is NULL, then ASSERT().
 994
 995   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 996                         Function and Register.
 997   @param  Size          Size in bytes of the transfer.
 998   @param  Buffer        Pointer to a buffer containing the data to write.
 999
1000   @return Size written to StartAddress.
1001
1002 **/
1003 UINTN
1004 EFIAPI
1005 PciWriteBuffer (
1006   IN      UINTN                     StartAddress,
1007   IN      UINTN                     Size,
1008   IN      VOID                      *Buffer
1009   );
1010
1011 #endif