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2 Provides services to access PCI Configuration Space.
4 These functions perform PCI configuration cycles using the default PCI configuration
5 access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
6 or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some
7 alternate access method. Modules will typically use the PCI Library for its PCI configuration
8 accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or
9 PCI Express Library may be used in conjunction with the PCI Library. The functionality of
10 these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use
11 explicit access methods.
13 Copyright (c) 2006 - 2008, Intel Corporation
14 All rights reserved. This program and the accompanying materials
15 are licensed and made available under the terms and conditions of the BSD License
16 which accompanies this distribution. The full text of the license may be found at
17 http://opensource.org/licenses/bsd-license.php
19 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
20 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
28 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
29 address that can be passed to the PCI Library functions.
31 @param Bus PCI Bus number. Range 0..255.
32 @param Device PCI Device number. Range 0..31.
33 @param Function PCI Function number. Range 0..7.
34 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095
37 @return The encoded PCI address.
40 #define PCI_LIB_ADDRESS(Bus,Device,Function,Offset) \
41 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
44 Reads an 8-bit PCI configuration register.
46 Reads and returns the 8-bit PCI configuration register specified by Address.
47 This function must guarantee that all PCI read and write operations are
50 If Address > 0x0FFFFFFF, then ASSERT().
52 @param Address Address that encodes the PCI Bus, Device, Function and
55 @return The read value from the PCI configuration register.
65 Writes an 8-bit PCI configuration register.
67 Writes the 8-bit PCI configuration register specified by Address with the
68 value specified by Value. Value is returned. This function must guarantee
69 that all PCI read and write operations are serialized.
71 If Address > 0x0FFFFFFF, then ASSERT().
73 @param Address Address that encodes the PCI Bus, Device, Function and
75 @param Value The value to write.
77 @return The value written to the PCI configuration register.
88 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
91 Reads the 8-bit PCI configuration register specified by Address, performs a
92 bitwise inclusive OR between the read result and the value specified by
93 OrData, and writes the result to the 8-bit PCI configuration register
94 specified by Address. The value written to the PCI configuration register is
95 returned. This function must guarantee that all PCI read and write operations
98 If Address > 0x0FFFFFFF, then ASSERT().
100 @param Address Address that encodes the PCI Bus, Device, Function and
102 @param OrData The value to OR with the PCI configuration register.
104 @return The value written back to the PCI configuration register.
115 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
118 Reads the 8-bit PCI configuration register specified by Address, performs a
119 bitwise AND between the read result and the value specified by AndData, and
120 writes the result to the 8-bit PCI configuration register specified by
121 Address. The value written to the PCI configuration register is returned.
122 This function must guarantee that all PCI read and write operations are
125 If Address > 0x0FFFFFFF, then ASSERT().
127 @param Address Address that encodes the PCI Bus, Device, Function and
129 @param AndData The value to AND with the PCI configuration register.
131 @return The value written back to the PCI configuration register.
142 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
143 value, followed a bitwise inclusive OR with another 8-bit value.
145 Reads the 8-bit PCI configuration register specified by Address, performs a
146 bitwise AND between the read result and the value specified by AndData,
147 performs a bitwise inclusive OR between the result of the AND operation and
148 the value specified by OrData, and writes the result to the 8-bit PCI
149 configuration register specified by Address. The value written to the PCI
150 configuration register is returned. This function must guarantee that all PCI
151 read and write operations are serialized.
153 If Address > 0x0FFFFFFF, then ASSERT().
155 @param Address Address that encodes the PCI Bus, Device, Function and
157 @param AndData The value to AND with the PCI configuration register.
158 @param OrData The value to OR with the result of the AND operation.
160 @return The value written back to the PCI configuration register.
172 Reads a bit field of a PCI configuration register.
174 Reads the bit field in an 8-bit PCI configuration register. The bit field is
175 specified by the StartBit and the EndBit. The value of the bit field is
178 If Address > 0x0FFFFFFF, then ASSERT().
179 If StartBit is greater than 7, then ASSERT().
180 If EndBit is greater than 7, then ASSERT().
181 If EndBit is less than StartBit, then ASSERT().
183 @param Address PCI configuration register to read.
184 @param StartBit The ordinal of the least significant bit in the bit field.
186 @param EndBit The ordinal of the most significant bit in the bit field.
189 @return The value of the bit field read from the PCI configuration register.
201 Writes a bit field to a PCI configuration register.
203 Writes Value to the bit field of the PCI configuration register. The bit
204 field is specified by the StartBit and the EndBit. All other bits in the
205 destination PCI configuration register are preserved. The new value of the
206 8-bit register is returned.
208 If Address > 0x0FFFFFFF, then ASSERT().
209 If StartBit is greater than 7, then ASSERT().
210 If EndBit is greater than 7, then ASSERT().
211 If EndBit is less than StartBit, then ASSERT().
213 @param Address PCI configuration register to write.
214 @param StartBit The ordinal of the least significant bit in the bit field.
216 @param EndBit The ordinal of the most significant bit in the bit field.
218 @param Value New value of the bit field.
220 @return The value written back to the PCI configuration register.
233 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
234 writes the result back to the bit field in the 8-bit port.
236 Reads the 8-bit PCI configuration register specified by Address, performs a
237 bitwise inclusive OR between the read result and the value specified by
238 OrData, and writes the result to the 8-bit PCI configuration register
239 specified by Address. The value written to the PCI configuration register is
240 returned. This function must guarantee that all PCI read and write operations
241 are serialized. Extra left bits in OrData are stripped.
243 If Address > 0x0FFFFFFF, then ASSERT().
244 If StartBit is greater than 7, then ASSERT().
245 If EndBit is greater than 7, then ASSERT().
246 If EndBit is less than StartBit, then ASSERT().
248 @param Address PCI configuration register to write.
249 @param StartBit The ordinal of the least significant bit in the bit field.
251 @param EndBit The ordinal of the most significant bit in the bit field.
253 @param OrData The value to OR with the PCI configuration register.
255 @return The value written back to the PCI configuration register.
268 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
269 AND, and writes the result back to the bit field in the 8-bit register.
271 Reads the 8-bit PCI configuration register specified by Address, performs a
272 bitwise AND between the read result and the value specified by AndData, and
273 writes the result to the 8-bit PCI configuration register specified by
274 Address. The value written to the PCI configuration register is returned.
275 This function must guarantee that all PCI read and write operations are
276 serialized. Extra left bits in AndData are stripped.
278 If Address > 0x0FFFFFFF, then ASSERT().
279 If StartBit is greater than 7, then ASSERT().
280 If EndBit is greater than 7, then ASSERT().
281 If EndBit is less than StartBit, then ASSERT().
283 @param Address PCI configuration register to write.
284 @param StartBit The ordinal of the least significant bit in the bit field.
286 @param EndBit The ordinal of the most significant bit in the bit field.
288 @param AndData The value to AND with the PCI configuration register.
290 @return The value written back to the PCI configuration register.
303 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
304 bitwise inclusive OR, and writes the result back to the bit field in the
307 Reads the 8-bit PCI configuration register specified by Address, performs a
308 bitwise AND followed by a bitwise inclusive OR between the read result and
309 the value specified by AndData, and writes the result to the 8-bit PCI
310 configuration register specified by Address. The value written to the PCI
311 configuration register is returned. This function must guarantee that all PCI
312 read and write operations are serialized. Extra left bits in both AndData and
315 If Address > 0x0FFFFFFF, then ASSERT().
316 If StartBit is greater than 7, then ASSERT().
317 If EndBit is greater than 7, then ASSERT().
318 If EndBit is less than StartBit, then ASSERT().
320 @param Address PCI configuration register to write.
321 @param StartBit The ordinal of the least significant bit in the bit field.
323 @param EndBit The ordinal of the most significant bit in the bit field.
325 @param AndData The value to AND with the PCI configuration register.
326 @param OrData The value to OR with the result of the AND operation.
328 @return The value written back to the PCI configuration register.
333 PciBitFieldAndThenOr8 (
342 Reads a 16-bit PCI configuration register.
344 Reads and returns the 16-bit PCI configuration register specified by Address.
345 This function must guarantee that all PCI read and write operations are
348 If Address > 0x0FFFFFFF, then ASSERT().
349 If Address is not aligned on a 16-bit boundary, then ASSERT().
351 @param Address Address that encodes the PCI Bus, Device, Function and
354 @return The read value from the PCI configuration register.
364 Writes a 16-bit PCI configuration register.
366 Writes the 16-bit PCI configuration register specified by Address with the
367 value specified by Value. Value is returned. This function must guarantee
368 that all PCI read and write operations are serialized.
370 If Address > 0x0FFFFFFF, then ASSERT().
371 If Address is not aligned on a 16-bit boundary, then ASSERT().
373 @param Address Address that encodes the PCI Bus, Device, Function and
375 @param Value The value to write.
377 @return The value written to the PCI configuration register.
388 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
391 Reads the 16-bit PCI configuration register specified by Address, performs a
392 bitwise inclusive OR between the read result and the value specified by
393 OrData, and writes the result to the 16-bit PCI configuration register
394 specified by Address. The value written to the PCI configuration register is
395 returned. This function must guarantee that all PCI read and write operations
398 If Address > 0x0FFFFFFF, then ASSERT().
399 If Address is not aligned on a 16-bit boundary, then ASSERT().
401 @param Address Address that encodes the PCI Bus, Device, Function and
403 @param OrData The value to OR with the PCI configuration register.
405 @return The value written back to the PCI configuration register.
416 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
419 Reads the 16-bit PCI configuration register specified by Address, performs a
420 bitwise AND between the read result and the value specified by AndData, and
421 writes the result to the 16-bit PCI configuration register specified by
422 Address. The value written to the PCI configuration register is returned.
423 This function must guarantee that all PCI read and write operations are
426 If Address > 0x0FFFFFFF, then ASSERT().
427 If Address is not aligned on a 16-bit boundary, then ASSERT().
429 @param Address Address that encodes the PCI Bus, Device, Function and
431 @param AndData The value to AND with the PCI configuration register.
433 @return The value written back to the PCI configuration register.
444 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
445 value, followed a bitwise inclusive OR with another 16-bit value.
447 Reads the 16-bit PCI configuration register specified by Address, performs a
448 bitwise AND between the read result and the value specified by AndData,
449 performs a bitwise inclusive OR between the result of the AND operation and
450 the value specified by OrData, and writes the result to the 16-bit PCI
451 configuration register specified by Address. The value written to the PCI
452 configuration register is returned. This function must guarantee that all PCI
453 read and write operations are serialized.
455 If Address > 0x0FFFFFFF, then ASSERT().
456 If Address is not aligned on a 16-bit boundary, then ASSERT().
458 @param Address Address that encodes the PCI Bus, Device, Function and
460 @param AndData The value to AND with the PCI configuration register.
461 @param OrData The value to OR with the result of the AND operation.
463 @return The value written back to the PCI configuration register.
475 Reads a bit field of a PCI configuration register.
477 Reads the bit field in a 16-bit PCI configuration register. The bit field is
478 specified by the StartBit and the EndBit. The value of the bit field is
481 If Address > 0x0FFFFFFF, then ASSERT().
482 If Address is not aligned on a 16-bit boundary, then ASSERT().
483 If StartBit is greater than 15, then ASSERT().
484 If EndBit is greater than 15, then ASSERT().
485 If EndBit is less than StartBit, then ASSERT().
487 @param Address PCI configuration register to read.
488 @param StartBit The ordinal of the least significant bit in the bit field.
490 @param EndBit The ordinal of the most significant bit in the bit field.
493 @return The value of the bit field read from the PCI configuration register.
505 Writes a bit field to a PCI configuration register.
507 Writes Value to the bit field of the PCI configuration register. The bit
508 field is specified by the StartBit and the EndBit. All other bits in the
509 destination PCI configuration register are preserved. The new value of the
510 16-bit register is returned.
512 If Address > 0x0FFFFFFF, then ASSERT().
513 If Address is not aligned on a 16-bit boundary, then ASSERT().
514 If StartBit is greater than 15, then ASSERT().
515 If EndBit is greater than 15, then ASSERT().
516 If EndBit is less than StartBit, then ASSERT().
518 @param Address PCI configuration register to write.
519 @param StartBit The ordinal of the least significant bit in the bit field.
521 @param EndBit The ordinal of the most significant bit in the bit field.
523 @param Value New value of the bit field.
525 @return The value written back to the PCI configuration register.
538 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
539 writes the result back to the bit field in the 16-bit port.
541 Reads the 16-bit PCI configuration register specified by Address, performs a
542 bitwise inclusive OR between the read result and the value specified by
543 OrData, and writes the result to the 16-bit PCI configuration register
544 specified by Address. The value written to the PCI configuration register is
545 returned. This function must guarantee that all PCI read and write operations
546 are serialized. Extra left bits in OrData are stripped.
548 If Address > 0x0FFFFFFF, then ASSERT().
549 If Address is not aligned on a 16-bit boundary, then ASSERT().
550 If StartBit is greater than 15, then ASSERT().
551 If EndBit is greater than 15, then ASSERT().
552 If EndBit is less than StartBit, then ASSERT().
554 @param Address PCI configuration register to write.
555 @param StartBit The ordinal of the least significant bit in the bit field.
557 @param EndBit The ordinal of the most significant bit in the bit field.
559 @param OrData The value to OR with the PCI configuration register.
561 @return The value written back to the PCI configuration register.
574 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
575 AND, and writes the result back to the bit field in the 16-bit register.
577 Reads the 16-bit PCI configuration register specified by Address, performs a
578 bitwise AND between the read result and the value specified by AndData, and
579 writes the result to the 16-bit PCI configuration register specified by
580 Address. The value written to the PCI configuration register is returned.
581 This function must guarantee that all PCI read and write operations are
582 serialized. Extra left bits in AndData are stripped.
584 If Address > 0x0FFFFFFF, then ASSERT().
585 If Address is not aligned on a 16-bit boundary, then ASSERT().
586 If StartBit is greater than 15, then ASSERT().
587 If EndBit is greater than 15, then ASSERT().
588 If EndBit is less than StartBit, then ASSERT().
590 @param Address PCI configuration register to write.
591 @param StartBit The ordinal of the least significant bit in the bit field.
593 @param EndBit The ordinal of the most significant bit in the bit field.
595 @param AndData The value to AND with the PCI configuration register.
597 @return The value written back to the PCI configuration register.
610 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
611 bitwise inclusive OR, and writes the result back to the bit field in the
614 Reads the 16-bit PCI configuration register specified by Address, performs a
615 bitwise AND followed by a bitwise inclusive OR between the read result and
616 the value specified by AndData, and writes the result to the 16-bit PCI
617 configuration register specified by Address. The value written to the PCI
618 configuration register is returned. This function must guarantee that all PCI
619 read and write operations are serialized. Extra left bits in both AndData and
622 If Address > 0x0FFFFFFF, then ASSERT().
623 If Address is not aligned on a 16-bit boundary, then ASSERT().
624 If StartBit is greater than 15, then ASSERT().
625 If EndBit is greater than 15, then ASSERT().
626 If EndBit is less than StartBit, then ASSERT().
628 @param Address PCI configuration register to write.
629 @param StartBit The ordinal of the least significant bit in the bit field.
631 @param EndBit The ordinal of the most significant bit in the bit field.
633 @param AndData The value to AND with the PCI configuration register.
634 @param OrData The value to OR with the result of the AND operation.
636 @return The value written back to the PCI configuration register.
641 PciBitFieldAndThenOr16 (
650 Reads a 32-bit PCI configuration register.
652 Reads and returns the 32-bit PCI configuration register specified by Address.
653 This function must guarantee that all PCI read and write operations are
656 If Address > 0x0FFFFFFF, then ASSERT().
657 If Address is not aligned on a 32-bit boundary, then ASSERT().
659 @param Address Address that encodes the PCI Bus, Device, Function and
662 @return The read value from the PCI configuration register.
672 Writes a 32-bit PCI configuration register.
674 Writes the 32-bit PCI configuration register specified by Address with the
675 value specified by Value. Value is returned. This function must guarantee
676 that all PCI read and write operations are serialized.
678 If Address > 0x0FFFFFFF, then ASSERT().
679 If Address is not aligned on a 32-bit boundary, then ASSERT().
681 @param Address Address that encodes the PCI Bus, Device, Function and
683 @param Value The value to write.
685 @return The value written to the PCI configuration register.
696 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
699 Reads the 32-bit PCI configuration register specified by Address, performs a
700 bitwise inclusive OR between the read result and the value specified by
701 OrData, and writes the result to the 32-bit PCI configuration register
702 specified by Address. The value written to the PCI configuration register is
703 returned. This function must guarantee that all PCI read and write operations
706 If Address > 0x0FFFFFFF, then ASSERT().
707 If Address is not aligned on a 32-bit boundary, then ASSERT().
709 @param Address Address that encodes the PCI Bus, Device, Function and
711 @param OrData The value to OR with the PCI configuration register.
713 @return The value written back to the PCI configuration register.
724 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
727 Reads the 32-bit PCI configuration register specified by Address, performs a
728 bitwise AND between the read result and the value specified by AndData, and
729 writes the result to the 32-bit PCI configuration register specified by
730 Address. The value written to the PCI configuration register is returned.
731 This function must guarantee that all PCI read and write operations are
734 If Address > 0x0FFFFFFF, then ASSERT().
735 If Address is not aligned on a 32-bit boundary, then ASSERT().
737 @param Address Address that encodes the PCI Bus, Device, Function and
739 @param AndData The value to AND with the PCI configuration register.
741 @return The value written back to the PCI configuration register.
752 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
753 value, followed a bitwise inclusive OR with another 32-bit value.
755 Reads the 32-bit PCI configuration register specified by Address, performs a
756 bitwise AND between the read result and the value specified by AndData,
757 performs a bitwise inclusive OR between the result of the AND operation and
758 the value specified by OrData, and writes the result to the 32-bit PCI
759 configuration register specified by Address. The value written to the PCI
760 configuration register is returned. This function must guarantee that all PCI
761 read and write operations are serialized.
763 If Address > 0x0FFFFFFF, then ASSERT().
764 If Address is not aligned on a 32-bit boundary, then ASSERT().
766 @param Address Address that encodes the PCI Bus, Device, Function and
768 @param AndData The value to AND with the PCI configuration register.
769 @param OrData The value to OR with the result of the AND operation.
771 @return The value written back to the PCI configuration register.
783 Reads a bit field of a PCI configuration register.
785 Reads the bit field in a 32-bit PCI configuration register. The bit field is
786 specified by the StartBit and the EndBit. The value of the bit field is
789 If Address > 0x0FFFFFFF, then ASSERT().
790 If Address is not aligned on a 32-bit boundary, then ASSERT().
791 If StartBit is greater than 31, then ASSERT().
792 If EndBit is greater than 31, then ASSERT().
793 If EndBit is less than StartBit, then ASSERT().
795 @param Address PCI configuration register to read.
796 @param StartBit The ordinal of the least significant bit in the bit field.
798 @param EndBit The ordinal of the most significant bit in the bit field.
801 @return The value of the bit field read from the PCI configuration register.
813 Writes a bit field to a PCI configuration register.
815 Writes Value to the bit field of the PCI configuration register. The bit
816 field is specified by the StartBit and the EndBit. All other bits in the
817 destination PCI configuration register are preserved. The new value of the
818 32-bit register is returned.
820 If Address > 0x0FFFFFFF, then ASSERT().
821 If Address is not aligned on a 32-bit boundary, then ASSERT().
822 If StartBit is greater than 31, then ASSERT().
823 If EndBit is greater than 31, then ASSERT().
824 If EndBit is less than StartBit, then ASSERT().
826 @param Address PCI configuration register to write.
827 @param StartBit The ordinal of the least significant bit in the bit field.
829 @param EndBit The ordinal of the most significant bit in the bit field.
831 @param Value New value of the bit field.
833 @return The value written back to the PCI configuration register.
846 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
847 writes the result back to the bit field in the 32-bit port.
849 Reads the 32-bit PCI configuration register specified by Address, performs a
850 bitwise inclusive OR between the read result and the value specified by
851 OrData, and writes the result to the 32-bit PCI configuration register
852 specified by Address. The value written to the PCI configuration register is
853 returned. This function must guarantee that all PCI read and write operations
854 are serialized. Extra left bits in OrData are stripped.
856 If Address > 0x0FFFFFFF, then ASSERT().
857 If Address is not aligned on a 32-bit boundary, then ASSERT().
858 If StartBit is greater than 31, then ASSERT().
859 If EndBit is greater than 31, then ASSERT().
860 If EndBit is less than StartBit, then ASSERT().
862 @param Address PCI configuration register to write.
863 @param StartBit The ordinal of the least significant bit in the bit field.
865 @param EndBit The ordinal of the most significant bit in the bit field.
867 @param OrData The value to OR with the PCI configuration register.
869 @return The value written back to the PCI configuration register.
882 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
883 AND, and writes the result back to the bit field in the 32-bit register.
885 Reads the 32-bit PCI configuration register specified by Address, performs a
886 bitwise AND between the read result and the value specified by AndData, and
887 writes the result to the 32-bit PCI configuration register specified by
888 Address. The value written to the PCI configuration register is returned.
889 This function must guarantee that all PCI read and write operations are
890 serialized. Extra left bits in AndData are stripped.
892 If Address > 0x0FFFFFFF, then ASSERT().
893 If Address is not aligned on a 32-bit boundary, then ASSERT().
894 If StartBit is greater than 31, then ASSERT().
895 If EndBit is greater than 31, then ASSERT().
896 If EndBit is less than StartBit, then ASSERT().
898 @param Address PCI configuration register to write.
899 @param StartBit The ordinal of the least significant bit in the bit field.
901 @param EndBit The ordinal of the most significant bit in the bit field.
903 @param AndData The value to AND with the PCI configuration register.
905 @return The value written back to the PCI configuration register.
918 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
919 bitwise inclusive OR, and writes the result back to the bit field in the
922 Reads the 32-bit PCI configuration register specified by Address, performs a
923 bitwise AND followed by a bitwise inclusive OR between the read result and
924 the value specified by AndData, and writes the result to the 32-bit PCI
925 configuration register specified by Address. The value written to the PCI
926 configuration register is returned. This function must guarantee that all PCI
927 read and write operations are serialized. Extra left bits in both AndData and
930 If Address > 0x0FFFFFFF, then ASSERT().
931 If Address is not aligned on a 32-bit boundary, then ASSERT().
932 If StartBit is greater than 31, then ASSERT().
933 If EndBit is greater than 31, then ASSERT().
934 If EndBit is less than StartBit, then ASSERT().
936 @param Address PCI configuration register to write.
937 @param StartBit The ordinal of the least significant bit in the bit field.
939 @param EndBit The ordinal of the most significant bit in the bit field.
941 @param AndData The value to AND with the PCI configuration register.
942 @param OrData The value to OR with the result of the AND operation.
944 @return The value written back to the PCI configuration register.
949 PciBitFieldAndThenOr32 (
958 Reads a range of PCI configuration registers into a caller supplied buffer.
960 Reads the range of PCI configuration registers specified by StartAddress and
961 Size into the buffer specified by Buffer. This function only allows the PCI
962 configuration registers from a single PCI function to be read. Size is
963 returned. When possible 32-bit PCI configuration read cycles are used to read
964 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
965 and 16-bit PCI configuration read cycles may be used at the beginning and the
968 If StartAddress > 0x0FFFFFFF, then ASSERT().
969 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
970 If Size > 0 and Buffer is NULL, then ASSERT().
972 @param StartAddress Starting address that encodes the PCI Bus, Device,
973 Function and Register.
974 @param Size Size in bytes of the transfer.
975 @param Buffer Pointer to a buffer receiving the data read.
983 IN UINTN StartAddress
,
989 Copies the data in a caller supplied buffer to a specified range of PCI
992 Writes the range of PCI configuration registers specified by StartAddress and
993 Size from the buffer specified by Buffer. This function only allows the PCI
994 configuration registers from a single PCI function to be written. Size is
995 returned. When possible 32-bit PCI configuration write cycles are used to
996 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
997 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
998 and the end of the range.
1000 If StartAddress > 0x0FFFFFFF, then ASSERT().
1001 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1002 If Size > 0 and Buffer is NULL, then ASSERT().
1004 @param StartAddress Starting address that encodes the PCI Bus, Device,
1005 Function and Register.
1006 @param Size Size in bytes of the transfer.
1007 @param Buffer Pointer to a buffer containing the data to write.
1009 @return Size written to StartAddress.
1015 IN UINTN StartAddress
,