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2 Provides services to access PCI Configuration Space.
4 These functions perform PCI configuration cycles using the default PCI configuration
5 access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
6 or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some
7 alternate access method. Modules will typically use the PCI Library for its PCI configuration
8 accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or
9 PCI Express Library may be used in conjunction with the PCI Library. The functionality of
10 these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use
11 explicit access methods.
13 Copyright (c) 2006 - 2008, Intel Corporation<BR>
14 All rights reserved. This program and the accompanying materials
15 are licensed and made available under the terms and conditions of the BSD License
16 which accompanies this distribution. The full text of the license may be found at
17 http://opensource.org/licenses/bsd-license.php
19 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
20 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
28 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
29 address that can be passed to the PCI Library functions.
31 @param Bus PCI Bus number. Range 0..255.
32 @param Device PCI Device number. Range 0..31.
33 @param Function PCI Function number. Range 0..7.
34 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095
37 @return The encoded PCI address.
40 #define PCI_LIB_ADDRESS(Bus,Device,Function,Offset) \
41 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
44 Register a PCI device so PCI configuration registers may be accessed after
45 SetVirtualAddressMap().
47 If Address > 0x0FFFFFFF, then ASSERT().
49 @param Address Address that encodes the PCI Bus, Device, Function and
52 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
53 @retval RETURN_UNSUPPORTED An attempt was made to call this function
54 after ExitBootServices().
55 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
56 at runtime could not be mapped.
57 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
58 complete the registration.
63 PciRegisterForRuntimeAccess (
68 Reads an 8-bit PCI configuration register.
70 Reads and returns the 8-bit PCI configuration register specified by Address.
71 This function must guarantee that all PCI read and write operations are
74 If Address > 0x0FFFFFFF, then ASSERT().
76 @param Address Address that encodes the PCI Bus, Device, Function and
79 @return The read value from the PCI configuration register.
89 Writes an 8-bit PCI configuration register.
91 Writes the 8-bit PCI configuration register specified by Address with the
92 value specified by Value. Value is returned. This function must guarantee
93 that all PCI read and write operations are serialized.
95 If Address > 0x0FFFFFFF, then ASSERT().
97 @param Address Address that encodes the PCI Bus, Device, Function and
99 @param Value The value to write.
101 @return The value written to the PCI configuration register.
112 Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
115 Reads the 8-bit PCI configuration register specified by Address, performs a
116 bitwise inclusive OR between the read result and the value specified by
117 OrData, and writes the result to the 8-bit PCI configuration register
118 specified by Address. The value written to the PCI configuration register is
119 returned. This function must guarantee that all PCI read and write operations
122 If Address > 0x0FFFFFFF, then ASSERT().
124 @param Address Address that encodes the PCI Bus, Device, Function and
126 @param OrData The value to OR with the PCI configuration register.
128 @return The value written back to the PCI configuration register.
139 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
142 Reads the 8-bit PCI configuration register specified by Address, performs a
143 bitwise AND between the read result and the value specified by AndData, and
144 writes the result to the 8-bit PCI configuration register specified by
145 Address. The value written to the PCI configuration register is returned.
146 This function must guarantee that all PCI read and write operations are
149 If Address > 0x0FFFFFFF, then ASSERT().
151 @param Address Address that encodes the PCI Bus, Device, Function and
153 @param AndData The value to AND with the PCI configuration register.
155 @return The value written back to the PCI configuration register.
166 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
167 value, followed a bitwise inclusive OR with another 8-bit value.
169 Reads the 8-bit PCI configuration register specified by Address, performs a
170 bitwise AND between the read result and the value specified by AndData,
171 performs a bitwise inclusive OR between the result of the AND operation and
172 the value specified by OrData, and writes the result to the 8-bit PCI
173 configuration register specified by Address. The value written to the PCI
174 configuration register is returned. This function must guarantee that all PCI
175 read and write operations are serialized.
177 If Address > 0x0FFFFFFF, then ASSERT().
179 @param Address Address that encodes the PCI Bus, Device, Function and
181 @param AndData The value to AND with the PCI configuration register.
182 @param OrData The value to OR with the result of the AND operation.
184 @return The value written back to the PCI configuration register.
196 Reads a bit field of a PCI configuration register.
198 Reads the bit field in an 8-bit PCI configuration register. The bit field is
199 specified by the StartBit and the EndBit. The value of the bit field is
202 If Address > 0x0FFFFFFF, then ASSERT().
203 If StartBit is greater than 7, then ASSERT().
204 If EndBit is greater than 7, then ASSERT().
205 If EndBit is less than StartBit, then ASSERT().
207 @param Address PCI configuration register to read.
208 @param StartBit The ordinal of the least significant bit in the bit field.
210 @param EndBit The ordinal of the most significant bit in the bit field.
213 @return The value of the bit field read from the PCI configuration register.
225 Writes a bit field to a PCI configuration register.
227 Writes Value to the bit field of the PCI configuration register. The bit
228 field is specified by the StartBit and the EndBit. All other bits in the
229 destination PCI configuration register are preserved. The new value of the
230 8-bit register is returned.
232 If Address > 0x0FFFFFFF, then ASSERT().
233 If StartBit is greater than 7, then ASSERT().
234 If EndBit is greater than 7, then ASSERT().
235 If EndBit is less than StartBit, then ASSERT().
237 @param Address PCI configuration register to write.
238 @param StartBit The ordinal of the least significant bit in the bit field.
240 @param EndBit The ordinal of the most significant bit in the bit field.
242 @param Value New value of the bit field.
244 @return The value written back to the PCI configuration register.
257 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
258 writes the result back to the bit field in the 8-bit port.
260 Reads the 8-bit PCI configuration register specified by Address, performs a
261 bitwise inclusive OR between the read result and the value specified by
262 OrData, and writes the result to the 8-bit PCI configuration register
263 specified by Address. The value written to the PCI configuration register is
264 returned. This function must guarantee that all PCI read and write operations
265 are serialized. Extra left bits in OrData are stripped.
267 If Address > 0x0FFFFFFF, then ASSERT().
268 If StartBit is greater than 7, then ASSERT().
269 If EndBit is greater than 7, then ASSERT().
270 If EndBit is less than StartBit, then ASSERT().
272 @param Address PCI configuration register to write.
273 @param StartBit The ordinal of the least significant bit in the bit field.
275 @param EndBit The ordinal of the most significant bit in the bit field.
277 @param OrData The value to OR with the PCI configuration register.
279 @return The value written back to the PCI configuration register.
292 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
293 AND, and writes the result back to the bit field in the 8-bit register.
295 Reads the 8-bit PCI configuration register specified by Address, performs a
296 bitwise AND between the read result and the value specified by AndData, and
297 writes the result to the 8-bit PCI configuration register specified by
298 Address. The value written to the PCI configuration register is returned.
299 This function must guarantee that all PCI read and write operations are
300 serialized. Extra left bits in AndData are stripped.
302 If Address > 0x0FFFFFFF, then ASSERT().
303 If StartBit is greater than 7, then ASSERT().
304 If EndBit is greater than 7, then ASSERT().
305 If EndBit is less than StartBit, then ASSERT().
307 @param Address PCI configuration register to write.
308 @param StartBit The ordinal of the least significant bit in the bit field.
310 @param EndBit The ordinal of the most significant bit in the bit field.
312 @param AndData The value to AND with the PCI configuration register.
314 @return The value written back to the PCI configuration register.
327 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
328 bitwise inclusive OR, and writes the result back to the bit field in the
331 Reads the 8-bit PCI configuration register specified by Address, performs a
332 bitwise AND followed by a bitwise inclusive OR between the read result and
333 the value specified by AndData, and writes the result to the 8-bit PCI
334 configuration register specified by Address. The value written to the PCI
335 configuration register is returned. This function must guarantee that all PCI
336 read and write operations are serialized. Extra left bits in both AndData and
339 If Address > 0x0FFFFFFF, then ASSERT().
340 If StartBit is greater than 7, then ASSERT().
341 If EndBit is greater than 7, then ASSERT().
342 If EndBit is less than StartBit, then ASSERT().
344 @param Address PCI configuration register to write.
345 @param StartBit The ordinal of the least significant bit in the bit field.
347 @param EndBit The ordinal of the most significant bit in the bit field.
349 @param AndData The value to AND with the PCI configuration register.
350 @param OrData The value to OR with the result of the AND operation.
352 @return The value written back to the PCI configuration register.
357 PciBitFieldAndThenOr8 (
366 Reads a 16-bit PCI configuration register.
368 Reads and returns the 16-bit PCI configuration register specified by Address.
369 This function must guarantee that all PCI read and write operations are
372 If Address > 0x0FFFFFFF, then ASSERT().
373 If Address is not aligned on a 16-bit boundary, then ASSERT().
375 @param Address Address that encodes the PCI Bus, Device, Function and
378 @return The read value from the PCI configuration register.
388 Writes a 16-bit PCI configuration register.
390 Writes the 16-bit PCI configuration register specified by Address with the
391 value specified by Value. Value is returned. This function must guarantee
392 that all PCI read and write operations are serialized.
394 If Address > 0x0FFFFFFF, then ASSERT().
395 If Address is not aligned on a 16-bit boundary, then ASSERT().
397 @param Address Address that encodes the PCI Bus, Device, Function and
399 @param Value The value to write.
401 @return The value written to the PCI configuration register.
412 Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
415 Reads the 16-bit PCI configuration register specified by Address, performs a
416 bitwise inclusive OR between the read result and the value specified by
417 OrData, and writes the result to the 16-bit PCI configuration register
418 specified by Address. The value written to the PCI configuration register is
419 returned. This function must guarantee that all PCI read and write operations
422 If Address > 0x0FFFFFFF, then ASSERT().
423 If Address is not aligned on a 16-bit boundary, then ASSERT().
425 @param Address Address that encodes the PCI Bus, Device, Function and
427 @param OrData The value to OR with the PCI configuration register.
429 @return The value written back to the PCI configuration register.
440 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
443 Reads the 16-bit PCI configuration register specified by Address, performs a
444 bitwise AND between the read result and the value specified by AndData, and
445 writes the result to the 16-bit PCI configuration register specified by
446 Address. The value written to the PCI configuration register is returned.
447 This function must guarantee that all PCI read and write operations are
450 If Address > 0x0FFFFFFF, then ASSERT().
451 If Address is not aligned on a 16-bit boundary, then ASSERT().
453 @param Address Address that encodes the PCI Bus, Device, Function and
455 @param AndData The value to AND with the PCI configuration register.
457 @return The value written back to the PCI configuration register.
468 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
469 value, followed a bitwise inclusive OR with another 16-bit value.
471 Reads the 16-bit PCI configuration register specified by Address, performs a
472 bitwise AND between the read result and the value specified by AndData,
473 performs a bitwise inclusive OR between the result of the AND operation and
474 the value specified by OrData, and writes the result to the 16-bit PCI
475 configuration register specified by Address. The value written to the PCI
476 configuration register is returned. This function must guarantee that all PCI
477 read and write operations are serialized.
479 If Address > 0x0FFFFFFF, then ASSERT().
480 If Address is not aligned on a 16-bit boundary, then ASSERT().
482 @param Address Address that encodes the PCI Bus, Device, Function and
484 @param AndData The value to AND with the PCI configuration register.
485 @param OrData The value to OR with the result of the AND operation.
487 @return The value written back to the PCI configuration register.
499 Reads a bit field of a PCI configuration register.
501 Reads the bit field in a 16-bit PCI configuration register. The bit field is
502 specified by the StartBit and the EndBit. The value of the bit field is
505 If Address > 0x0FFFFFFF, then ASSERT().
506 If Address is not aligned on a 16-bit boundary, then ASSERT().
507 If StartBit is greater than 15, then ASSERT().
508 If EndBit is greater than 15, then ASSERT().
509 If EndBit is less than StartBit, then ASSERT().
511 @param Address PCI configuration register to read.
512 @param StartBit The ordinal of the least significant bit in the bit field.
514 @param EndBit The ordinal of the most significant bit in the bit field.
517 @return The value of the bit field read from the PCI configuration register.
529 Writes a bit field to a PCI configuration register.
531 Writes Value to the bit field of the PCI configuration register. The bit
532 field is specified by the StartBit and the EndBit. All other bits in the
533 destination PCI configuration register are preserved. The new value of the
534 16-bit register is returned.
536 If Address > 0x0FFFFFFF, then ASSERT().
537 If Address is not aligned on a 16-bit boundary, then ASSERT().
538 If StartBit is greater than 15, then ASSERT().
539 If EndBit is greater than 15, then ASSERT().
540 If EndBit is less than StartBit, then ASSERT().
542 @param Address PCI configuration register to write.
543 @param StartBit The ordinal of the least significant bit in the bit field.
545 @param EndBit The ordinal of the most significant bit in the bit field.
547 @param Value New value of the bit field.
549 @return The value written back to the PCI configuration register.
562 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
563 writes the result back to the bit field in the 16-bit port.
565 Reads the 16-bit PCI configuration register specified by Address, performs a
566 bitwise inclusive OR between the read result and the value specified by
567 OrData, and writes the result to the 16-bit PCI configuration register
568 specified by Address. The value written to the PCI configuration register is
569 returned. This function must guarantee that all PCI read and write operations
570 are serialized. Extra left bits in OrData are stripped.
572 If Address > 0x0FFFFFFF, then ASSERT().
573 If Address is not aligned on a 16-bit boundary, then ASSERT().
574 If StartBit is greater than 15, then ASSERT().
575 If EndBit is greater than 15, then ASSERT().
576 If EndBit is less than StartBit, then ASSERT().
578 @param Address PCI configuration register to write.
579 @param StartBit The ordinal of the least significant bit in the bit field.
581 @param EndBit The ordinal of the most significant bit in the bit field.
583 @param OrData The value to OR with the PCI configuration register.
585 @return The value written back to the PCI configuration register.
598 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
599 AND, and writes the result back to the bit field in the 16-bit register.
601 Reads the 16-bit PCI configuration register specified by Address, performs a
602 bitwise AND between the read result and the value specified by AndData, and
603 writes the result to the 16-bit PCI configuration register specified by
604 Address. The value written to the PCI configuration register is returned.
605 This function must guarantee that all PCI read and write operations are
606 serialized. Extra left bits in AndData are stripped.
608 If Address > 0x0FFFFFFF, then ASSERT().
609 If Address is not aligned on a 16-bit boundary, then ASSERT().
610 If StartBit is greater than 15, then ASSERT().
611 If EndBit is greater than 15, then ASSERT().
612 If EndBit is less than StartBit, then ASSERT().
614 @param Address PCI configuration register to write.
615 @param StartBit The ordinal of the least significant bit in the bit field.
617 @param EndBit The ordinal of the most significant bit in the bit field.
619 @param AndData The value to AND with the PCI configuration register.
621 @return The value written back to the PCI configuration register.
634 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
635 bitwise inclusive OR, and writes the result back to the bit field in the
638 Reads the 16-bit PCI configuration register specified by Address, performs a
639 bitwise AND followed by a bitwise inclusive OR between the read result and
640 the value specified by AndData, and writes the result to the 16-bit PCI
641 configuration register specified by Address. The value written to the PCI
642 configuration register is returned. This function must guarantee that all PCI
643 read and write operations are serialized. Extra left bits in both AndData and
646 If Address > 0x0FFFFFFF, then ASSERT().
647 If Address is not aligned on a 16-bit boundary, then ASSERT().
648 If StartBit is greater than 15, then ASSERT().
649 If EndBit is greater than 15, then ASSERT().
650 If EndBit is less than StartBit, then ASSERT().
652 @param Address PCI configuration register to write.
653 @param StartBit The ordinal of the least significant bit in the bit field.
655 @param EndBit The ordinal of the most significant bit in the bit field.
657 @param AndData The value to AND with the PCI configuration register.
658 @param OrData The value to OR with the result of the AND operation.
660 @return The value written back to the PCI configuration register.
665 PciBitFieldAndThenOr16 (
674 Reads a 32-bit PCI configuration register.
676 Reads and returns the 32-bit PCI configuration register specified by Address.
677 This function must guarantee that all PCI read and write operations are
680 If Address > 0x0FFFFFFF, then ASSERT().
681 If Address is not aligned on a 32-bit boundary, then ASSERT().
683 @param Address Address that encodes the PCI Bus, Device, Function and
686 @return The read value from the PCI configuration register.
696 Writes a 32-bit PCI configuration register.
698 Writes the 32-bit PCI configuration register specified by Address with the
699 value specified by Value. Value is returned. This function must guarantee
700 that all PCI read and write operations are serialized.
702 If Address > 0x0FFFFFFF, then ASSERT().
703 If Address is not aligned on a 32-bit boundary, then ASSERT().
705 @param Address Address that encodes the PCI Bus, Device, Function and
707 @param Value The value to write.
709 @return The value written to the PCI configuration register.
720 Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
723 Reads the 32-bit PCI configuration register specified by Address, performs a
724 bitwise inclusive OR between the read result and the value specified by
725 OrData, and writes the result to the 32-bit PCI configuration register
726 specified by Address. The value written to the PCI configuration register is
727 returned. This function must guarantee that all PCI read and write operations
730 If Address > 0x0FFFFFFF, then ASSERT().
731 If Address is not aligned on a 32-bit boundary, then ASSERT().
733 @param Address Address that encodes the PCI Bus, Device, Function and
735 @param OrData The value to OR with the PCI configuration register.
737 @return The value written back to the PCI configuration register.
748 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
751 Reads the 32-bit PCI configuration register specified by Address, performs a
752 bitwise AND between the read result and the value specified by AndData, and
753 writes the result to the 32-bit PCI configuration register specified by
754 Address. The value written to the PCI configuration register is returned.
755 This function must guarantee that all PCI read and write operations are
758 If Address > 0x0FFFFFFF, then ASSERT().
759 If Address is not aligned on a 32-bit boundary, then ASSERT().
761 @param Address Address that encodes the PCI Bus, Device, Function and
763 @param AndData The value to AND with the PCI configuration register.
765 @return The value written back to the PCI configuration register.
776 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
777 value, followed a bitwise inclusive OR with another 32-bit value.
779 Reads the 32-bit PCI configuration register specified by Address, performs a
780 bitwise AND between the read result and the value specified by AndData,
781 performs a bitwise inclusive OR between the result of the AND operation and
782 the value specified by OrData, and writes the result to the 32-bit PCI
783 configuration register specified by Address. The value written to the PCI
784 configuration register is returned. This function must guarantee that all PCI
785 read and write operations are serialized.
787 If Address > 0x0FFFFFFF, then ASSERT().
788 If Address is not aligned on a 32-bit boundary, then ASSERT().
790 @param Address Address that encodes the PCI Bus, Device, Function and
792 @param AndData The value to AND with the PCI configuration register.
793 @param OrData The value to OR with the result of the AND operation.
795 @return The value written back to the PCI configuration register.
807 Reads a bit field of a PCI configuration register.
809 Reads the bit field in a 32-bit PCI configuration register. The bit field is
810 specified by the StartBit and the EndBit. The value of the bit field is
813 If Address > 0x0FFFFFFF, then ASSERT().
814 If Address is not aligned on a 32-bit boundary, then ASSERT().
815 If StartBit is greater than 31, then ASSERT().
816 If EndBit is greater than 31, then ASSERT().
817 If EndBit is less than StartBit, then ASSERT().
819 @param Address PCI configuration register to read.
820 @param StartBit The ordinal of the least significant bit in the bit field.
822 @param EndBit The ordinal of the most significant bit in the bit field.
825 @return The value of the bit field read from the PCI configuration register.
837 Writes a bit field to a PCI configuration register.
839 Writes Value to the bit field of the PCI configuration register. The bit
840 field is specified by the StartBit and the EndBit. All other bits in the
841 destination PCI configuration register are preserved. The new value of the
842 32-bit register is returned.
844 If Address > 0x0FFFFFFF, then ASSERT().
845 If Address is not aligned on a 32-bit boundary, then ASSERT().
846 If StartBit is greater than 31, then ASSERT().
847 If EndBit is greater than 31, then ASSERT().
848 If EndBit is less than StartBit, then ASSERT().
850 @param Address PCI configuration register to write.
851 @param StartBit The ordinal of the least significant bit in the bit field.
853 @param EndBit The ordinal of the most significant bit in the bit field.
855 @param Value New value of the bit field.
857 @return The value written back to the PCI configuration register.
870 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
871 writes the result back to the bit field in the 32-bit port.
873 Reads the 32-bit PCI configuration register specified by Address, performs a
874 bitwise inclusive OR between the read result and the value specified by
875 OrData, and writes the result to the 32-bit PCI configuration register
876 specified by Address. The value written to the PCI configuration register is
877 returned. This function must guarantee that all PCI read and write operations
878 are serialized. Extra left bits in OrData are stripped.
880 If Address > 0x0FFFFFFF, then ASSERT().
881 If Address is not aligned on a 32-bit boundary, then ASSERT().
882 If StartBit is greater than 31, then ASSERT().
883 If EndBit is greater than 31, then ASSERT().
884 If EndBit is less than StartBit, then ASSERT().
886 @param Address PCI configuration register to write.
887 @param StartBit The ordinal of the least significant bit in the bit field.
889 @param EndBit The ordinal of the most significant bit in the bit field.
891 @param OrData The value to OR with the PCI configuration register.
893 @return The value written back to the PCI configuration register.
906 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
907 AND, and writes the result back to the bit field in the 32-bit register.
909 Reads the 32-bit PCI configuration register specified by Address, performs a
910 bitwise AND between the read result and the value specified by AndData, and
911 writes the result to the 32-bit PCI configuration register specified by
912 Address. The value written to the PCI configuration register is returned.
913 This function must guarantee that all PCI read and write operations are
914 serialized. Extra left bits in AndData are stripped.
916 If Address > 0x0FFFFFFF, then ASSERT().
917 If Address is not aligned on a 32-bit boundary, then ASSERT().
918 If StartBit is greater than 31, then ASSERT().
919 If EndBit is greater than 31, then ASSERT().
920 If EndBit is less than StartBit, then ASSERT().
922 @param Address PCI configuration register to write.
923 @param StartBit The ordinal of the least significant bit in the bit field.
925 @param EndBit The ordinal of the most significant bit in the bit field.
927 @param AndData The value to AND with the PCI configuration register.
929 @return The value written back to the PCI configuration register.
942 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
943 bitwise inclusive OR, and writes the result back to the bit field in the
946 Reads the 32-bit PCI configuration register specified by Address, performs a
947 bitwise AND followed by a bitwise inclusive OR between the read result and
948 the value specified by AndData, and writes the result to the 32-bit PCI
949 configuration register specified by Address. The value written to the PCI
950 configuration register is returned. This function must guarantee that all PCI
951 read and write operations are serialized. Extra left bits in both AndData and
954 If Address > 0x0FFFFFFF, then ASSERT().
955 If Address is not aligned on a 32-bit boundary, then ASSERT().
956 If StartBit is greater than 31, then ASSERT().
957 If EndBit is greater than 31, then ASSERT().
958 If EndBit is less than StartBit, then ASSERT().
960 @param Address PCI configuration register to write.
961 @param StartBit The ordinal of the least significant bit in the bit field.
963 @param EndBit The ordinal of the most significant bit in the bit field.
965 @param AndData The value to AND with the PCI configuration register.
966 @param OrData The value to OR with the result of the AND operation.
968 @return The value written back to the PCI configuration register.
973 PciBitFieldAndThenOr32 (
982 Reads a range of PCI configuration registers into a caller supplied buffer.
984 Reads the range of PCI configuration registers specified by StartAddress and
985 Size into the buffer specified by Buffer. This function only allows the PCI
986 configuration registers from a single PCI function to be read. Size is
987 returned. When possible 32-bit PCI configuration read cycles are used to read
988 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
989 and 16-bit PCI configuration read cycles may be used at the beginning and the
992 If StartAddress > 0x0FFFFFFF, then ASSERT().
993 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
994 If Size > 0 and Buffer is NULL, then ASSERT().
996 @param StartAddress Starting address that encodes the PCI Bus, Device,
997 Function and Register.
998 @param Size Size in bytes of the transfer.
999 @param Buffer Pointer to a buffer receiving the data read.
1007 IN UINTN StartAddress
,
1013 Copies the data in a caller supplied buffer to a specified range of PCI
1014 configuration space.
1016 Writes the range of PCI configuration registers specified by StartAddress and
1017 Size from the buffer specified by Buffer. This function only allows the PCI
1018 configuration registers from a single PCI function to be written. Size is
1019 returned. When possible 32-bit PCI configuration write cycles are used to
1020 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1021 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1022 and the end of the range.
1024 If StartAddress > 0x0FFFFFFF, then ASSERT().
1025 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1026 If Size > 0 and Buffer is NULL, then ASSERT().
1028 @param StartAddress Starting address that encodes the PCI Bus, Device,
1029 Function and Register.
1030 @param Size Size in bytes of the transfer.
1031 @param Buffer Pointer to a buffer containing the data to write.
1033 @return Size written to StartAddress.
1039 IN UINTN StartAddress
,