MdePkg/Include/Library/PciLib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space.
   3
   4   These functions perform PCI configuration cycles using the default PCI configuration
   5   access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
   6   or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some
   7   alternate access method.  Modules will typically use the PCI Library for its PCI configuration
   8   accesses.  However, if a module requires a mix of PCI access methods, the PCI CF8 Library or
   9   PCI Express Library may be used in conjunction with the PCI Library.  The functionality of
  10   these three libraries is identical.  The PCI CF8 Library and PCI Express Library simply use
  11   explicit access methods.
  12
  13 Copyright (c) 2006 - 2008, Intel Corporation<BR>
  14 All rights reserved. This program and the accompanying materials
  15 are licensed and made available under the terms and conditions of the BSD License
  16 which accompanies this distribution.  The full text of the license may be found at
  17 http://opensource.org/licenses/bsd-license.php
  18
  19 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  20 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  21
  22 **/
  23
  24 #ifndef __PCI_LIB_H__
  25 #define __PCI_LIB_H__
  26
  27 /**
  28   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  29   address that can be passed to the PCI Library functions.
  30
  31   @param  Bus       PCI Bus number. Range 0..255.
  32   @param  Device    PCI Device number. Range 0..31.
  33   @param  Function  PCI Function number. Range 0..7.
  34   @param  Register  PCI Register number. Range 0..255 for PCI. Range 0..4095
  35                     for PCI Express.
  36
  37   @return The encoded PCI address.
  38
  39 **/
  40 #define PCI_LIB_ADDRESS(Bus,Device,Function,Offset)   \
  41   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  42
  43 /**
  44   Register a PCI device so PCI configuration registers may be accessed after
  45   SetVirtualAddressMap().
  46
  47   If Address > 0x0FFFFFFF, then ASSERT().
  48
  49   @param  Address Address that encodes the PCI Bus, Device, Function and
  50                   Register.
  51
  52   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  53   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  54                                    after ExitBootServices().
  55   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  56                                    at runtime could not be mapped.
  57   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  58                                    complete the registration.
  59
  60 **/
  61 RETURN_STATUS
  62 EFIAPI
  63 PciRegisterForRuntimeAccess (
  64   IN UINTN  Address
  65   );
  66
  67 /**
  68   Reads an 8-bit PCI configuration register.
  69
  70   Reads and returns the 8-bit PCI configuration register specified by Address.
  71   This function must guarantee that all PCI read and write operations are
  72   serialized.
  73
  74   If Address > 0x0FFFFFFF, then ASSERT().
  75
  76   @param  Address Address that encodes the PCI Bus, Device, Function and
  77                   Register.
  78
  79   @return The read value from the PCI configuration register.
  80
  81 **/
  82 UINT8
  83 EFIAPI
  84 PciRead8 (
  85   IN      UINTN                     Address
  86   );
  87
  88 /**
  89   Writes an 8-bit PCI configuration register.
  90
  91   Writes the 8-bit PCI configuration register specified by Address with the
  92   value specified by Value. Value is returned. This function must guarantee
  93   that all PCI read and write operations are serialized.
  94
  95   If Address > 0x0FFFFFFF, then ASSERT().
  96
  97   @param  Address Address that encodes the PCI Bus, Device, Function and
  98                   Register.
  99   @param  Value   The value to write.
 100
 101   @return The value written to the PCI configuration register.
 102
 103 **/
 104 UINT8
 105 EFIAPI
 106 PciWrite8 (
 107   IN      UINTN                     Address,
 108   IN      UINT8                     Value
 109   );
 110
 111 /**
 112   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
 113   an 8-bit value.
 114
 115   Reads the 8-bit PCI configuration register specified by Address, performs a
 116   bitwise inclusive OR between the read result and the value specified by
 117   OrData, and writes the result to the 8-bit PCI configuration register
 118   specified by Address. The value written to the PCI configuration register is
 119   returned. This function must guarantee that all PCI read and write operations
 120   are serialized.
 121
 122   If Address > 0x0FFFFFFF, then ASSERT().
 123
 124   @param  Address Address that encodes the PCI Bus, Device, Function and
 125                   Register.
 126   @param  OrData  The value to OR with the PCI configuration register.
 127
 128   @return The value written back to the PCI configuration register.
 129
 130 **/
 131 UINT8
 132 EFIAPI
 133 PciOr8 (
 134   IN      UINTN                     Address,
 135   IN      UINT8                     OrData
 136   );
 137
 138 /**
 139   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 140   value.
 141
 142   Reads the 8-bit PCI configuration register specified by Address, performs a
 143   bitwise AND between the read result and the value specified by AndData, and
 144   writes the result to the 8-bit PCI configuration register specified by
 145   Address. The value written to the PCI configuration register is returned.
 146   This function must guarantee that all PCI read and write operations are
 147   serialized.
 148
 149   If Address > 0x0FFFFFFF, then ASSERT().
 150
 151   @param  Address Address that encodes the PCI Bus, Device, Function and
 152                   Register.
 153   @param  AndData The value to AND with the PCI configuration register.
 154
 155   @return The value written back to the PCI configuration register.
 156
 157 **/
 158 UINT8
 159 EFIAPI
 160 PciAnd8 (
 161   IN      UINTN                     Address,
 162   IN      UINT8                     AndData
 163   );
 164
 165 /**
 166   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 167   value, followed a  bitwise inclusive OR with another 8-bit value.
 168
 169   Reads the 8-bit PCI configuration register specified by Address, performs a
 170   bitwise AND between the read result and the value specified by AndData,
 171   performs a bitwise inclusive OR between the result of the AND operation and
 172   the value specified by OrData, and writes the result to the 8-bit PCI
 173   configuration register specified by Address. The value written to the PCI
 174   configuration register is returned. This function must guarantee that all PCI
 175   read and write operations are serialized.
 176
 177   If Address > 0x0FFFFFFF, then ASSERT().
 178
 179   @param  Address Address that encodes the PCI Bus, Device, Function and
 180                   Register.
 181   @param  AndData The value to AND with the PCI configuration register.
 182   @param  OrData  The value to OR with the result of the AND operation.
 183
 184   @return The value written back to the PCI configuration register.
 185
 186 **/
 187 UINT8
 188 EFIAPI
 189 PciAndThenOr8 (
 190   IN      UINTN                     Address,
 191   IN      UINT8                     AndData,
 192   IN      UINT8                     OrData
 193   );
 194
 195 /**
 196   Reads a bit field of a PCI configuration register.
 197
 198   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 199   specified by the StartBit and the EndBit. The value of the bit field is
 200   returned.
 201
 202   If Address > 0x0FFFFFFF, then ASSERT().
 203   If StartBit is greater than 7, then ASSERT().
 204   If EndBit is greater than 7, then ASSERT().
 205   If EndBit is less than StartBit, then ASSERT().
 206
 207   @param  Address   PCI configuration register to read.
 208   @param  StartBit  The ordinal of the least significant bit in the bit field.
 209                     Range 0..7.
 210   @param  EndBit    The ordinal of the most significant bit in the bit field.
 211                     Range 0..7.
 212
 213   @return The value of the bit field read from the PCI configuration register.
 214
 215 **/
 216 UINT8
 217 EFIAPI
 218 PciBitFieldRead8 (
 219   IN      UINTN                     Address,
 220   IN      UINTN                     StartBit,
 221   IN      UINTN                     EndBit
 222   );
 223
 224 /**
 225   Writes a bit field to a PCI configuration register.
 226
 227   Writes Value to the bit field of the PCI configuration register. The bit
 228   field is specified by the StartBit and the EndBit. All other bits in the
 229   destination PCI configuration register are preserved. The new value of the
 230   8-bit register is returned.
 231
 232   If Address > 0x0FFFFFFF, then ASSERT().
 233   If StartBit is greater than 7, then ASSERT().
 234   If EndBit is greater than 7, then ASSERT().
 235   If EndBit is less than StartBit, then ASSERT().
 236
 237   @param  Address   PCI configuration register to write.
 238   @param  StartBit  The ordinal of the least significant bit in the bit field.
 239                     Range 0..7.
 240   @param  EndBit    The ordinal of the most significant bit in the bit field.
 241                     Range 0..7.
 242   @param  Value     New value of the bit field.
 243
 244   @return The value written back to the PCI configuration register.
 245
 246 **/
 247 UINT8
 248 EFIAPI
 249 PciBitFieldWrite8 (
 250   IN      UINTN                     Address,
 251   IN      UINTN                     StartBit,
 252   IN      UINTN                     EndBit,
 253   IN      UINT8                     Value
 254   );
 255
 256 /**
 257   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 258   writes the result back to the bit field in the 8-bit port.
 259
 260   Reads the 8-bit PCI configuration register specified by Address, performs a
 261   bitwise inclusive OR between the read result and the value specified by
 262   OrData, and writes the result to the 8-bit PCI configuration register
 263   specified by Address. The value written to the PCI configuration register is
 264   returned. This function must guarantee that all PCI read and write operations
 265   are serialized. Extra left bits in OrData are stripped.
 266
 267   If Address > 0x0FFFFFFF, then ASSERT().
 268   If StartBit is greater than 7, then ASSERT().
 269   If EndBit is greater than 7, then ASSERT().
 270   If EndBit is less than StartBit, then ASSERT().
 271
 272   @param  Address   PCI configuration register to write.
 273   @param  StartBit  The ordinal of the least significant bit in the bit field.
 274                     Range 0..7.
 275   @param  EndBit    The ordinal of the most significant bit in the bit field.
 276                     Range 0..7.
 277   @param  OrData    The value to OR with the PCI configuration register.
 278
 279   @return The value written back to the PCI configuration register.
 280
 281 **/
 282 UINT8
 283 EFIAPI
 284 PciBitFieldOr8 (
 285   IN      UINTN                     Address,
 286   IN      UINTN                     StartBit,
 287   IN      UINTN                     EndBit,
 288   IN      UINT8                     OrData
 289   );
 290
 291 /**
 292   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 293   AND, and writes the result back to the bit field in the 8-bit register.
 294
 295   Reads the 8-bit PCI configuration register specified by Address, performs a
 296   bitwise AND between the read result and the value specified by AndData, and
 297   writes the result to the 8-bit PCI configuration register specified by
 298   Address. The value written to the PCI configuration register is returned.
 299   This function must guarantee that all PCI read and write operations are
 300   serialized. Extra left bits in AndData are stripped.
 301
 302   If Address > 0x0FFFFFFF, then ASSERT().
 303   If StartBit is greater than 7, then ASSERT().
 304   If EndBit is greater than 7, then ASSERT().
 305   If EndBit is less than StartBit, then ASSERT().
 306
 307   @param  Address   PCI configuration register to write.
 308   @param  StartBit  The ordinal of the least significant bit in the bit field.
 309                     Range 0..7.
 310   @param  EndBit    The ordinal of the most significant bit in the bit field.
 311                     Range 0..7.
 312   @param  AndData   The value to AND with the PCI configuration register.
 313
 314   @return The value written back to the PCI configuration register.
 315
 316 **/
 317 UINT8
 318 EFIAPI
 319 PciBitFieldAnd8 (
 320   IN      UINTN                     Address,
 321   IN      UINTN                     StartBit,
 322   IN      UINTN                     EndBit,
 323   IN      UINT8                     AndData
 324   );
 325
 326 /**
 327   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 328   bitwise inclusive OR, and writes the result back to the bit field in the
 329   8-bit port.
 330
 331   Reads the 8-bit PCI configuration register specified by Address, performs a
 332   bitwise AND followed by a bitwise inclusive OR between the read result and
 333   the value specified by AndData, and writes the result to the 8-bit PCI
 334   configuration register specified by Address. The value written to the PCI
 335   configuration register is returned. This function must guarantee that all PCI
 336   read and write operations are serialized. Extra left bits in both AndData and
 337   OrData are stripped.
 338
 339   If Address > 0x0FFFFFFF, then ASSERT().
 340   If StartBit is greater than 7, then ASSERT().
 341   If EndBit is greater than 7, then ASSERT().
 342   If EndBit is less than StartBit, then ASSERT().
 343
 344   @param  Address   PCI configuration register to write.
 345   @param  StartBit  The ordinal of the least significant bit in the bit field.
 346                     Range 0..7.
 347   @param  EndBit    The ordinal of the most significant bit in the bit field.
 348                     Range 0..7.
 349   @param  AndData   The value to AND with the PCI configuration register.
 350   @param  OrData    The value to OR with the result of the AND operation.
 351
 352   @return The value written back to the PCI configuration register.
 353
 354 **/
 355 UINT8
 356 EFIAPI
 357 PciBitFieldAndThenOr8 (
 358   IN      UINTN                     Address,
 359   IN      UINTN                     StartBit,
 360   IN      UINTN                     EndBit,
 361   IN      UINT8                     AndData,
 362   IN      UINT8                     OrData
 363   );
 364
 365 /**
 366   Reads a 16-bit PCI configuration register.
 367
 368   Reads and returns the 16-bit PCI configuration register specified by Address.
 369   This function must guarantee that all PCI read and write operations are
 370   serialized.
 371
 372   If Address > 0x0FFFFFFF, then ASSERT().
 373   If Address is not aligned on a 16-bit boundary, then ASSERT().
 374
 375   @param  Address Address that encodes the PCI Bus, Device, Function and
 376                   Register.
 377
 378   @return The read value from the PCI configuration register.
 379
 380 **/
 381 UINT16
 382 EFIAPI
 383 PciRead16 (
 384   IN      UINTN                     Address
 385   );
 386
 387 /**
 388   Writes a 16-bit PCI configuration register.
 389
 390   Writes the 16-bit PCI configuration register specified by Address with the
 391   value specified by Value. Value is returned. This function must guarantee
 392   that all PCI read and write operations are serialized.
 393
 394   If Address > 0x0FFFFFFF, then ASSERT().
 395   If Address is not aligned on a 16-bit boundary, then ASSERT().
 396
 397   @param  Address Address that encodes the PCI Bus, Device, Function and
 398                   Register.
 399   @param  Value   The value to write.
 400
 401   @return The value written to the PCI configuration register.
 402
 403 **/
 404 UINT16
 405 EFIAPI
 406 PciWrite16 (
 407   IN      UINTN                     Address,
 408   IN      UINT16                    Value
 409   );
 410
 411 /**
 412   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 413   a 16-bit value.
 414
 415   Reads the 16-bit PCI configuration register specified by Address, performs a
 416   bitwise inclusive OR between the read result and the value specified by
 417   OrData, and writes the result to the 16-bit PCI configuration register
 418   specified by Address. The value written to the PCI configuration register is
 419   returned. This function must guarantee that all PCI read and write operations
 420   are serialized.
 421
 422   If Address > 0x0FFFFFFF, then ASSERT().
 423   If Address is not aligned on a 16-bit boundary, then ASSERT().
 424
 425   @param  Address Address that encodes the PCI Bus, Device, Function and
 426                   Register.
 427   @param  OrData  The value to OR with the PCI configuration register.
 428
 429   @return The value written back to the PCI configuration register.
 430
 431 **/
 432 UINT16
 433 EFIAPI
 434 PciOr16 (
 435   IN      UINTN                     Address,
 436   IN      UINT16                    OrData
 437   );
 438
 439 /**
 440   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 441   value.
 442
 443   Reads the 16-bit PCI configuration register specified by Address, performs a
 444   bitwise AND between the read result and the value specified by AndData, and
 445   writes the result to the 16-bit PCI configuration register specified by
 446   Address. The value written to the PCI configuration register is returned.
 447   This function must guarantee that all PCI read and write operations are
 448   serialized.
 449
 450   If Address > 0x0FFFFFFF, then ASSERT().
 451   If Address is not aligned on a 16-bit boundary, then ASSERT().
 452
 453   @param  Address Address that encodes the PCI Bus, Device, Function and
 454                   Register.
 455   @param  AndData The value to AND with the PCI configuration register.
 456
 457   @return The value written back to the PCI configuration register.
 458
 459 **/
 460 UINT16
 461 EFIAPI
 462 PciAnd16 (
 463   IN      UINTN                     Address,
 464   IN      UINT16                    AndData
 465   );
 466
 467 /**
 468   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 469   value, followed a  bitwise inclusive OR with another 16-bit value.
 470
 471   Reads the 16-bit PCI configuration register specified by Address, performs a
 472   bitwise AND between the read result and the value specified by AndData,
 473   performs a bitwise inclusive OR between the result of the AND operation and
 474   the value specified by OrData, and writes the result to the 16-bit PCI
 475   configuration register specified by Address. The value written to the PCI
 476   configuration register is returned. This function must guarantee that all PCI
 477   read and write operations are serialized.
 478
 479   If Address > 0x0FFFFFFF, then ASSERT().
 480   If Address is not aligned on a 16-bit boundary, then ASSERT().
 481
 482   @param  Address Address that encodes the PCI Bus, Device, Function and
 483                   Register.
 484   @param  AndData The value to AND with the PCI configuration register.
 485   @param  OrData  The value to OR with the result of the AND operation.
 486
 487   @return The value written back to the PCI configuration register.
 488
 489 **/
 490 UINT16
 491 EFIAPI
 492 PciAndThenOr16 (
 493   IN      UINTN                     Address,
 494   IN      UINT16                    AndData,
 495   IN      UINT16                    OrData
 496   );
 497
 498 /**
 499   Reads a bit field of a PCI configuration register.
 500
 501   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 502   specified by the StartBit and the EndBit. The value of the bit field is
 503   returned.
 504
 505   If Address > 0x0FFFFFFF, then ASSERT().
 506   If Address is not aligned on a 16-bit boundary, then ASSERT().
 507   If StartBit is greater than 15, then ASSERT().
 508   If EndBit is greater than 15, then ASSERT().
 509   If EndBit is less than StartBit, then ASSERT().
 510
 511   @param  Address   PCI configuration register to read.
 512   @param  StartBit  The ordinal of the least significant bit in the bit field.
 513                     Range 0..15.
 514   @param  EndBit    The ordinal of the most significant bit in the bit field.
 515                     Range 0..15.
 516
 517   @return The value of the bit field read from the PCI configuration register.
 518
 519 **/
 520 UINT16
 521 EFIAPI
 522 PciBitFieldRead16 (
 523   IN      UINTN                     Address,
 524   IN      UINTN                     StartBit,
 525   IN      UINTN                     EndBit
 526   );
 527
 528 /**
 529   Writes a bit field to a PCI configuration register.
 530
 531   Writes Value to the bit field of the PCI configuration register. The bit
 532   field is specified by the StartBit and the EndBit. All other bits in the
 533   destination PCI configuration register are preserved. The new value of the
 534   16-bit register is returned.
 535
 536   If Address > 0x0FFFFFFF, then ASSERT().
 537   If Address is not aligned on a 16-bit boundary, then ASSERT().
 538   If StartBit is greater than 15, then ASSERT().
 539   If EndBit is greater than 15, then ASSERT().
 540   If EndBit is less than StartBit, then ASSERT().
 541
 542   @param  Address   PCI configuration register to write.
 543   @param  StartBit  The ordinal of the least significant bit in the bit field.
 544                     Range 0..15.
 545   @param  EndBit    The ordinal of the most significant bit in the bit field.
 546                     Range 0..15.
 547   @param  Value     New value of the bit field.
 548
 549   @return The value written back to the PCI configuration register.
 550
 551 **/
 552 UINT16
 553 EFIAPI
 554 PciBitFieldWrite16 (
 555   IN      UINTN                     Address,
 556   IN      UINTN                     StartBit,
 557   IN      UINTN                     EndBit,
 558   IN      UINT16                    Value
 559   );
 560
 561 /**
 562   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 563   writes the result back to the bit field in the 16-bit port.
 564
 565   Reads the 16-bit PCI configuration register specified by Address, performs a
 566   bitwise inclusive OR between the read result and the value specified by
 567   OrData, and writes the result to the 16-bit PCI configuration register
 568   specified by Address. The value written to the PCI configuration register is
 569   returned. This function must guarantee that all PCI read and write operations
 570   are serialized. Extra left bits in OrData are stripped.
 571
 572   If Address > 0x0FFFFFFF, then ASSERT().
 573   If Address is not aligned on a 16-bit boundary, then ASSERT().
 574   If StartBit is greater than 15, then ASSERT().
 575   If EndBit is greater than 15, then ASSERT().
 576   If EndBit is less than StartBit, then ASSERT().
 577
 578   @param  Address   PCI configuration register to write.
 579   @param  StartBit  The ordinal of the least significant bit in the bit field.
 580                     Range 0..15.
 581   @param  EndBit    The ordinal of the most significant bit in the bit field.
 582                     Range 0..15.
 583   @param  OrData    The value to OR with the PCI configuration register.
 584
 585   @return The value written back to the PCI configuration register.
 586
 587 **/
 588 UINT16
 589 EFIAPI
 590 PciBitFieldOr16 (
 591   IN      UINTN                     Address,
 592   IN      UINTN                     StartBit,
 593   IN      UINTN                     EndBit,
 594   IN      UINT16                    OrData
 595   );
 596
 597 /**
 598   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 599   AND, and writes the result back to the bit field in the 16-bit register.
 600
 601   Reads the 16-bit PCI configuration register specified by Address, performs a
 602   bitwise AND between the read result and the value specified by AndData, and
 603   writes the result to the 16-bit PCI configuration register specified by
 604   Address. The value written to the PCI configuration register is returned.
 605   This function must guarantee that all PCI read and write operations are
 606   serialized. Extra left bits in AndData are stripped.
 607
 608   If Address > 0x0FFFFFFF, then ASSERT().
 609   If Address is not aligned on a 16-bit boundary, then ASSERT().
 610   If StartBit is greater than 15, then ASSERT().
 611   If EndBit is greater than 15, then ASSERT().
 612   If EndBit is less than StartBit, then ASSERT().
 613
 614   @param  Address   PCI configuration register to write.
 615   @param  StartBit  The ordinal of the least significant bit in the bit field.
 616                     Range 0..15.
 617   @param  EndBit    The ordinal of the most significant bit in the bit field.
 618                     Range 0..15.
 619   @param  AndData   The value to AND with the PCI configuration register.
 620
 621   @return The value written back to the PCI configuration register.
 622
 623 **/
 624 UINT16
 625 EFIAPI
 626 PciBitFieldAnd16 (
 627   IN      UINTN                     Address,
 628   IN      UINTN                     StartBit,
 629   IN      UINTN                     EndBit,
 630   IN      UINT16                    AndData
 631   );
 632
 633 /**
 634   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 635   bitwise inclusive OR, and writes the result back to the bit field in the
 636   16-bit port.
 637
 638   Reads the 16-bit PCI configuration register specified by Address, performs a
 639   bitwise AND followed by a bitwise inclusive OR between the read result and
 640   the value specified by AndData, and writes the result to the 16-bit PCI
 641   configuration register specified by Address. The value written to the PCI
 642   configuration register is returned. This function must guarantee that all PCI
 643   read and write operations are serialized. Extra left bits in both AndData and
 644   OrData are stripped.
 645
 646   If Address > 0x0FFFFFFF, then ASSERT().
 647   If Address is not aligned on a 16-bit boundary, then ASSERT().
 648   If StartBit is greater than 15, then ASSERT().
 649   If EndBit is greater than 15, then ASSERT().
 650   If EndBit is less than StartBit, then ASSERT().
 651
 652   @param  Address   PCI configuration register to write.
 653   @param  StartBit  The ordinal of the least significant bit in the bit field.
 654                     Range 0..15.
 655   @param  EndBit    The ordinal of the most significant bit in the bit field.
 656                     Range 0..15.
 657   @param  AndData   The value to AND with the PCI configuration register.
 658   @param  OrData    The value to OR with the result of the AND operation.
 659
 660   @return The value written back to the PCI configuration register.
 661
 662 **/
 663 UINT16
 664 EFIAPI
 665 PciBitFieldAndThenOr16 (
 666   IN      UINTN                     Address,
 667   IN      UINTN                     StartBit,
 668   IN      UINTN                     EndBit,
 669   IN      UINT16                    AndData,
 670   IN      UINT16                    OrData
 671   );
 672
 673 /**
 674   Reads a 32-bit PCI configuration register.
 675
 676   Reads and returns the 32-bit PCI configuration register specified by Address.
 677   This function must guarantee that all PCI read and write operations are
 678   serialized.
 679
 680   If Address > 0x0FFFFFFF, then ASSERT().
 681   If Address is not aligned on a 32-bit boundary, then ASSERT().
 682
 683   @param  Address Address that encodes the PCI Bus, Device, Function and
 684                   Register.
 685
 686   @return The read value from the PCI configuration register.
 687
 688 **/
 689 UINT32
 690 EFIAPI
 691 PciRead32 (
 692   IN      UINTN                     Address
 693   );
 694
 695 /**
 696   Writes a 32-bit PCI configuration register.
 697
 698   Writes the 32-bit PCI configuration register specified by Address with the
 699   value specified by Value. Value is returned. This function must guarantee
 700   that all PCI read and write operations are serialized.
 701
 702   If Address > 0x0FFFFFFF, then ASSERT().
 703   If Address is not aligned on a 32-bit boundary, then ASSERT().
 704
 705   @param  Address Address that encodes the PCI Bus, Device, Function and
 706                   Register.
 707   @param  Value   The value to write.
 708
 709   @return The value written to the PCI configuration register.
 710
 711 **/
 712 UINT32
 713 EFIAPI
 714 PciWrite32 (
 715   IN      UINTN                     Address,
 716   IN      UINT32                    Value
 717   );
 718
 719 /**
 720   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 721   a 32-bit value.
 722
 723   Reads the 32-bit PCI configuration register specified by Address, performs a
 724   bitwise inclusive OR between the read result and the value specified by
 725   OrData, and writes the result to the 32-bit PCI configuration register
 726   specified by Address. The value written to the PCI configuration register is
 727   returned. This function must guarantee that all PCI read and write operations
 728   are serialized.
 729
 730   If Address > 0x0FFFFFFF, then ASSERT().
 731   If Address is not aligned on a 32-bit boundary, then ASSERT().
 732
 733   @param  Address Address that encodes the PCI Bus, Device, Function and
 734                   Register.
 735   @param  OrData  The value to OR with the PCI configuration register.
 736
 737   @return The value written back to the PCI configuration register.
 738
 739 **/
 740 UINT32
 741 EFIAPI
 742 PciOr32 (
 743   IN      UINTN                     Address,
 744   IN      UINT32                    OrData
 745   );
 746
 747 /**
 748   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 749   value.
 750
 751   Reads the 32-bit PCI configuration register specified by Address, performs a
 752   bitwise AND between the read result and the value specified by AndData, and
 753   writes the result to the 32-bit PCI configuration register specified by
 754   Address. The value written to the PCI configuration register is returned.
 755   This function must guarantee that all PCI read and write operations are
 756   serialized.
 757
 758   If Address > 0x0FFFFFFF, then ASSERT().
 759   If Address is not aligned on a 32-bit boundary, then ASSERT().
 760
 761   @param  Address Address that encodes the PCI Bus, Device, Function and
 762                   Register.
 763   @param  AndData The value to AND with the PCI configuration register.
 764
 765   @return The value written back to the PCI configuration register.
 766
 767 **/
 768 UINT32
 769 EFIAPI
 770 PciAnd32 (
 771   IN      UINTN                     Address,
 772   IN      UINT32                    AndData
 773   );
 774
 775 /**
 776   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 777   value, followed a  bitwise inclusive OR with another 32-bit value.
 778
 779   Reads the 32-bit PCI configuration register specified by Address, performs a
 780   bitwise AND between the read result and the value specified by AndData,
 781   performs a bitwise inclusive OR between the result of the AND operation and
 782   the value specified by OrData, and writes the result to the 32-bit PCI
 783   configuration register specified by Address. The value written to the PCI
 784   configuration register is returned. This function must guarantee that all PCI
 785   read and write operations are serialized.
 786
 787   If Address > 0x0FFFFFFF, then ASSERT().
 788   If Address is not aligned on a 32-bit boundary, then ASSERT().
 789
 790   @param  Address Address that encodes the PCI Bus, Device, Function and
 791                   Register.
 792   @param  AndData The value to AND with the PCI configuration register.
 793   @param  OrData  The value to OR with the result of the AND operation.
 794
 795   @return The value written back to the PCI configuration register.
 796
 797 **/
 798 UINT32
 799 EFIAPI
 800 PciAndThenOr32 (
 801   IN      UINTN                     Address,
 802   IN      UINT32                    AndData,
 803   IN      UINT32                    OrData
 804   );
 805
 806 /**
 807   Reads a bit field of a PCI configuration register.
 808
 809   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 810   specified by the StartBit and the EndBit. The value of the bit field is
 811   returned.
 812
 813   If Address > 0x0FFFFFFF, then ASSERT().
 814   If Address is not aligned on a 32-bit boundary, then ASSERT().
 815   If StartBit is greater than 31, then ASSERT().
 816   If EndBit is greater than 31, then ASSERT().
 817   If EndBit is less than StartBit, then ASSERT().
 818
 819   @param  Address   PCI configuration register to read.
 820   @param  StartBit  The ordinal of the least significant bit in the bit field.
 821                     Range 0..31.
 822   @param  EndBit    The ordinal of the most significant bit in the bit field.
 823                     Range 0..31.
 824
 825   @return The value of the bit field read from the PCI configuration register.
 826
 827 **/
 828 UINT32
 829 EFIAPI
 830 PciBitFieldRead32 (
 831   IN      UINTN                     Address,
 832   IN      UINTN                     StartBit,
 833   IN      UINTN                     EndBit
 834   );
 835
 836 /**
 837   Writes a bit field to a PCI configuration register.
 838
 839   Writes Value to the bit field of the PCI configuration register. The bit
 840   field is specified by the StartBit and the EndBit. All other bits in the
 841   destination PCI configuration register are preserved. The new value of the
 842   32-bit register is returned.
 843
 844   If Address > 0x0FFFFFFF, then ASSERT().
 845   If Address is not aligned on a 32-bit boundary, then ASSERT().
 846   If StartBit is greater than 31, then ASSERT().
 847   If EndBit is greater than 31, then ASSERT().
 848   If EndBit is less than StartBit, then ASSERT().
 849
 850   @param  Address   PCI configuration register to write.
 851   @param  StartBit  The ordinal of the least significant bit in the bit field.
 852                     Range 0..31.
 853   @param  EndBit    The ordinal of the most significant bit in the bit field.
 854                     Range 0..31.
 855   @param  Value     New value of the bit field.
 856
 857   @return The value written back to the PCI configuration register.
 858
 859 **/
 860 UINT32
 861 EFIAPI
 862 PciBitFieldWrite32 (
 863   IN      UINTN                     Address,
 864   IN      UINTN                     StartBit,
 865   IN      UINTN                     EndBit,
 866   IN      UINT32                    Value
 867   );
 868
 869 /**
 870   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 871   writes the result back to the bit field in the 32-bit port.
 872
 873   Reads the 32-bit PCI configuration register specified by Address, performs a
 874   bitwise inclusive OR between the read result and the value specified by
 875   OrData, and writes the result to the 32-bit PCI configuration register
 876   specified by Address. The value written to the PCI configuration register is
 877   returned. This function must guarantee that all PCI read and write operations
 878   are serialized. Extra left bits in OrData are stripped.
 879
 880   If Address > 0x0FFFFFFF, then ASSERT().
 881   If Address is not aligned on a 32-bit boundary, then ASSERT().
 882   If StartBit is greater than 31, then ASSERT().
 883   If EndBit is greater than 31, then ASSERT().
 884   If EndBit is less than StartBit, then ASSERT().
 885
 886   @param  Address   PCI configuration register to write.
 887   @param  StartBit  The ordinal of the least significant bit in the bit field.
 888                     Range 0..31.
 889   @param  EndBit    The ordinal of the most significant bit in the bit field.
 890                     Range 0..31.
 891   @param  OrData    The value to OR with the PCI configuration register.
 892
 893   @return The value written back to the PCI configuration register.
 894
 895 **/
 896 UINT32
 897 EFIAPI
 898 PciBitFieldOr32 (
 899   IN      UINTN                     Address,
 900   IN      UINTN                     StartBit,
 901   IN      UINTN                     EndBit,
 902   IN      UINT32                    OrData
 903   );
 904
 905 /**
 906   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 907   AND, and writes the result back to the bit field in the 32-bit register.
 908
 909   Reads the 32-bit PCI configuration register specified by Address, performs a
 910   bitwise AND between the read result and the value specified by AndData, and
 911   writes the result to the 32-bit PCI configuration register specified by
 912   Address. The value written to the PCI configuration register is returned.
 913   This function must guarantee that all PCI read and write operations are
 914   serialized. Extra left bits in AndData are stripped.
 915
 916   If Address > 0x0FFFFFFF, then ASSERT().
 917   If Address is not aligned on a 32-bit boundary, then ASSERT().
 918   If StartBit is greater than 31, then ASSERT().
 919   If EndBit is greater than 31, then ASSERT().
 920   If EndBit is less than StartBit, then ASSERT().
 921
 922   @param  Address   PCI configuration register to write.
 923   @param  StartBit  The ordinal of the least significant bit in the bit field.
 924                     Range 0..31.
 925   @param  EndBit    The ordinal of the most significant bit in the bit field.
 926                     Range 0..31.
 927   @param  AndData   The value to AND with the PCI configuration register.
 928
 929   @return The value written back to the PCI configuration register.
 930
 931 **/
 932 UINT32
 933 EFIAPI
 934 PciBitFieldAnd32 (
 935   IN      UINTN                     Address,
 936   IN      UINTN                     StartBit,
 937   IN      UINTN                     EndBit,
 938   IN      UINT32                    AndData
 939   );
 940
 941 /**
 942   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 943   bitwise inclusive OR, and writes the result back to the bit field in the
 944   32-bit port.
 945
 946   Reads the 32-bit PCI configuration register specified by Address, performs a
 947   bitwise AND followed by a bitwise inclusive OR between the read result and
 948   the value specified by AndData, and writes the result to the 32-bit PCI
 949   configuration register specified by Address. The value written to the PCI
 950   configuration register is returned. This function must guarantee that all PCI
 951   read and write operations are serialized. Extra left bits in both AndData and
 952   OrData are stripped.
 953
 954   If Address > 0x0FFFFFFF, then ASSERT().
 955   If Address is not aligned on a 32-bit boundary, then ASSERT().
 956   If StartBit is greater than 31, then ASSERT().
 957   If EndBit is greater than 31, then ASSERT().
 958   If EndBit is less than StartBit, then ASSERT().
 959
 960   @param  Address   PCI configuration register to write.
 961   @param  StartBit  The ordinal of the least significant bit in the bit field.
 962                     Range 0..31.
 963   @param  EndBit    The ordinal of the most significant bit in the bit field.
 964                     Range 0..31.
 965   @param  AndData   The value to AND with the PCI configuration register.
 966   @param  OrData    The value to OR with the result of the AND operation.
 967
 968   @return The value written back to the PCI configuration register.
 969
 970 **/
 971 UINT32
 972 EFIAPI
 973 PciBitFieldAndThenOr32 (
 974   IN      UINTN                     Address,
 975   IN      UINTN                     StartBit,
 976   IN      UINTN                     EndBit,
 977   IN      UINT32                    AndData,
 978   IN      UINT32                    OrData
 979   );
 980
 981 /**
 982   Reads a range of PCI configuration registers into a caller supplied buffer.
 983
 984   Reads the range of PCI configuration registers specified by StartAddress and
 985   Size into the buffer specified by Buffer. This function only allows the PCI
 986   configuration registers from a single PCI function to be read. Size is
 987   returned. When possible 32-bit PCI configuration read cycles are used to read
 988   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 989   and 16-bit PCI configuration read cycles may be used at the beginning and the
 990   end of the range.
 991
 992   If StartAddress > 0x0FFFFFFF, then ASSERT().
 993   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 994   If Size > 0 and Buffer is NULL, then ASSERT().
 995
 996   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 997                         Function and Register.
 998   @param  Size          Size in bytes of the transfer.
 999   @param  Buffer        Pointer to a buffer receiving the data read.
1000
1001   @return Size
1002
1003 **/
1004 UINTN
1005 EFIAPI
1006 PciReadBuffer (
1007   IN      UINTN                     StartAddress,
1008   IN      UINTN                     Size,
1009   OUT     VOID                      *Buffer
1010   );
1011
1012 /**
1013   Copies the data in a caller supplied buffer to a specified range of PCI
1014   configuration space.
1015
1016   Writes the range of PCI configuration registers specified by StartAddress and
1017   Size from the buffer specified by Buffer. This function only allows the PCI
1018   configuration registers from a single PCI function to be written. Size is
1019   returned. When possible 32-bit PCI configuration write cycles are used to
1020   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1021   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1022   and the end of the range.
1023
1024   If StartAddress > 0x0FFFFFFF, then ASSERT().
1025   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1026   If Size > 0 and Buffer is NULL, then ASSERT().
1027
1028   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1029                         Function and Register.
1030   @param  Size          Size in bytes of the transfer.
1031   @param  Buffer        Pointer to a buffer containing the data to write.
1032
1033   @return Size written to StartAddress.
1034
1035 **/
1036 UINTN
1037 EFIAPI
1038 PciWriteBuffer (
1039   IN      UINTN                     StartAddress,
1040   IN      UINTN                     Size,
1041   IN      VOID                      *Buffer
1042   );
1043
1044 #endif