MdePkg/Include/Ppi/PciCfg2.h

   1 /** @file
   2   This file declares PciCfg2 PPI.
   3
   4   This ppi Provides platform or chipset-specific access to
   5   the PCI configuration space for a specific PCI segment.
   6
   7   Copyright (c) 2006 - 2008, Intel Corporation
   8   All rights reserved. This program and the accompanying materials
   9   are licensed and made available under the terms and conditions of the BSD License
  10   which accompanies this distribution.  The full text of the license may be found at
  11   http://opensource.org/licenses/bsd-license.php
  12
  13   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16   @par Revision Reference:
  17   This PPI is defined in PI
  18   Version 1.00.
  19
  20 **/
  21
  22 #ifndef __PEI_PCI_CFG2_H__
  23 #define __PEI_PCI_CFG2_H__
  24
  25 #include <ProcessorBind.h>
  26 #include <Pi/PiPeiCis.h>
  27
  28 #define EFI_PEI_PCI_CFG2_PPI_GUID \
  29   { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }
  30
  31
  32 typedef struct _EFI_PEI_PCI_CFG2_PPI   EFI_PEI_PCI_CFG2_PPI;
  33
  34 #define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \
  35   (((bus) << 24) | \
  36   ((dev) << 16) | \
  37   ((func) << 8) | \
  38   ((reg) < 256 ? (reg) : ((UINT64)(reg) << 32)));
  39
  40 //
  41 // EFI_PEI_PCI_CFG_PPI_WIDTH
  42 //
  43 typedef enum {
  44   EfiPeiPciCfgWidthUint8  = 0,
  45   EfiPeiPciCfgWidthUint16 = 1,
  46   EfiPeiPciCfgWidthUint32 = 2,
  47   EfiPeiPciCfgWidthUint64 = 3,
  48   EfiPeiPciCfgWidthMaximum
  49 } EFI_PEI_PCI_CFG_PPI_WIDTH;
  50
  51 //
  52 // EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS
  53 //
  54 typedef struct {
  55   UINT8   Register;
  56   UINT8   Function;
  57   UINT8   Device;
  58   UINT8   Bus;
  59   UINT32  ExtendedRegister;
  60 } EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;
  61
  62 /**
  63   Reads from or write to a given location in the PCI configuration space.
  64
  65   @param  PeiServices     An indirect pointer to the PEI Services Table published by the PEI Foundation.
  66
  67   @param  This            Pointer to local data for the interface.
  68
  69   @param  Width           The width of the access. Enumerated in bytes.
  70                           See EFI_PEI_PCI_CFG_PPI_WIDTH above.
  71
  72   @param  Address         The physical address of the access. The format of
  73                           the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.
  74
  75   @param  Buffer          A pointer to the buffer of data..
  76
  77
  78   @retval EFI_SUCCESS           The function completed successfully.
  79
  80   @retval EFI_DEVICE_ERROR      There was a problem with the transaction.
  81
  82   @retval EFI_DEVICE_NOT_READY  The device is not capable of supporting the operation at this
  83                                 time.
  84
  85 **/
  86 typedef
  87 EFI_STATUS
  88 (EFIAPI *EFI_PEI_PCI_CFG2_PPI_IO)(
  89   IN CONST  EFI_PEI_SERVICES          **PeiServices,
  90   IN CONST  EFI_PEI_PCI_CFG2_PPI      *This,
  91   IN        EFI_PEI_PCI_CFG_PPI_WIDTH Width,
  92   IN        UINT64                    Address,
  93   IN OUT    VOID                      *Buffer
  94 );
  95
  96
  97 /**
  98   Performs a read-modify-write operation on the contents
  99   from a given location in the PCI configuration space.
 100
 101   @param  PeiServices     An indirect pointer to the PEI Services Table
 102                           published by the PEI Foundation.
 103
 104   @param  This            Pointer to local data for the interface.
 105
 106   @param  Width           The width of the access. Enumerated in bytes. Type
 107                           EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().
 108
 109   @param  Address         The physical address of the access.
 110
 111   @param  SetBits         Points to value to bitwise-OR with the read configuration value.
 112
 113                           The size of the value is determined by Width.
 114
 115   @param  ClearBits       Points to the value to negate and bitwise-AND with the read configuration value.
 116                           The size of the value is determined by Width.
 117
 118
 119   @retval EFI_SUCCESS           The function completed successfully.
 120
 121   @retval EFI_DEVICE_ERROR      There was a problem with the transaction.
 122
 123   @retval EFI_DEVICE_NOT_READY  The device is not capable of supporting
 124                                 the operation at this time.
 125
 126 **/
 127 typedef
 128 EFI_STATUS
 129 (EFIAPI *EFI_PEI_PCI_CFG2_PPI_RW)(
 130   IN CONST  EFI_PEI_SERVICES          **PeiServices,
 131   IN CONST  EFI_PEI_PCI_CFG2_PPI      *This,
 132   IN        EFI_PEI_PCI_CFG_PPI_WIDTH Width,
 133   IN        UINT64                    Address,
 134   IN CONST  VOID                      *SetBits,
 135   IN CONST  VOID                      *ClearBits
 136 );
 137
 138 /**
 139   @par Ppi Description:
 140   The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI
 141   controllers behind a PCI root bridge controller.
 142
 143   @param Read     PCI read services.  See the Read() function description.
 144
 145   @param Write    PCI write services.  See the Write() function description.
 146
 147   @param Modify   PCI read-modify-write services.  See the Modify() function description.
 148
 149   @param Segment  The PCI bus segment which the specified functions will access.
 150
 151 **/
 152 struct _EFI_PEI_PCI_CFG2_PPI {
 153   EFI_PEI_PCI_CFG2_PPI_IO  Read;
 154   EFI_PEI_PCI_CFG2_PPI_IO  Write;
 155   EFI_PEI_PCI_CFG2_PPI_RW  Modify;
 156   UINT16                  Segment;
 157 };
 158
 159
 160 extern EFI_GUID gEfiPciCfg2PpiGuid;
 161
 162 #endif