MdePkg/Include/Protocol/DebugSupport.h

   1 /** @file
   2   DebugSupport protocol and supporting definitions as defined in the UEFI2.4
   3   specification.
   4
   5   The DebugSupport protocol is used by source level debuggers to abstract the
   6   processor and handle context save and restore operations.
   7
   8 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   9 Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
  10 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
  11
  12 SPDX-License-Identifier: BSD-2-Clause-Patent
  13
  14 **/
  15
  16 #ifndef __DEBUG_SUPPORT_H__
  17 #define __DEBUG_SUPPORT_H__
  18
  19 #include <IndustryStandard/PeImage.h>
  20
  21 typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;
  22
  23 ///
  24 /// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}.
  25 ///
  26 #define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \
  27   { \
  28     0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \
  29   }
  30
  31 ///
  32 /// Processor exception to be hooked.
  33 /// All exception types for IA32, X64, Itanium and EBC processors are defined.
  34 ///
  35 typedef INTN  EFI_EXCEPTION_TYPE;
  36
  37 ///
  38 ///  IA-32 processor exception types.
  39 ///
  40 #define EXCEPT_IA32_DIVIDE_ERROR    0
  41 #define EXCEPT_IA32_DEBUG           1
  42 #define EXCEPT_IA32_NMI             2
  43 #define EXCEPT_IA32_BREAKPOINT      3
  44 #define EXCEPT_IA32_OVERFLOW        4
  45 #define EXCEPT_IA32_BOUND           5
  46 #define EXCEPT_IA32_INVALID_OPCODE  6
  47 #define EXCEPT_IA32_DOUBLE_FAULT    8
  48 #define EXCEPT_IA32_INVALID_TSS     10
  49 #define EXCEPT_IA32_SEG_NOT_PRESENT 11
  50 #define EXCEPT_IA32_STACK_FAULT     12
  51 #define EXCEPT_IA32_GP_FAULT        13
  52 #define EXCEPT_IA32_PAGE_FAULT      14
  53 #define EXCEPT_IA32_FP_ERROR        16
  54 #define EXCEPT_IA32_ALIGNMENT_CHECK 17
  55 #define EXCEPT_IA32_MACHINE_CHECK   18
  56 #define EXCEPT_IA32_SIMD            19
  57
  58 ///
  59 /// FXSAVE_STATE.
  60 /// FP / MMX / XMM registers (see fxrstor instruction definition).
  61 ///
  62 typedef struct {
  63   UINT16  Fcw;
  64   UINT16  Fsw;
  65   UINT16  Ftw;
  66   UINT16  Opcode;
  67   UINT32  Eip;
  68   UINT16  Cs;
  69   UINT16  Reserved1;
  70   UINT32  DataOffset;
  71   UINT16  Ds;
  72   UINT8   Reserved2[10];
  73   UINT8   St0Mm0[10], Reserved3[6];
  74   UINT8   St1Mm1[10], Reserved4[6];
  75   UINT8   St2Mm2[10], Reserved5[6];
  76   UINT8   St3Mm3[10], Reserved6[6];
  77   UINT8   St4Mm4[10], Reserved7[6];
  78   UINT8   St5Mm5[10], Reserved8[6];
  79   UINT8   St6Mm6[10], Reserved9[6];
  80   UINT8   St7Mm7[10], Reserved10[6];
  81   UINT8   Xmm0[16];
  82   UINT8   Xmm1[16];
  83   UINT8   Xmm2[16];
  84   UINT8   Xmm3[16];
  85   UINT8   Xmm4[16];
  86   UINT8   Xmm5[16];
  87   UINT8   Xmm6[16];
  88   UINT8   Xmm7[16];
  89   UINT8   Reserved11[14 * 16];
  90 } EFI_FX_SAVE_STATE_IA32;
  91
  92 ///
  93 ///  IA-32 processor context definition.
  94 ///
  95 typedef struct {
  96   UINT32                 ExceptionData;
  97   EFI_FX_SAVE_STATE_IA32 FxSaveState;
  98   UINT32                 Dr0;
  99   UINT32                 Dr1;
 100   UINT32                 Dr2;
 101   UINT32                 Dr3;
 102   UINT32                 Dr6;
 103   UINT32                 Dr7;
 104   UINT32                 Cr0;
 105   UINT32                 Cr1;  /* Reserved */
 106   UINT32                 Cr2;
 107   UINT32                 Cr3;
 108   UINT32                 Cr4;
 109   UINT32                 Eflags;
 110   UINT32                 Ldtr;
 111   UINT32                 Tr;
 112   UINT32                 Gdtr[2];
 113   UINT32                 Idtr[2];
 114   UINT32                 Eip;
 115   UINT32                 Gs;
 116   UINT32                 Fs;
 117   UINT32                 Es;
 118   UINT32                 Ds;
 119   UINT32                 Cs;
 120   UINT32                 Ss;
 121   UINT32                 Edi;
 122   UINT32                 Esi;
 123   UINT32                 Ebp;
 124   UINT32                 Esp;
 125   UINT32                 Ebx;
 126   UINT32                 Edx;
 127   UINT32                 Ecx;
 128   UINT32                 Eax;
 129 } EFI_SYSTEM_CONTEXT_IA32;
 130
 131 ///
 132 ///  x64 processor exception types.
 133 ///
 134 #define EXCEPT_X64_DIVIDE_ERROR    0
 135 #define EXCEPT_X64_DEBUG           1
 136 #define EXCEPT_X64_NMI             2
 137 #define EXCEPT_X64_BREAKPOINT      3
 138 #define EXCEPT_X64_OVERFLOW        4
 139 #define EXCEPT_X64_BOUND           5
 140 #define EXCEPT_X64_INVALID_OPCODE  6
 141 #define EXCEPT_X64_DOUBLE_FAULT    8
 142 #define EXCEPT_X64_INVALID_TSS     10
 143 #define EXCEPT_X64_SEG_NOT_PRESENT 11
 144 #define EXCEPT_X64_STACK_FAULT     12
 145 #define EXCEPT_X64_GP_FAULT        13
 146 #define EXCEPT_X64_PAGE_FAULT      14
 147 #define EXCEPT_X64_FP_ERROR        16
 148 #define EXCEPT_X64_ALIGNMENT_CHECK 17
 149 #define EXCEPT_X64_MACHINE_CHECK   18
 150 #define EXCEPT_X64_SIMD            19
 151
 152 ///
 153 /// FXSAVE_STATE.
 154 /// FP / MMX / XMM registers (see fxrstor instruction definition).
 155 ///
 156 typedef struct {
 157   UINT16  Fcw;
 158   UINT16  Fsw;
 159   UINT16  Ftw;
 160   UINT16  Opcode;
 161   UINT64  Rip;
 162   UINT64  DataOffset;
 163   UINT8   Reserved1[8];
 164   UINT8   St0Mm0[10], Reserved2[6];
 165   UINT8   St1Mm1[10], Reserved3[6];
 166   UINT8   St2Mm2[10], Reserved4[6];
 167   UINT8   St3Mm3[10], Reserved5[6];
 168   UINT8   St4Mm4[10], Reserved6[6];
 169   UINT8   St5Mm5[10], Reserved7[6];
 170   UINT8   St6Mm6[10], Reserved8[6];
 171   UINT8   St7Mm7[10], Reserved9[6];
 172   UINT8   Xmm0[16];
 173   UINT8   Xmm1[16];
 174   UINT8   Xmm2[16];
 175   UINT8   Xmm3[16];
 176   UINT8   Xmm4[16];
 177   UINT8   Xmm5[16];
 178   UINT8   Xmm6[16];
 179   UINT8   Xmm7[16];
 180   //
 181   // NOTE: UEFI 2.0 spec definition as follows.
 182   //
 183   UINT8   Reserved11[14 * 16];
 184 } EFI_FX_SAVE_STATE_X64;
 185
 186 ///
 187 ///  x64 processor context definition.
 188 ///
 189 typedef struct {
 190   UINT64                ExceptionData;
 191   EFI_FX_SAVE_STATE_X64 FxSaveState;
 192   UINT64                Dr0;
 193   UINT64                Dr1;
 194   UINT64                Dr2;
 195   UINT64                Dr3;
 196   UINT64                Dr6;
 197   UINT64                Dr7;
 198   UINT64                Cr0;
 199   UINT64                Cr1;  /* Reserved */
 200   UINT64                Cr2;
 201   UINT64                Cr3;
 202   UINT64                Cr4;
 203   UINT64                Cr8;
 204   UINT64                Rflags;
 205   UINT64                Ldtr;
 206   UINT64                Tr;
 207   UINT64                Gdtr[2];
 208   UINT64                Idtr[2];
 209   UINT64                Rip;
 210   UINT64                Gs;
 211   UINT64                Fs;
 212   UINT64                Es;
 213   UINT64                Ds;
 214   UINT64                Cs;
 215   UINT64                Ss;
 216   UINT64                Rdi;
 217   UINT64                Rsi;
 218   UINT64                Rbp;
 219   UINT64                Rsp;
 220   UINT64                Rbx;
 221   UINT64                Rdx;
 222   UINT64                Rcx;
 223   UINT64                Rax;
 224   UINT64                R8;
 225   UINT64                R9;
 226   UINT64                R10;
 227   UINT64                R11;
 228   UINT64                R12;
 229   UINT64                R13;
 230   UINT64                R14;
 231   UINT64                R15;
 232 } EFI_SYSTEM_CONTEXT_X64;
 233
 234 ///
 235 ///  Itanium Processor Family Exception types.
 236 ///
 237 #define EXCEPT_IPF_VHTP_TRANSLATION       0
 238 #define EXCEPT_IPF_INSTRUCTION_TLB        1
 239 #define EXCEPT_IPF_DATA_TLB               2
 240 #define EXCEPT_IPF_ALT_INSTRUCTION_TLB    3
 241 #define EXCEPT_IPF_ALT_DATA_TLB           4
 242 #define EXCEPT_IPF_DATA_NESTED_TLB        5
 243 #define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6
 244 #define EXCEPT_IPF_DATA_KEY_MISSED        7
 245 #define EXCEPT_IPF_DIRTY_BIT              8
 246 #define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9
 247 #define EXCEPT_IPF_DATA_ACCESS_BIT        10
 248 #define EXCEPT_IPF_BREAKPOINT             11
 249 #define EXCEPT_IPF_EXTERNAL_INTERRUPT     12
 250 //
 251 // 13 - 19 reserved
 252 //
 253 #define EXCEPT_IPF_PAGE_NOT_PRESENT           20
 254 #define EXCEPT_IPF_KEY_PERMISSION             21
 255 #define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS  22
 256 #define EXCEPT_IPF_DATA_ACCESS_RIGHTS         23
 257 #define EXCEPT_IPF_GENERAL_EXCEPTION          24
 258 #define EXCEPT_IPF_DISABLED_FP_REGISTER       25
 259 #define EXCEPT_IPF_NAT_CONSUMPTION            26
 260 #define EXCEPT_IPF_SPECULATION                27
 261 //
 262 // 28 reserved
 263 //
 264 #define EXCEPT_IPF_DEBUG                          29
 265 #define EXCEPT_IPF_UNALIGNED_REFERENCE            30
 266 #define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE     31
 267 #define EXCEPT_IPF_FP_FAULT                       32
 268 #define EXCEPT_IPF_FP_TRAP                        33
 269 #define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP  34
 270 #define EXCEPT_IPF_TAKEN_BRANCH                   35
 271 #define EXCEPT_IPF_SINGLE_STEP                    36
 272 //
 273 // 37 - 44 reserved
 274 //
 275 #define EXCEPT_IPF_IA32_EXCEPTION 45
 276 #define EXCEPT_IPF_IA32_INTERCEPT 46
 277 #define EXCEPT_IPF_IA32_INTERRUPT 47
 278
 279 ///
 280 ///  IPF processor context definition.
 281 ///
 282 typedef struct {
 283   //
 284   // The first reserved field is necessary to preserve alignment for the correct
 285   // bits in UNAT and to insure F2 is 16 byte aligned.
 286   //
 287   UINT64  Reserved;
 288   UINT64  R1;
 289   UINT64  R2;
 290   UINT64  R3;
 291   UINT64  R4;
 292   UINT64  R5;
 293   UINT64  R6;
 294   UINT64  R7;
 295   UINT64  R8;
 296   UINT64  R9;
 297   UINT64  R10;
 298   UINT64  R11;
 299   UINT64  R12;
 300   UINT64  R13;
 301   UINT64  R14;
 302   UINT64  R15;
 303   UINT64  R16;
 304   UINT64  R17;
 305   UINT64  R18;
 306   UINT64  R19;
 307   UINT64  R20;
 308   UINT64  R21;
 309   UINT64  R22;
 310   UINT64  R23;
 311   UINT64  R24;
 312   UINT64  R25;
 313   UINT64  R26;
 314   UINT64  R27;
 315   UINT64  R28;
 316   UINT64  R29;
 317   UINT64  R30;
 318   UINT64  R31;
 319
 320   UINT64  F2[2];
 321   UINT64  F3[2];
 322   UINT64  F4[2];
 323   UINT64  F5[2];
 324   UINT64  F6[2];
 325   UINT64  F7[2];
 326   UINT64  F8[2];
 327   UINT64  F9[2];
 328   UINT64  F10[2];
 329   UINT64  F11[2];
 330   UINT64  F12[2];
 331   UINT64  F13[2];
 332   UINT64  F14[2];
 333   UINT64  F15[2];
 334   UINT64  F16[2];
 335   UINT64  F17[2];
 336   UINT64  F18[2];
 337   UINT64  F19[2];
 338   UINT64  F20[2];
 339   UINT64  F21[2];
 340   UINT64  F22[2];
 341   UINT64  F23[2];
 342   UINT64  F24[2];
 343   UINT64  F25[2];
 344   UINT64  F26[2];
 345   UINT64  F27[2];
 346   UINT64  F28[2];
 347   UINT64  F29[2];
 348   UINT64  F30[2];
 349   UINT64  F31[2];
 350
 351   UINT64  Pr;
 352
 353   UINT64  B0;
 354   UINT64  B1;
 355   UINT64  B2;
 356   UINT64  B3;
 357   UINT64  B4;
 358   UINT64  B5;
 359   UINT64  B6;
 360   UINT64  B7;
 361
 362   //
 363   // application registers
 364   //
 365   UINT64  ArRsc;
 366   UINT64  ArBsp;
 367   UINT64  ArBspstore;
 368   UINT64  ArRnat;
 369
 370   UINT64  ArFcr;
 371
 372   UINT64  ArEflag;
 373   UINT64  ArCsd;
 374   UINT64  ArSsd;
 375   UINT64  ArCflg;
 376   UINT64  ArFsr;
 377   UINT64  ArFir;
 378   UINT64  ArFdr;
 379
 380   UINT64  ArCcv;
 381
 382   UINT64  ArUnat;
 383
 384   UINT64  ArFpsr;
 385
 386   UINT64  ArPfs;
 387   UINT64  ArLc;
 388   UINT64  ArEc;
 389
 390   //
 391   // control registers
 392   //
 393   UINT64  CrDcr;
 394   UINT64  CrItm;
 395   UINT64  CrIva;
 396   UINT64  CrPta;
 397   UINT64  CrIpsr;
 398   UINT64  CrIsr;
 399   UINT64  CrIip;
 400   UINT64  CrIfa;
 401   UINT64  CrItir;
 402   UINT64  CrIipa;
 403   UINT64  CrIfs;
 404   UINT64  CrIim;
 405   UINT64  CrIha;
 406
 407   //
 408   // debug registers
 409   //
 410   UINT64  Dbr0;
 411   UINT64  Dbr1;
 412   UINT64  Dbr2;
 413   UINT64  Dbr3;
 414   UINT64  Dbr4;
 415   UINT64  Dbr5;
 416   UINT64  Dbr6;
 417   UINT64  Dbr7;
 418
 419   UINT64  Ibr0;
 420   UINT64  Ibr1;
 421   UINT64  Ibr2;
 422   UINT64  Ibr3;
 423   UINT64  Ibr4;
 424   UINT64  Ibr5;
 425   UINT64  Ibr6;
 426   UINT64  Ibr7;
 427
 428   //
 429   // virtual registers - nat bits for R1-R31
 430   //
 431   UINT64  IntNat;
 432
 433 } EFI_SYSTEM_CONTEXT_IPF;
 434
 435 ///
 436 ///  EBC processor exception types.
 437 ///
 438 #define EXCEPT_EBC_UNDEFINED            0
 439 #define EXCEPT_EBC_DIVIDE_ERROR         1
 440 #define EXCEPT_EBC_DEBUG                2
 441 #define EXCEPT_EBC_BREAKPOINT           3
 442 #define EXCEPT_EBC_OVERFLOW             4
 443 #define EXCEPT_EBC_INVALID_OPCODE       5   ///< Opcode out of range.
 444 #define EXCEPT_EBC_STACK_FAULT          6
 445 #define EXCEPT_EBC_ALIGNMENT_CHECK      7
 446 #define EXCEPT_EBC_INSTRUCTION_ENCODING 8   ///< Malformed instruction.
 447 #define EXCEPT_EBC_BAD_BREAK            9   ///< BREAK 0 or undefined BREAK.
 448 #define EXCEPT_EBC_STEP                 10  ///< To support debug stepping.
 449 ///
 450 /// For coding convenience, define the maximum valid EBC exception.
 451 ///
 452 #define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP
 453
 454 ///
 455 ///  EBC processor context definition.
 456 ///
 457 typedef struct {
 458   UINT64  R0;
 459   UINT64  R1;
 460   UINT64  R2;
 461   UINT64  R3;
 462   UINT64  R4;
 463   UINT64  R5;
 464   UINT64  R6;
 465   UINT64  R7;
 466   UINT64  Flags;
 467   UINT64  ControlFlags;
 468   UINT64  Ip;
 469 } EFI_SYSTEM_CONTEXT_EBC;
 470
 471
 472
 473 ///
 474 ///  ARM processor exception types.
 475 ///
 476 #define EXCEPT_ARM_RESET                    0
 477 #define EXCEPT_ARM_UNDEFINED_INSTRUCTION    1
 478 #define EXCEPT_ARM_SOFTWARE_INTERRUPT       2
 479 #define EXCEPT_ARM_PREFETCH_ABORT           3
 480 #define EXCEPT_ARM_DATA_ABORT               4
 481 #define EXCEPT_ARM_RESERVED                 5
 482 #define EXCEPT_ARM_IRQ                      6
 483 #define EXCEPT_ARM_FIQ                      7
 484
 485 ///
 486 /// For coding convenience, define the maximum valid ARM exception.
 487 ///
 488 #define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ
 489
 490 ///
 491 ///  ARM processor context definition.
 492 ///
 493 typedef struct {
 494   UINT32  R0;
 495   UINT32  R1;
 496   UINT32  R2;
 497   UINT32  R3;
 498   UINT32  R4;
 499   UINT32  R5;
 500   UINT32  R6;
 501   UINT32  R7;
 502   UINT32  R8;
 503   UINT32  R9;
 504   UINT32  R10;
 505   UINT32  R11;
 506   UINT32  R12;
 507   UINT32  SP;
 508   UINT32  LR;
 509   UINT32  PC;
 510   UINT32  CPSR;
 511   UINT32  DFSR;
 512   UINT32  DFAR;
 513   UINT32  IFSR;
 514   UINT32  IFAR;
 515 } EFI_SYSTEM_CONTEXT_ARM;
 516
 517
 518 ///
 519 ///  AARCH64 processor exception types.
 520 ///
 521 #define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS    0
 522 #define EXCEPT_AARCH64_IRQ                       1
 523 #define EXCEPT_AARCH64_FIQ                       2
 524 #define EXCEPT_AARCH64_SERROR                    3
 525
 526 ///
 527 /// For coding convenience, define the maximum valid ARM exception.
 528 ///
 529 #define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR
 530
 531 typedef struct {
 532   // General Purpose Registers
 533   UINT64  X0;
 534   UINT64  X1;
 535   UINT64  X2;
 536   UINT64  X3;
 537   UINT64  X4;
 538   UINT64  X5;
 539   UINT64  X6;
 540   UINT64  X7;
 541   UINT64  X8;
 542   UINT64  X9;
 543   UINT64  X10;
 544   UINT64  X11;
 545   UINT64  X12;
 546   UINT64  X13;
 547   UINT64  X14;
 548   UINT64  X15;
 549   UINT64  X16;
 550   UINT64  X17;
 551   UINT64  X18;
 552   UINT64  X19;
 553   UINT64  X20;
 554   UINT64  X21;
 555   UINT64  X22;
 556   UINT64  X23;
 557   UINT64  X24;
 558   UINT64  X25;
 559   UINT64  X26;
 560   UINT64  X27;
 561   UINT64  X28;
 562   UINT64  FP;   // x29 - Frame pointer
 563   UINT64  LR;   // x30 - Link Register
 564   UINT64  SP;   // x31 - Stack pointer
 565
 566   // FP/SIMD Registers
 567   UINT64  V0[2];
 568   UINT64  V1[2];
 569   UINT64  V2[2];
 570   UINT64  V3[2];
 571   UINT64  V4[2];
 572   UINT64  V5[2];
 573   UINT64  V6[2];
 574   UINT64  V7[2];
 575   UINT64  V8[2];
 576   UINT64  V9[2];
 577   UINT64  V10[2];
 578   UINT64  V11[2];
 579   UINT64  V12[2];
 580   UINT64  V13[2];
 581   UINT64  V14[2];
 582   UINT64  V15[2];
 583   UINT64  V16[2];
 584   UINT64  V17[2];
 585   UINT64  V18[2];
 586   UINT64  V19[2];
 587   UINT64  V20[2];
 588   UINT64  V21[2];
 589   UINT64  V22[2];
 590   UINT64  V23[2];
 591   UINT64  V24[2];
 592   UINT64  V25[2];
 593   UINT64  V26[2];
 594   UINT64  V27[2];
 595   UINT64  V28[2];
 596   UINT64  V29[2];
 597   UINT64  V30[2];
 598   UINT64  V31[2];
 599
 600   UINT64  ELR;  // Exception Link Register
 601   UINT64  SPSR; // Saved Processor Status Register
 602   UINT64  FPSR; // Floating Point Status Register
 603   UINT64  ESR;  // Exception syndrome register
 604   UINT64  FAR;  // Fault Address Register
 605 } EFI_SYSTEM_CONTEXT_AARCH64;
 606
 607 ///
 608 /// RISC-V processor exception types.
 609 ///
 610 #define EXCEPT_RISCV_INST_MISALIGNED              0
 611 #define EXCEPT_RISCV_INST_ACCESS_FAULT            1
 612 #define EXCEPT_RISCV_ILLEGAL_INST                 2
 613 #define EXCEPT_RISCV_BREAKPOINT                   3
 614 #define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED      4
 615 #define EXCEPT_RISCV_LOAD_ACCESS_FAULT            5
 616 #define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6
 617 #define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT       7
 618 #define EXCEPT_RISCV_ENV_CALL_FROM_UMODE          8
 619 #define EXCEPT_RISCV_ENV_CALL_FROM_SMODE          9
 620 #define EXCEPT_RISCV_ENV_CALL_FROM_HMODE          10
 621 #define EXCEPT_RISCV_ENV_CALL_FROM_MMODE          11
 622
 623 #define EXCEPT_RISCV_SOFTWARE_INT       0x0
 624 #define EXCEPT_RISCV_TIMER_INT          0x1
 625
 626 typedef struct {
 627   UINT64  X0;
 628   UINT64  X1;
 629   UINT64  X2;
 630   UINT64  X3;
 631   UINT64  X4;
 632   UINT64  X5;
 633   UINT64  X6;
 634   UINT64  X7;
 635   UINT64  X8;
 636   UINT64  X9;
 637   UINT64  X10;
 638   UINT64  X11;
 639   UINT64  X12;
 640   UINT64  X13;
 641   UINT64  X14;
 642   UINT64  X15;
 643   UINT64  X16;
 644   UINT64  X17;
 645   UINT64  X18;
 646   UINT64  X19;
 647   UINT64  X20;
 648   UINT64  X21;
 649   UINT64  X22;
 650   UINT64  X23;
 651   UINT64  X24;
 652   UINT64  X25;
 653   UINT64  X26;
 654   UINT64  X27;
 655   UINT64  X28;
 656   UINT64  X29;
 657   UINT64  X30;
 658   UINT64  X31;
 659 } EFI_SYSTEM_CONTEXT_RISCV64;
 660
 661 ///
 662 /// Universal EFI_SYSTEM_CONTEXT definition.
 663 ///
 664 typedef union {
 665   EFI_SYSTEM_CONTEXT_EBC  *SystemContextEbc;
 666   EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;
 667   EFI_SYSTEM_CONTEXT_X64  *SystemContextX64;
 668   EFI_SYSTEM_CONTEXT_IPF  *SystemContextIpf;
 669   EFI_SYSTEM_CONTEXT_ARM  *SystemContextArm;
 670   EFI_SYSTEM_CONTEXT_AARCH64  *SystemContextAArch64;
 671   EFI_SYSTEM_CONTEXT_RISCV64  *SystemContextRiscV64;
 672 } EFI_SYSTEM_CONTEXT;
 673
 674 //
 675 // DebugSupport callback function prototypes
 676 //
 677
 678 /**
 679   Registers and enables an exception callback function for the specified exception.
 680
 681   @param  ExceptionType         Exception types in EBC, IA-32, x64, or IPF.
 682   @param  SystemContext         Exception content.
 683
 684 **/
 685 typedef
 686 VOID
 687 (EFIAPI *EFI_EXCEPTION_CALLBACK)(
 688   IN     EFI_EXCEPTION_TYPE               ExceptionType,
 689   IN OUT EFI_SYSTEM_CONTEXT               SystemContext
 690   );
 691
 692 /**
 693   Registers and enables the on-target debug agent's periodic entry point.
 694
 695   @param  SystemContext         Exception content.
 696
 697 **/
 698 typedef
 699 VOID
 700 (EFIAPI *EFI_PERIODIC_CALLBACK)(
 701   IN OUT EFI_SYSTEM_CONTEXT               SystemContext
 702   );
 703
 704 ///
 705 /// Machine type definition
 706 ///
 707 typedef enum {
 708   IsaIa32 = IMAGE_FILE_MACHINE_I386,           ///< 0x014C
 709   IsaX64  = IMAGE_FILE_MACHINE_X64,            ///< 0x8664
 710   IsaIpf  = IMAGE_FILE_MACHINE_IA64,           ///< 0x0200
 711   IsaEbc  = IMAGE_FILE_MACHINE_EBC,            ///< 0x0EBC
 712   IsaArm  = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2
 713   IsaAArch64  = IMAGE_FILE_MACHINE_ARM64       ///< 0xAA64
 714 } EFI_INSTRUCTION_SET_ARCHITECTURE;
 715
 716
 717 //
 718 // DebugSupport member function definitions
 719 //
 720
 721 /**
 722   Returns the maximum value that may be used for the ProcessorIndex parameter in
 723   RegisterPeriodicCallback() and RegisterExceptionCallback().
 724
 725   @param  This                  A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
 726   @param  MaxProcessorIndex     Pointer to a caller-allocated UINTN in which the maximum supported
 727                                 processor index is returned.
 728
 729   @retval EFI_SUCCESS           The function completed successfully.
 730
 731 **/
 732 typedef
 733 EFI_STATUS
 734 (EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)(
 735   IN EFI_DEBUG_SUPPORT_PROTOCOL          *This,
 736   OUT UINTN                              *MaxProcessorIndex
 737   );
 738
 739 /**
 740   Registers a function to be called back periodically in interrupt context.
 741
 742   @param  This                  A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
 743   @param  ProcessorIndex        Specifies which processor the callback function applies to.
 744   @param  PeriodicCallback      A pointer to a function of type PERIODIC_CALLBACK that is the main
 745                                 periodic entry point of the debug agent.
 746
 747   @retval EFI_SUCCESS           The function completed successfully.
 748   @retval EFI_ALREADY_STARTED   Non-NULL PeriodicCallback parameter when a callback
 749                                 function was previously registered.
 750   @retval EFI_OUT_OF_RESOURCES  System has insufficient memory resources to register new callback
 751                                 function.
 752
 753 **/
 754 typedef
 755 EFI_STATUS
 756 (EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)(
 757   IN EFI_DEBUG_SUPPORT_PROTOCOL          *This,
 758   IN UINTN                               ProcessorIndex,
 759   IN EFI_PERIODIC_CALLBACK               PeriodicCallback
 760   );
 761
 762 /**
 763   Registers a function to be called when a given processor exception occurs.
 764
 765   @param  This                  A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
 766   @param  ProcessorIndex        Specifies which processor the callback function applies to.
 767   @param  ExceptionCallback     A pointer to a function of type EXCEPTION_CALLBACK that is called
 768                                 when the processor exception specified by ExceptionType occurs.
 769   @param  ExceptionType         Specifies which processor exception to hook.
 770
 771   @retval EFI_SUCCESS           The function completed successfully.
 772   @retval EFI_ALREADY_STARTED   Non-NULL PeriodicCallback parameter when a callback
 773                                 function was previously registered.
 774   @retval EFI_OUT_OF_RESOURCES  System has insufficient memory resources to register new callback
 775                                 function.
 776
 777 **/
 778 typedef
 779 EFI_STATUS
 780 (EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)(
 781   IN EFI_DEBUG_SUPPORT_PROTOCOL          *This,
 782   IN UINTN                               ProcessorIndex,
 783   IN EFI_EXCEPTION_CALLBACK              ExceptionCallback,
 784   IN EFI_EXCEPTION_TYPE                  ExceptionType
 785   );
 786
 787 /**
 788   Invalidates processor instruction cache for a memory range. Subsequent execution in this range
 789   causes a fresh memory fetch to retrieve code to be executed.
 790
 791   @param  This                  A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
 792   @param  ProcessorIndex        Specifies which processor's instruction cache is to be invalidated.
 793   @param  Start                 Specifies the physical base of the memory range to be invalidated.
 794   @param  Length                Specifies the minimum number of bytes in the processor's instruction
 795                                 cache to invalidate.
 796
 797   @retval EFI_SUCCESS           The function completed successfully.
 798
 799 **/
 800 typedef
 801 EFI_STATUS
 802 (EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)(
 803   IN EFI_DEBUG_SUPPORT_PROTOCOL          *This,
 804   IN UINTN                               ProcessorIndex,
 805   IN VOID                                *Start,
 806   IN UINT64                              Length
 807   );
 808
 809 ///
 810 /// This protocol provides the services to allow the debug agent to register
 811 /// callback functions that are called either periodically or when specific
 812 /// processor exceptions occur.
 813 ///
 814 struct _EFI_DEBUG_SUPPORT_PROTOCOL {
 815   ///
 816   /// Declares the processor architecture for this instance of the EFI Debug Support protocol.
 817   ///
 818   EFI_INSTRUCTION_SET_ARCHITECTURE  Isa;
 819   EFI_GET_MAXIMUM_PROCESSOR_INDEX   GetMaximumProcessorIndex;
 820   EFI_REGISTER_PERIODIC_CALLBACK    RegisterPeriodicCallback;
 821   EFI_REGISTER_EXCEPTION_CALLBACK   RegisterExceptionCallback;
 822   EFI_INVALIDATE_INSTRUCTION_CACHE  InvalidateInstructionCache;
 823 };
 824
 825 extern EFI_GUID gEfiDebugSupportProtocolGuid;
 826
 827 #endif