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1 /** @file
2 PCI Root Bridge I/O protocol as defined in the UEFI 2.0 specification.
3
4 PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O,
5 and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform
6 defferent types of bus mastering DMA
7
8 Copyright (c) 2006 - 2008, Intel Corporation
9 All rights reserved. This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
13
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17 **/
18
19 #ifndef __PCI_ROOT_BRIDGE_IO_H__
20 #define __PCI_ROOT_BRIDGE_IO_H__
21
22 #define EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \
23 { \
24 0x2f707ebb, 0x4a1a, 0x11d4, {0x9a, 0x38, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
25 }
26
27 typedef struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL;
28
29 ///
30 /// *******************************************************
31 /// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH
32 /// *******************************************************
33 ///
34 typedef enum {
35 EfiPciWidthUint8,
36 EfiPciWidthUint16,
37 EfiPciWidthUint32,
38 EfiPciWidthUint64,
39 EfiPciWidthFifoUint8,
40 EfiPciWidthFifoUint16,
41 EfiPciWidthFifoUint32,
42 EfiPciWidthFifoUint64,
43 EfiPciWidthFillUint8,
44 EfiPciWidthFillUint16,
45 EfiPciWidthFillUint32,
46 EfiPciWidthFillUint64,
47 EfiPciWidthMaximum
48 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH;
49
50 ///
51 /// *******************************************************
52 /// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION
53 /// *******************************************************
54 ///
55 typedef enum {
56 ///
57 /// A read operation from system memory by a bus master that is not capable of producing
58 /// PCI dual address cycles.
59 ///
60 EfiPciOperationBusMasterRead,
61 ///
62 /// A write operation from system memory by a bus master that is not capable of producing
63 /// PCI dual address cycles.
64 ///
65 EfiPciOperationBusMasterWrite,
66 ///
67 /// Provides both read and write access to system memory by both the processor and a bus
68 /// master that is not capable of producing PCI dual address cycles.
69 ///
70 EfiPciOperationBusMasterCommonBuffer,
71 ///
72 /// A read operation from system memory by a bus master that is capable of producing PCI
73 /// dual address cycles.
74 ///
75 EfiPciOperationBusMasterRead64,
76 ///
77 /// A write operation to system memory by a bus master that is capable of producing PCI
78 /// dual address cycles.
79 ///
80 EfiPciOperationBusMasterWrite64,
81 ///
82 /// Provides both read and write access to system memory by both the processor and a bus
83 /// master that is capable of producing PCI dual address cycles.
84 ///
85 EfiPciOperationBusMasterCommonBuffer64,
86 EfiPciOperationMaximum
87 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;
88
89 #define EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001
90 #define EFI_PCI_ATTRIBUTE_ISA_IO 0x0002
91 #define EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO 0x0004
92 #define EFI_PCI_ATTRIBUTE_VGA_MEMORY 0x0008
93 #define EFI_PCI_ATTRIBUTE_VGA_IO 0x0010
94 #define EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO 0x0020
95 #define EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO 0x0040
96 #define EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080
97 #define EFI_PCI_ATTRIBUTE_MEMORY_CACHED 0x0800
98 #define EFI_PCI_ATTRIBUTE_MEMORY_DISABLE 0x1000
99 #define EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000
100
101 #define EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER (EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED | EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE)
102
103 #define EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER (~EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER)
104
105 #define EFI_PCI_ADDRESS(bus, dev, func, reg) \
106 ((UINT64) ((((UINTN) bus) << 24) + (((UINTN) dev) << 16) + (((UINTN) func) << 8) + ((UINTN) reg)))
107
108 typedef struct {
109 UINT8 Register;
110 UINT8 Function;
111 UINT8 Device;
112 UINT8 Bus;
113 UINT32 ExtendedRegister;
114 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS;
115
116 /**
117 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
118 satisfied or after a defined duration.
119
120 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
121 @param Width Signifies the width of the memory or I/O operations.
122 @param Address The base address of the memory or I/O operations.
123 @param Mask Mask used for the polling criteria.
124 @param Value The comparison value used for the polling exit criteria.
125 @param Delay The number of 100 ns units to poll.
126 @param Result Pointer to the last value read from the memory location.
127
128 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
129 @retval EFI_TIMEOUT Delay expired before a match occurred.
130 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
131 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
132
133 **/
134 typedef
135 EFI_STATUS
136 (EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM)(
137 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
138 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
139 IN UINT64 Address,
140 IN UINT64 Mask,
141 IN UINT64 Value,
142 IN UINT64 Delay,
143 OUT UINT64 *Result
144 );
145
146 /**
147 Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
148
149 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
150 @param Width Signifies the width of the memory operations.
151 @param Address The base address of the memory operations.
152 @param Count The number of memory operations to perform.
153 @param Buffer For read operations, the destination buffer to store the results. For write
154 operations, the source buffer to write data from.
155
156 @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
157 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
158 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
159
160 **/
161 typedef
162 EFI_STATUS
163 (EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM)(
164 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
165 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
166 IN UINT64 Address,
167 IN UINTN Count,
168 IN OUT VOID *Buffer
169 );
170
171 typedef struct {
172 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Read;
173 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM Write;
174 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;
175
176 /**
177 Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
178 root bridge memory space.
179
180 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
181 @param Width Signifies the width of the memory operations.
182 @param DestAddress The destination address of the memory operation.
183 @param SrcAddress The source address of the memory operation.
184 @param Count The number of memory operations to perform.
185
186 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
187 @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
188 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
189
190 **/
191 typedef
192 EFI_STATUS
193 (EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM)(
194 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
195 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
196 IN UINT64 DestAddress,
197 IN UINT64 SrcAddress,
198 IN UINTN Count
199 );
200
201 /**
202 Provides the PCI controller-Cspecific addresses required to access system memory from a
203 DMA bus master.
204
205 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
206 @param Operation Indicates if the bus master is going to read or write to system memory.
207 @param HostAddress The system memory address to map to the PCI controller.
208 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
209 that were mapped.
210 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
211 access the hosts HostAddress.
212 @param Mapping A resulting value to pass to Unmap().
213
214 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
215 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
216 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
217 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
218 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
219
220 **/
221 typedef
222 EFI_STATUS
223 (EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP)(
224 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
225 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
226 IN VOID *HostAddress,
227 IN OUT UINTN *NumberOfBytes,
228 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
229 OUT VOID **Mapping
230 );
231
232 /**
233 Completes the Map() operation and releases any corresponding resources.
234
235 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
236 @param Mapping The mapping value returned from Map().
237
238 @retval EFI_SUCCESS The range was unmapped.
239 @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
240 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
241
242 **/
243 typedef
244 EFI_STATUS
245 (EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP)(
246 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
247 IN VOID *Mapping
248 );
249
250 /**
251 Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
252 EfiPciOperationBusMasterCommonBuffer64 mapping.
253
254 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
255 @param Type This parameter is not used and must be ignored.
256 @param MemoryType The type of memory to allocate, EfiBootServicesData or
257 EfiRuntimeServicesData.
258 @param Pages The number of pages to allocate.
259 @param HostAddress A pointer to store the base system memory address of the
260 allocated range.
261 @param Attributes The requested bit mask of attributes for the allocated range.
262
263 @retval EFI_SUCCESS The requested memory pages were allocated.
264 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
265 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
266 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
267 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
268
269 **/
270 typedef
271 EFI_STATUS
272 (EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER)(
273 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
274 IN EFI_ALLOCATE_TYPE Type,
275 IN EFI_MEMORY_TYPE MemoryType,
276 IN UINTN Pages,
277 IN OUT VOID **HostAddress,
278 IN UINT64 Attributes
279 );
280
281 /**
282 Frees memory that was allocated with AllocateBuffer().
283
284 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
285 @param Pages The number of pages to free.
286 @param HostAddress The base system memory address of the allocated range.
287
288 @retval EFI_SUCCESS The requested memory pages were freed.
289 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
290 was not allocated with AllocateBuffer().
291
292 **/
293 typedef
294 EFI_STATUS
295 (EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER)(
296 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
297 IN UINTN Pages,
298 IN VOID *HostAddress
299 );
300
301 /**
302 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
303
304 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
305
306 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
307 bridge to system memory.
308 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
309 host bridge due to a hardware error.
310
311 **/
312 typedef
313 EFI_STATUS
314 (EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH)(
315 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
316 );
317
318 /**
319 Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
320 attributes that a PCI root bridge is currently using.
321
322 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
323 @param Supports A pointer to the mask of attributes that this PCI root bridge supports
324 setting with SetAttributes().
325 @param Attributes A pointer to the mask of attributes that this PCI root bridge is currently
326 using.
327
328 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
329 bridge supports is returned in Supports. If Attributes is
330 not NULL, then the attributes that the PCI root bridge is currently
331 using is returned in Attributes.
332 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
333
334
335 **/
336 typedef
337 EFI_STATUS
338 (EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES)(
339 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
340 OUT UINT64 *Supports,
341 OUT UINT64 *Attributes
342 );
343
344 /**
345 Sets attributes for a resource range on a PCI root bridge.
346
347 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
348 @param Attributes The mask of attributes to set.
349 @param ResourceBase A pointer to the base address of the resource range to be modified by the
350 attributes specified by Attributes.
351 @param ResourceLength A pointer to the length of the resource range to be modified by the
352 attributes specified by Attributes.
353
354 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource
355 range specified by ResourceBase and ResourceLength
356 were set on the PCI root bridge, and the actual resource range is
357 returned in ResuourceBase and ResourceLength.
358 @retval EFI_UNSUPPORTED A bit is set in Attributes that is not supported by the PCI Root
359 Bridge.
360 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the
361 resource range specified by BaseAddress and Length.
362 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
363
364 **/
365 typedef
366 EFI_STATUS
367 (EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES)(
368 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
369 IN UINT64 Attributes,
370 IN OUT UINT64 *ResourceBase,
371 IN OUT UINT64 *ResourceLength
372 );
373
374 /**
375 Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
376 resource descriptors.
377
378 @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
379 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current
380 configuration of this PCI root bridge.
381
382 @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in
383 Resources.
384 @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be
385 retrieved.
386
387 **/
388 typedef
389 EFI_STATUS
390 (EFIAPI *EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION)(
391 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
392 OUT VOID **Resources
393 );
394
395 ///
396 /// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are
397 /// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller.
398 ///
399 struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {
400 ///
401 /// The EFI_HANDLE of the PCI Host Bridge of which this PCI Root Bridge is a member.
402 ///
403 EFI_HANDLE ParentHandle;
404 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollMem;
405 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_POLL_IO_MEM PollIo;
406 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Mem;
407 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Io;
408 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS Pci;
409 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_COPY_MEM CopyMem;
410 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_MAP Map;
411 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_UNMAP Unmap;
412 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer;
413 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FREE_BUFFER FreeBuffer;
414 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_FLUSH Flush;
415 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES GetAttributes;
416 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES SetAttributes;
417 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION Configuration;
418
419 ///
420 /// The segment number that this PCI root bridge resides.
421 ///
422 UINT32 SegmentNumber;
423 };
424
425 extern EFI_GUID gEfiPciRootBridgeIoProtocolGuid;
426
427 #endif