MdePkg/Include/Register/Amd/Fam17Msr.h

   1 /** @file
   2   MSR Definitions.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
  14
  15 **/
  16
  17 #ifndef __FAM17_MSR_H__
  18 #define __FAM17_MSR_H__
  19
  20 /**
  21   Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register
  22
  23 **/
  24 #define MSR_SEV_ES_GHCB  0xc0010130
  25
  26 /**
  27   MSR information returned for #MSR_SEV_ES_GHCB
  28 **/
  29 typedef union {
  30   struct {
  31     UINT32    Function  : 12;
  32     UINT32    Reserved1 : 20;
  33     UINT32    Reserved2 : 32;
  34   } GhcbInfo;
  35
  36   struct {
  37     UINT8     Reserved[3];
  38     UINT8     SevEncryptionBitPos;
  39     UINT16    SevEsProtocolMin;
  40     UINT16    SevEsProtocolMax;
  41   } GhcbProtocol;
  42
  43   struct {
  44     UINT32    Function      : 12;
  45     UINT32    ReasonCodeSet : 4;
  46     UINT32    ReasonCode    : 8;
  47     UINT32    Reserved1     : 8;
  48     UINT32    Reserved2     : 32;
  49   } GhcbTerminate;
  50
  51   struct {
  52     UINT64    Function : 12;
  53     UINT64    Features : 52;
  54   } GhcbHypervisorFeatures;
  55
  56   struct {
  57     UINT64    Function         : 12;
  58     UINT64    GuestFrameNumber : 52;
  59   } GhcbGpaRegister;
  60
  61   struct {
  62     UINT64    Function         : 12;
  63     UINT64    GuestFrameNumber : 40;
  64     UINT64    Operation        : 4;
  65     UINT64    Reserved         : 8;
  66   } SnpPageStateChangeRequest;
  67
  68   struct {
  69     UINT32    Function : 12;
  70     UINT32    Reserved : 20;
  71     UINT32    ErrorCode;
  72   } SnpPageStateChangeResponse;
  73
  74   VOID      *Ghcb;
  75
  76   UINT64    GhcbPhysicalAddress;
  77 } MSR_SEV_ES_GHCB_REGISTER;
  78
  79 #define GHCB_INFO_SEV_INFO                        1
  80 #define GHCB_INFO_SEV_INFO_GET                    2
  81 #define GHCB_INFO_CPUID_REQUEST                   4
  82 #define GHCB_INFO_CPUID_RESPONSE                  5
  83 #define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST       18
  84 #define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE      19
  85 #define GHCB_INFO_SNP_PAGE_STATE_CHANGE_REQUEST   20
  86 #define GHCB_INFO_SNP_PAGE_STATE_CHANGE_RESPONSE  21
  87 #define GHCB_HYPERVISOR_FEATURES_REQUEST          128
  88 #define GHCB_HYPERVISOR_FEATURES_RESPONSE         129
  89 #define GHCB_INFO_TERMINATE_REQUEST               256
  90
  91 #define GHCB_TERMINATE_GHCB           0
  92 #define GHCB_TERMINATE_GHCB_GENERAL   0
  93 #define GHCB_TERMINATE_GHCB_PROTOCOL  1
  94
  95 /**
  96   Secure Encrypted Virtualization (SEV) status register
  97
  98 **/
  99 #define MSR_SEV_STATUS  0xc0010131
 100
 101 /**
 102   MSR information returned for #MSR_SEV_STATUS
 103 **/
 104 typedef union {
 105   ///
 106   /// Individual bit fields
 107   ///
 108   struct {
 109     ///
 110     /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled
 111     ///
 112     UINT32    SevBit    : 1;
 113
 114     ///
 115     /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled
 116     ///
 117     UINT32    SevEsBit  : 1;
 118
 119     ///
 120     /// [Bit 2] Secure Nested Paging (SevSnp) is enabled
 121     ///
 122     UINT32    SevSnpBit : 1;
 123
 124     UINT32    Reserved2 : 29;
 125   } Bits;
 126   ///
 127   /// All bit fields as a 32-bit value
 128   ///
 129   UINT32    Uint32;
 130   ///
 131   /// All bit fields as a 64-bit value
 132   ///
 133   UINT64    Uint64;
 134 } MSR_SEV_STATUS_REGISTER;
 135
 136 #endif