2 Intel Architectural MSR Definitions.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __INTEL_ARCHITECTURAL_MSR_H__
19 #define __INTEL_ARCHITECTURAL_MSR_H__
22 See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
24 @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
25 @param EAX Lower 32-bits of MSR value.
26 @param EDX Upper 32-bits of MSR value.
32 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
33 AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
35 @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
37 #define MSR_IA32_P5_MC_ADDR 0x00000000
40 See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
42 @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
43 @param EAX Lower 32-bits of MSR value.
44 @param EDX Upper 32-bits of MSR value.
50 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
51 AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
53 @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
55 #define MSR_IA32_P5_MC_TYPE 0x00000001
58 See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
59 at Display Family / Display Model 0F_03H.
61 @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)
62 @param EAX Lower 32-bits of MSR value.
63 @param EDX Upper 32-bits of MSR value.
69 Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
70 AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
72 @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.
74 #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
77 See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
80 @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
81 @param EAX Lower 32-bits of MSR value.
82 @param EDX Upper 32-bits of MSR value.
88 Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
89 AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
91 @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.
93 #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
96 Platform ID (RO) The operating system can use this MSR to determine "slot"
97 information for the processor and the proper microcode update to load.
98 Introduced at Display Family / Display Model 06_01H.
100 @param ECX MSR_IA32_PLATFORM_ID (0x00000017)
101 @param EAX Lower 32-bits of MSR value.
102 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
103 @param EDX Upper 32-bits of MSR value.
104 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
108 MSR_IA32_PLATFORM_ID_REGISTER Msr;
110 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
112 @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
114 #define MSR_IA32_PLATFORM_ID 0x00000017
117 MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
121 /// Individual bit fields
124 UINT32 Reserved1
: 32;
125 UINT32 Reserved2
: 18;
127 /// [Bits 52:50] Platform Id (RO) Contains information concerning the
128 /// intended platform for the processor.
131 /// 0 0 0 Processor Flag 0.
132 /// 0 0 1 Processor Flag 1
133 /// 0 1 0 Processor Flag 2
134 /// 0 1 1 Processor Flag 3
135 /// 1 0 0 Processor Flag 4
136 /// 1 0 1 Processor Flag 5
137 /// 1 1 0 Processor Flag 6
138 /// 1 1 1 Processor Flag 7
140 UINT32 PlatformId
: 3;
141 UINT32 Reserved3
: 11;
144 /// All bit fields as a 64-bit value
147 } MSR_IA32_PLATFORM_ID_REGISTER
;
152 @param ECX MSR_IA32_APIC_BASE (0x0000001B)
153 @param EAX Lower 32-bits of MSR value.
154 Described by the type MSR_IA32_APIC_BASE_REGISTER.
155 @param EDX Upper 32-bits of MSR value.
156 Described by the type MSR_IA32_APIC_BASE_REGISTER.
160 MSR_IA32_APIC_BASE_REGISTER Msr;
162 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
163 AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
165 @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
167 #define MSR_IA32_APIC_BASE 0x0000001B
170 MSR information returned for MSR index #MSR_IA32_APIC_BASE
174 /// Individual bit fields
177 UINT32 Reserved1
: 8;
179 /// [Bit 8] BSP flag (R/W).
182 UINT32 Reserved2
: 1;
184 /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
189 /// [Bit 11] APIC Global Enable (R/W).
193 /// [Bits 31:12] APIC Base (R/W).
195 UINT32 ApicBase
: 20;
197 /// [Bits 63:32] APIC Base (R/W).
199 UINT32 ApicBaseHi
: 32;
202 /// All bit fields as a 64-bit value
205 } MSR_IA32_APIC_BASE_REGISTER
;
208 Control Features in Intel 64 Processor (R/W). If any one enumeration
209 condition for defined bit field holds.
211 @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)
212 @param EAX Lower 32-bits of MSR value.
213 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
214 @param EDX Upper 32-bits of MSR value.
215 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
219 MSR_IA32_FEATURE_CONTROL_REGISTER Msr;
221 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
222 AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
224 @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
226 #define MSR_IA32_FEATURE_CONTROL 0x0000003A
229 MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
233 /// Individual bit fields
237 /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from
238 /// being written, writes to this bit will result in GP(0). Note: Once the
239 /// Lock bit is set, the contents of this register cannot be modified.
240 /// Therefore the lock bit must be set after configuring support for Intel
241 /// Virtualization Technology and prior to transferring control to an
242 /// option ROM or the OS. Hence, once the Lock bit is set, the entire
243 /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD
244 /// is not deasserted. If any one enumeration condition for defined bit
245 /// field position greater than bit 0 holds.
249 /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
250 /// system executive to use VMX in conjunction with SMX to support
251 /// Intel(R) Trusted Execution Technology. BIOS must set this bit only
252 /// when the CPUID function 1 returns VMX feature flag and SMX feature
253 /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
254 /// CPUID.01H:ECX[6] = 1.
256 UINT32 EnableVmxInsideSmx
: 1;
258 /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
259 /// for system executive that do not require SMX. BIOS must set this bit
260 /// only when the CPUID function 1 returns VMX feature flag set (ECX bit
261 /// 5). If CPUID.01H:ECX[5] = 1.
263 UINT32 EnableVmxOutsideSmx
: 1;
264 UINT32 Reserved1
: 5;
266 /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
267 /// in the field represents an enable control for a corresponding SENTER
268 /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
269 /// CPUID.01H:ECX[6] = 1.
271 UINT32 SenterLocalFunctionEnables
: 7;
273 /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
274 /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
275 /// 6] is set. If CPUID.01H:ECX[6] = 1.
277 UINT32 SenterGlobalEnable
: 1;
278 UINT32 Reserved2
: 1;
280 /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to
281 /// enable runtime reconfiguration of SGX Launch Control via
282 /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
284 UINT32 SgxLaunchControlEnable
: 1;
286 /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
287 /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
289 UINT32 SgxEnable
: 1;
290 UINT32 Reserved3
: 1;
292 /// [Bit 20] LMCE On (R/WL): When set, system software can program the
293 /// MSRs associated with LMCE to configure delivery of some machine check
294 /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
297 UINT32 Reserved4
: 11;
298 UINT32 Reserved5
: 32;
301 /// All bit fields as a 32-bit value
305 /// All bit fields as a 64-bit value
308 } MSR_IA32_FEATURE_CONTROL_REGISTER
;
311 Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
312 ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for
313 a logical processor. Reset value is Zero. A write to IA32_TSC will modify
314 the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does
315 not affect the internal invariant TSC hardware.
317 @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)
318 @param EAX Lower 32-bits of MSR value.
319 @param EDX Upper 32-bits of MSR value.
325 Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
326 AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
328 @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
330 #define MSR_IA32_TSC_ADJUST 0x0000003B
333 BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
334 microcode update to be loaded into the processor. See Section 9.11.6,
335 "Microcode Update Loader." A processor may prevent writing to this MSR when
336 loading guest states on VM entries or saving guest states on VM exits.
337 Introduced at Display Family / Display Model 06_01H.
339 @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)
340 @param EAX Lower 32-bits of MSR value.
341 @param EDX Upper 32-bits of MSR value.
348 AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
350 @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
352 #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
355 BIOS Update Signature (RO) Returns the microcode update signature following
356 the execution of CPUID.01H. A processor may prevent writing to this MSR when
357 loading guest states on VM entries or saving guest states on VM exits.
358 Introduced at Display Family / Display Model 06_01H.
360 @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)
361 @param EAX Lower 32-bits of MSR value.
362 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
363 @param EDX Upper 32-bits of MSR value.
364 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
368 MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;
370 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
372 @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
374 #define MSR_IA32_BIOS_SIGN_ID 0x0000008B
377 MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
381 /// Individual bit fields
384 UINT32 Reserved
: 32;
386 /// [Bits 63:32] Microcode update signature. This field contains the
387 /// signature of the currently loaded microcode update when read following
388 /// the execution of the CPUID instruction, function 1. It is required
389 /// that this register field be pre-loaded with zero prior to executing
390 /// the CPUID, function 1. If the field remains equal to zero, then there
391 /// is no microcode update loaded. Another nonzero value will be the
394 UINT32 MicrocodeUpdateSignature
: 32;
397 /// All bit fields as a 64-bit value
400 } MSR_IA32_BIOS_SIGN_ID_REGISTER
;
403 IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the
404 SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the
405 default value is the digest of Intel's signing key. Read permitted If
406 CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):
407 EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.
409 @param ECX MSR_IA32_SGXLEPUBKEYHASHn
410 @param EAX Lower 32-bits of MSR value.
411 @param EDX Upper 32-bits of MSR value.
417 Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);
418 AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);
420 @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.
421 MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.
422 MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.
423 MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.
426 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
427 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
428 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
429 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
433 SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =
436 @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
437 @param EAX Lower 32-bits of MSR value.
438 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
439 @param EDX Upper 32-bits of MSR value.
440 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
444 MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;
446 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
447 AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
449 @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
451 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
454 MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
458 /// Individual bit fields
462 /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this
463 /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment
464 /// (see Section 34.15.6), the dual-monitor treatment cannot be activated
465 /// if the bit is 0. This bit is cleared when the logical processor is
469 UINT32 Reserved1
: 1;
471 /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
472 /// IA32_VMX_MISC[28].
475 UINT32 Reserved2
: 9;
477 /// [Bits 31:12] MSEG Base (R/W).
479 UINT32 MsegBase
: 20;
480 UINT32 Reserved3
: 32;
483 /// All bit fields as a 32-bit value
487 /// All bit fields as a 64-bit value
490 } MSR_IA32_SMM_MONITOR_CTL_REGISTER
;
493 MSEG header that is located at the physical address specified by the MsegBase
494 field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
498 /// Different processors may use different MSEG revision identifiers. These
499 /// identifiers enable software to avoid using an MSEG header formatted for
500 /// one processor on a processor that uses a different format. Software can
501 /// discover the MSEG revision identifier that a processor uses by reading
502 /// the VMX capability MSR IA32_VMX_MISC.
504 UINT32 MsegHeaderRevision
;
506 /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field
507 /// is the IA-32e mode SMM feature bit. It indicates whether the logical
508 /// processor will be in IA-32e mode after the STM is activated.
510 UINT32 MonitorFeatures
;
512 UINT32 GdtrBaseOffset
;
518 /// Pad header so total size is 2KB
520 UINT8 Reserved
[SIZE_2KB
- 8 * sizeof (UINT32
)];
524 /// @{ Define values for the MonitorFeatures field of #MSEG_HEADER
526 #define STM_FEATURES_IA32E 0x1
532 Base address of the logical processor's SMRAM image (RO, SMM only). If
535 @param ECX MSR_IA32_SMBASE (0x0000009E)
536 @param EAX Lower 32-bits of MSR value.
537 @param EDX Upper 32-bits of MSR value.
543 Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
545 @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
547 #define MSR_IA32_SMBASE 0x0000009E
550 General Performance Counters (R/W).
551 MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.
553 @param ECX MSR_IA32_PMCn
554 @param EAX Lower 32-bits of MSR value.
555 @param EDX Upper 32-bits of MSR value.
561 Msr = AsmReadMsr64 (MSR_IA32_PMC0);
562 AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
564 @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.
565 MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.
566 MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.
567 MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.
568 MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.
569 MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.
570 MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.
571 MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
574 #define MSR_IA32_PMC0 0x000000C1
575 #define MSR_IA32_PMC1 0x000000C2
576 #define MSR_IA32_PMC2 0x000000C3
577 #define MSR_IA32_PMC3 0x000000C4
578 #define MSR_IA32_PMC4 0x000000C5
579 #define MSR_IA32_PMC5 0x000000C6
580 #define MSR_IA32_PMC6 0x000000C7
581 #define MSR_IA32_PMC7 0x000000C8
585 TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
586 C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
587 to TSC freq.) when the logical processor is in C0. Cleared upon overflow /
588 wrap-around of IA32_APERF.
590 @param ECX MSR_IA32_MPERF (0x000000E7)
591 @param EAX Lower 32-bits of MSR value.
592 @param EDX Upper 32-bits of MSR value.
598 Msr = AsmReadMsr64 (MSR_IA32_MPERF);
599 AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
601 @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
603 #define MSR_IA32_MPERF 0x000000E7
606 Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
607 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at
608 the coordinated clock frequency, when the logical processor is in C0.
609 Cleared upon overflow / wrap-around of IA32_MPERF.
611 @param ECX MSR_IA32_APERF (0x000000E8)
612 @param EAX Lower 32-bits of MSR value.
613 @param EDX Upper 32-bits of MSR value.
619 Msr = AsmReadMsr64 (MSR_IA32_APERF);
620 AsmWriteMsr64 (MSR_IA32_APERF, Msr);
622 @note MSR_IA32_APERF is defined as IA32_APERF in SDM.
624 #define MSR_IA32_APERF 0x000000E8
627 MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
628 Introduced at Display Family / Display Model 06_01H.
630 @param ECX MSR_IA32_MTRRCAP (0x000000FE)
631 @param EAX Lower 32-bits of MSR value.
632 Described by the type MSR_IA32_MTRRCAP_REGISTER.
633 @param EDX Upper 32-bits of MSR value.
634 Described by the type MSR_IA32_MTRRCAP_REGISTER.
638 MSR_IA32_MTRRCAP_REGISTER Msr;
640 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
642 @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.
644 #define MSR_IA32_MTRRCAP 0x000000FE
647 MSR information returned for MSR index #MSR_IA32_MTRRCAP
651 /// Individual bit fields
655 /// [Bits 7:0] VCNT: The number of variable memory type ranges in the
660 /// [Bit 8] Fixed range MTRRs are supported when set.
663 UINT32 Reserved1
: 1;
665 /// [Bit 10] WC Supported when set.
669 /// [Bit 11] SMRR Supported when set.
672 UINT32 Reserved2
: 20;
673 UINT32 Reserved3
: 32;
676 /// All bit fields as a 32-bit value
680 /// All bit fields as a 64-bit value
683 } MSR_IA32_MTRRCAP_REGISTER
;
686 SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
688 @param ECX MSR_IA32_SYSENTER_CS (0x00000174)
689 @param EAX Lower 32-bits of MSR value.
690 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
691 @param EDX Upper 32-bits of MSR value.
692 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
696 MSR_IA32_SYSENTER_CS_REGISTER Msr;
698 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
699 AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);
701 @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.
703 #define MSR_IA32_SYSENTER_CS 0x00000174
706 MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
710 /// Individual bit fields
714 /// [Bits 15:0] CS Selector.
717 UINT32 Reserved1
: 16;
718 UINT32 Reserved2
: 32;
721 /// All bit fields as a 32-bit value
725 /// All bit fields as a 64-bit value
728 } MSR_IA32_SYSENTER_CS_REGISTER
;
731 SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
733 @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)
734 @param EAX Lower 32-bits of MSR value.
735 @param EDX Upper 32-bits of MSR value.
741 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
742 AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
744 @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.
746 #define MSR_IA32_SYSENTER_ESP 0x00000175
749 SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
751 @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)
752 @param EAX Lower 32-bits of MSR value.
753 @param EDX Upper 32-bits of MSR value.
759 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
760 AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
762 @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.
764 #define MSR_IA32_SYSENTER_EIP 0x00000176
767 Global Machine Check Capability (RO). Introduced at Display Family / Display
770 @param ECX MSR_IA32_MCG_CAP (0x00000179)
771 @param EAX Lower 32-bits of MSR value.
772 Described by the type MSR_IA32_MCG_CAP_REGISTER.
773 @param EDX Upper 32-bits of MSR value.
774 Described by the type MSR_IA32_MCG_CAP_REGISTER.
778 MSR_IA32_MCG_CAP_REGISTER Msr;
780 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
782 @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
784 #define MSR_IA32_MCG_CAP 0x00000179
787 MSR information returned for MSR index #MSR_IA32_MCG_CAP
791 /// Individual bit fields
795 /// [Bits 7:0] Count: Number of reporting banks.
799 /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
801 UINT32 MCG_CTL_P
: 1;
803 /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
804 /// if this bit is set.
806 UINT32 MCG_EXT_P
: 1;
808 /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
809 /// Introduced at Display Family / Display Model 06_01H.
811 UINT32 MCP_CMCI_P
: 1;
813 /// [Bit 11] MCG_TES_P: Threshold-based error status register are present
814 /// if this bit is set.
816 UINT32 MCG_TES_P
: 1;
817 UINT32 Reserved1
: 4;
819 /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
820 /// registers present.
822 UINT32 MCG_EXT_CNT
: 8;
824 /// [Bit 24] MCG_SER_P: The processor supports software error recovery if
827 UINT32 MCG_SER_P
: 1;
828 UINT32 Reserved2
: 1;
830 /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
831 /// firmware to be invoked when an error is detected so that it may
832 /// provide additional platform specific information in an ACPI format
833 /// "Generic Error Data Entry" that augments the data included in machine
834 /// check bank registers. Introduced at Display Family / Display Model
837 UINT32 MCG_ELOG_P
: 1;
839 /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
840 /// state in IA32_MCG_STATUS and associated MSR necessary to configure
841 /// Local Machine Check Exception (LMCE). Introduced at Display Family /
842 /// Display Model 06_3EH.
844 UINT32 MCG_LMCE_P
: 1;
845 UINT32 Reserved3
: 4;
846 UINT32 Reserved4
: 32;
849 /// All bit fields as a 32-bit value
853 /// All bit fields as a 64-bit value
856 } MSR_IA32_MCG_CAP_REGISTER
;
859 Global Machine Check Status (R/W0). Introduced at Display Family / Display
862 @param ECX MSR_IA32_MCG_STATUS (0x0000017A)
863 @param EAX Lower 32-bits of MSR value.
864 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
865 @param EDX Upper 32-bits of MSR value.
866 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
870 MSR_IA32_MCG_STATUS_REGISTER Msr;
872 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
873 AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);
875 @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.
877 #define MSR_IA32_MCG_STATUS 0x0000017A
880 MSR information returned for MSR index #MSR_IA32_MCG_STATUS
884 /// Individual bit fields
888 /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
893 /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
898 /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
899 /// / Display Model 06_01H.
903 /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
906 UINT32 Reserved1
: 28;
907 UINT32 Reserved2
: 32;
910 /// All bit fields as a 32-bit value
914 /// All bit fields as a 64-bit value
917 } MSR_IA32_MCG_STATUS_REGISTER
;
920 Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
922 @param ECX MSR_IA32_MCG_CTL (0x0000017B)
923 @param EAX Lower 32-bits of MSR value.
924 @param EDX Upper 32-bits of MSR value.
930 Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
931 AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);
933 @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.
935 #define MSR_IA32_MCG_CTL 0x0000017B
938 Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
940 @param ECX MSR_IA32_PERFEVTSELn
941 @param EAX Lower 32-bits of MSR value.
942 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
943 @param EDX Upper 32-bits of MSR value.
944 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
948 MSR_IA32_PERFEVTSEL_REGISTER Msr;
950 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
951 AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);
953 @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
954 MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
955 MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
956 MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
959 #define MSR_IA32_PERFEVTSEL0 0x00000186
960 #define MSR_IA32_PERFEVTSEL1 0x00000187
961 #define MSR_IA32_PERFEVTSEL2 0x00000188
962 #define MSR_IA32_PERFEVTSEL3 0x00000189
966 MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to
967 #MSR_IA32_PERFEVTSEL3
971 /// Individual bit fields
975 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
977 UINT32 EventSelect
: 8;
979 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
980 /// detect on the selected event logic.
984 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
988 /// [Bit 17] OS: Counts while in privilege level is ring 0.
992 /// [Bit 18] Edge: Enables edge detection if set.
996 /// [Bit 19] PC: enables pin control.
1000 /// [Bit 20] INT: enables interrupt on counter overflow.
1004 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
1005 /// event conditions occurring across all logical processors sharing a
1006 /// processor core. When set to 0, the counter only increments the
1007 /// associated event conditions occurring in the logical processor which
1008 /// programmed the MSR.
1012 /// [Bit 22] EN: enables the corresponding performance counter to commence
1013 /// counting when this bit is set.
1017 /// [Bit 23] INV: invert the CMASK.
1021 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
1022 /// performance counter increments each cycle if the event count is
1023 /// greater than or equal to the CMASK.
1026 UINT32 Reserved
: 32;
1029 /// All bit fields as a 32-bit value
1033 /// All bit fields as a 64-bit value
1036 } MSR_IA32_PERFEVTSEL_REGISTER
;
1039 Current performance state(P-State) operating point (RO). Introduced at
1040 Display Family / Display Model 0F_03H.
1042 @param ECX MSR_IA32_PERF_STATUS (0x00000198)
1043 @param EAX Lower 32-bits of MSR value.
1044 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
1045 @param EDX Upper 32-bits of MSR value.
1046 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
1048 <b>Example usage</b>
1050 MSR_IA32_PERF_STATUS_REGISTER Msr;
1052 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);
1054 @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.
1056 #define MSR_IA32_PERF_STATUS 0x00000198
1059 MSR information returned for MSR index #MSR_IA32_PERF_STATUS
1063 /// Individual bit fields
1067 /// [Bits 15:0] Current performance State Value.
1070 UINT32 Reserved1
: 16;
1071 UINT32 Reserved2
: 32;
1074 /// All bit fields as a 32-bit value
1078 /// All bit fields as a 64-bit value
1081 } MSR_IA32_PERF_STATUS_REGISTER
;
1084 (R/W). Introduced at Display Family / Display Model 0F_03H.
1086 @param ECX MSR_IA32_PERF_CTL (0x00000199)
1087 @param EAX Lower 32-bits of MSR value.
1088 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1089 @param EDX Upper 32-bits of MSR value.
1090 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1092 <b>Example usage</b>
1094 MSR_IA32_PERF_CTL_REGISTER Msr;
1096 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);
1097 AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);
1099 @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.
1101 #define MSR_IA32_PERF_CTL 0x00000199
1104 MSR information returned for MSR index #MSR_IA32_PERF_CTL
1108 /// Individual bit fields
1112 /// [Bits 15:0] Target performance State Value.
1114 UINT32 TargetState
: 16;
1115 UINT32 Reserved1
: 16;
1117 /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH
1121 UINT32 Reserved2
: 31;
1124 /// All bit fields as a 64-bit value
1127 } MSR_IA32_PERF_CTL_REGISTER
;
1130 Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
1131 Clock Modulation.". If CPUID.01H:EDX[22] = 1.
1133 @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)
1134 @param EAX Lower 32-bits of MSR value.
1135 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1136 @param EDX Upper 32-bits of MSR value.
1137 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1139 <b>Example usage</b>
1141 MSR_IA32_CLOCK_MODULATION_REGISTER Msr;
1143 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
1144 AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);
1146 @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
1148 #define MSR_IA32_CLOCK_MODULATION 0x0000019A
1151 MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION
1155 /// Individual bit fields
1159 /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If
1160 /// CPUID.06H:EAX[5] = 1.
1162 UINT32 ExtendedOnDemandClockModulationDutyCycle
: 1;
1164 /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
1165 /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.
1167 UINT32 OnDemandClockModulationDutyCycle
: 3;
1169 /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
1170 /// If CPUID.01H:EDX[22] = 1.
1172 UINT32 OnDemandClockModulationEnable
: 1;
1173 UINT32 Reserved1
: 27;
1174 UINT32 Reserved2
: 32;
1177 /// All bit fields as a 32-bit value
1181 /// All bit fields as a 64-bit value
1184 } MSR_IA32_CLOCK_MODULATION_REGISTER
;
1187 Thermal Interrupt Control (R/W) Enables and disables the generation of an
1188 interrupt on temperature transitions detected with the processor's thermal
1189 sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".
1190 If CPUID.01H:EDX[22] = 1
1192 @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)
1193 @param EAX Lower 32-bits of MSR value.
1194 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1195 @param EDX Upper 32-bits of MSR value.
1196 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1198 <b>Example usage</b>
1200 MSR_IA32_THERM_INTERRUPT_REGISTER Msr;
1202 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);
1203 AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);
1205 @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.
1207 #define MSR_IA32_THERM_INTERRUPT 0x0000019B
1210 MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT
1214 /// Individual bit fields
1218 /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1220 UINT32 HighTempEnable
: 1;
1222 /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1224 UINT32 LowTempEnable
: 1;
1226 /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1228 UINT32 PROCHOT_Enable
: 1;
1230 /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1232 UINT32 FORCEPR_Enable
: 1;
1234 /// [Bit 4] Critical Temperature Interrupt Enable.
1235 /// If CPUID.01H:EDX[22] = 1.
1237 UINT32 CriticalTempEnable
: 1;
1238 UINT32 Reserved1
: 3;
1240 /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.
1242 UINT32 Threshold1
: 7;
1244 /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1246 UINT32 Threshold1Enable
: 1;
1248 /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.
1250 UINT32 Threshold2
: 7;
1252 /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1254 UINT32 Threshold2Enable
: 1;
1256 /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.
1258 UINT32 PowerLimitNotificationEnable
: 1;
1259 UINT32 Reserved2
: 7;
1260 UINT32 Reserved3
: 32;
1263 /// All bit fields as a 32-bit value
1267 /// All bit fields as a 64-bit value
1270 } MSR_IA32_THERM_INTERRUPT_REGISTER
;
1273 Thermal Status Information (RO) Contains status information about the
1274 processor's thermal sensor and automatic thermal monitoring facilities. See
1275 Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.
1277 @param ECX MSR_IA32_THERM_STATUS (0x0000019C)
1278 @param EAX Lower 32-bits of MSR value.
1279 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1280 @param EDX Upper 32-bits of MSR value.
1281 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1283 <b>Example usage</b>
1285 MSR_IA32_THERM_STATUS_REGISTER Msr;
1287 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);
1289 @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.
1291 #define MSR_IA32_THERM_STATUS 0x0000019C
1294 MSR information returned for MSR index #MSR_IA32_THERM_STATUS
1298 /// Individual bit fields
1302 /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.
1304 UINT32 ThermalStatus
: 1;
1306 /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.
1308 UINT32 ThermalStatusLog
: 1;
1310 /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.
1312 UINT32 PROCHOT_FORCEPR_Event
: 1;
1314 /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.
1316 UINT32 PROCHOT_FORCEPR_Log
: 1;
1318 /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.
1320 UINT32 CriticalTempStatus
: 1;
1322 /// [Bit 5] Critical Temperature Status log (R/WC0).
1323 /// If CPUID.01H:EDX[22] = 1.
1325 UINT32 CriticalTempStatusLog
: 1;
1327 /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.
1329 UINT32 ThermalThreshold1Status
: 1;
1331 /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1333 UINT32 ThermalThreshold1Log
: 1;
1335 /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.
1337 UINT32 ThermalThreshold2Status
: 1;
1339 /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1341 UINT32 ThermalThreshold2Log
: 1;
1343 /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.
1345 UINT32 PowerLimitStatus
: 1;
1347 /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.
1349 UINT32 PowerLimitLog
: 1;
1351 /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1353 UINT32 CurrentLimitStatus
: 1;
1355 /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1357 UINT32 CurrentLimitLog
: 1;
1359 /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1361 UINT32 CrossDomainLimitStatus
: 1;
1363 /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1365 UINT32 CrossDomainLimitLog
: 1;
1367 /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.
1369 UINT32 DigitalReadout
: 7;
1370 UINT32 Reserved1
: 4;
1372 /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =
1375 UINT32 ResolutionInDegreesCelsius
: 4;
1377 /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.
1379 UINT32 ReadingValid
: 1;
1380 UINT32 Reserved2
: 32;
1383 /// All bit fields as a 32-bit value
1387 /// All bit fields as a 64-bit value
1390 } MSR_IA32_THERM_STATUS_REGISTER
;
1393 Enable Misc. Processor Features (R/W) Allows a variety of processor
1394 functions to be enabled and disabled.
1396 @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)
1397 @param EAX Lower 32-bits of MSR value.
1398 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1399 @param EDX Upper 32-bits of MSR value.
1400 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1402 <b>Example usage</b>
1404 MSR_IA32_MISC_ENABLE_REGISTER Msr;
1406 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
1407 AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);
1409 @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
1411 #define MSR_IA32_MISC_ENABLE 0x000001A0
1414 MSR information returned for MSR index #MSR_IA32_MISC_ENABLE
1418 /// Individual bit fields
1422 /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for
1423 /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings
1424 /// are disabled. Introduced at Display Family / Display Model 0F_0H.
1426 UINT32 FastStrings
: 1;
1427 UINT32 Reserved1
: 2;
1429 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
1430 /// this bit enables the thermal control circuit (TCC) portion of the
1431 /// Intel Thermal Monitor feature. This allows the processor to
1432 /// automatically reduce power consumption in response to TCC activation.
1433 /// 0 = Disabled. Note: In some products clearing this bit might be
1434 /// ignored in critical thermal conditions, and TM1, TM2 and adaptive
1435 /// thermal throttling will still be activated. The default value of this
1436 /// field varies with product. See respective tables where default value is
1437 /// listed. Introduced at Display Family / Display Model 0F_0H.
1439 UINT32 AutomaticThermalControlCircuit
: 1;
1440 UINT32 Reserved2
: 3;
1442 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
1443 /// monitoring enabled 0 = Performance monitoring disabled. Introduced at
1444 /// Display Family / Display Model 0F_0H.
1446 UINT32 PerformanceMonitoring
: 1;
1447 UINT32 Reserved3
: 3;
1449 /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't
1450 /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at
1451 /// Display Family / Display Model 0F_0H.
1455 /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =
1456 /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
1457 /// Family / Display Model 06_0FH.
1460 UINT32 Reserved4
: 3;
1462 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced
1463 /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep
1464 /// Technology enabled. If CPUID.01H: ECX[7] =1.
1467 UINT32 Reserved5
: 1;
1469 /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the
1470 /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This
1471 /// indicates that MONITOR/MWAIT are not supported. Software attempts to
1472 /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit
1473 /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit
1474 /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit
1475 /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it
1476 /// in the default state. Writing this bit when the SSE3 feature flag is
1477 /// set to 0 may generate a #GP exception. Introduced at Display Family /
1478 /// Display Model 0F_03H.
1481 UINT32 Reserved6
: 3;
1483 /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
1484 /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup
1485 /// question that allows users to specify when the installed OS does not
1486 /// support CPUID functions greater than 2. Before setting this bit, BIOS
1487 /// must execute the CPUID.0H and examine the maximum value returned in
1488 /// EAX[7:0]. If the maximum value is greater than 2, this bit is
1489 /// supported. Otherwise, this bit is not supported. Setting this bit when
1490 /// the maximum value is not greater than 2 may generate a #GP exception.
1491 /// Setting this bit may cause unexpected behavior in software that
1492 /// depends on the availability of CPUID leaves greater than 2. Introduced
1493 /// at Display Family / Display Model 0F_03H.
1495 UINT32 LimitCpuidMaxval
: 1;
1497 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
1498 /// disabled. xTPR messages are optional messages that allow the processor
1499 /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.
1501 UINT32 xTPR_Message_Disable
: 1;
1502 UINT32 Reserved7
: 8;
1503 UINT32 Reserved8
: 2;
1505 /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit
1506 /// feature (XD Bit) is disabled and the XD Bit extended feature flag will
1507 /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the
1508 /// Execute Disable Bit feature (if available) allows the OS to enable PAE
1509 /// paging and take advantage of data only pages. BIOS must not alter the
1510 /// contents of this bit location, if XD bit is not supported. Writing
1511 /// this bit to 1 when the XD Bit extended feature flag is set to 0 may
1512 /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.
1515 UINT32 Reserved9
: 29;
1518 /// All bit fields as a 64-bit value
1521 } MSR_IA32_MISC_ENABLE_REGISTER
;
1524 Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.
1526 @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)
1527 @param EAX Lower 32-bits of MSR value.
1528 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1529 @param EDX Upper 32-bits of MSR value.
1530 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1532 <b>Example usage</b>
1534 MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;
1536 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);
1537 AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);
1539 @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
1541 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
1544 MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS
1548 /// Individual bit fields
1552 /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest
1553 /// performance. 15 indicates preference to maximize energy saving.
1555 UINT32 PowerPolicyPreference
: 4;
1556 UINT32 Reserved1
: 28;
1557 UINT32 Reserved2
: 32;
1560 /// All bit fields as a 32-bit value
1564 /// All bit fields as a 64-bit value
1567 } MSR_IA32_ENERGY_PERF_BIAS_REGISTER
;
1570 Package Thermal Status Information (RO) Contains status information about
1571 the package's thermal sensor. See Section 14.8, "Package Level Thermal
1572 Management.". If CPUID.06H: EAX[6] = 1.
1574 @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)
1575 @param EAX Lower 32-bits of MSR value.
1576 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1577 @param EDX Upper 32-bits of MSR value.
1578 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1580 <b>Example usage</b>
1582 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;
1584 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);
1586 @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.
1588 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
1591 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS
1595 /// Individual bit fields
1599 /// [Bit 0] Pkg Thermal Status (RO):.
1601 UINT32 ThermalStatus
: 1;
1603 /// [Bit 1] Pkg Thermal Status Log (R/W):.
1605 UINT32 ThermalStatusLog
: 1;
1607 /// [Bit 2] Pkg PROCHOT # event (RO).
1609 UINT32 PROCHOT_Event
: 1;
1611 /// [Bit 3] Pkg PROCHOT # log (R/WC0).
1613 UINT32 PROCHOT_Log
: 1;
1615 /// [Bit 4] Pkg Critical Temperature Status (RO).
1617 UINT32 CriticalTempStatus
: 1;
1619 /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).
1621 UINT32 CriticalTempStatusLog
: 1;
1623 /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).
1625 UINT32 ThermalThreshold1Status
: 1;
1627 /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).
1629 UINT32 ThermalThreshold1Log
: 1;
1631 /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).
1633 UINT32 ThermalThreshold2Status
: 1;
1635 /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).
1637 UINT32 ThermalThreshold2Log
: 1;
1639 /// [Bit 10] Pkg Power Limitation Status (RO).
1641 UINT32 PowerLimitStatus
: 1;
1643 /// [Bit 11] Pkg Power Limitation log (R/WC0).
1645 UINT32 PowerLimitLog
: 1;
1646 UINT32 Reserved1
: 4;
1648 /// [Bits 22:16] Pkg Digital Readout (RO).
1650 UINT32 DigitalReadout
: 7;
1651 UINT32 Reserved2
: 9;
1652 UINT32 Reserved3
: 32;
1655 /// All bit fields as a 32-bit value
1659 /// All bit fields as a 64-bit value
1662 } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
;
1665 Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of
1666 an interrupt on temperature transitions detected with the package's thermal
1667 sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:
1670 @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)
1671 @param EAX Lower 32-bits of MSR value.
1672 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1673 @param EDX Upper 32-bits of MSR value.
1674 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1676 <b>Example usage</b>
1678 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;
1680 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);
1681 AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);
1683 @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.
1685 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
1688 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT
1692 /// Individual bit fields
1696 /// [Bit 0] Pkg High-Temperature Interrupt Enable.
1698 UINT32 HighTempEnable
: 1;
1700 /// [Bit 1] Pkg Low-Temperature Interrupt Enable.
1702 UINT32 LowTempEnable
: 1;
1704 /// [Bit 2] Pkg PROCHOT# Interrupt Enable.
1706 UINT32 PROCHOT_Enable
: 1;
1707 UINT32 Reserved1
: 1;
1709 /// [Bit 4] Pkg Overheat Interrupt Enable.
1711 UINT32 OverheatEnable
: 1;
1712 UINT32 Reserved2
: 3;
1714 /// [Bits 14:8] Pkg Threshold #1 Value.
1716 UINT32 Threshold1
: 7;
1718 /// [Bit 15] Pkg Threshold #1 Interrupt Enable.
1720 UINT32 Threshold1Enable
: 1;
1722 /// [Bits 22:16] Pkg Threshold #2 Value.
1724 UINT32 Threshold2
: 7;
1726 /// [Bit 23] Pkg Threshold #2 Interrupt Enable.
1728 UINT32 Threshold2Enable
: 1;
1730 /// [Bit 24] Pkg Power Limit Notification Enable.
1732 UINT32 PowerLimitNotificationEnable
: 1;
1733 UINT32 Reserved3
: 7;
1734 UINT32 Reserved4
: 32;
1737 /// All bit fields as a 32-bit value
1741 /// All bit fields as a 64-bit value
1744 } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
;
1747 Trace/Profile Resource Control (R/W). Introduced at Display Family / Display
1750 @param ECX MSR_IA32_DEBUGCTL (0x000001D9)
1751 @param EAX Lower 32-bits of MSR value.
1752 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1753 @param EDX Upper 32-bits of MSR value.
1754 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1756 <b>Example usage</b>
1758 MSR_IA32_DEBUGCTL_REGISTER Msr;
1760 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
1761 AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);
1763 @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.
1765 #define MSR_IA32_DEBUGCTL 0x000001D9
1768 MSR information returned for MSR index #MSR_IA32_DEBUGCTL
1772 /// Individual bit fields
1776 /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a
1777 /// running trace of the most recent branches taken by the processor in
1778 /// the LBR stack. Introduced at Display Family / Display Model 06_01H.
1782 /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat
1783 /// EFLAGS.TF as single-step on branches instead of single-step on
1784 /// instructions. Introduced at Display Family / Display Model 06_01H.
1787 UINT32 Reserved1
: 4;
1789 /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be
1790 /// sent. Introduced at Display Family / Display Model 06_0EH.
1794 /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to
1795 /// be logged in a BTS buffer. Introduced at Display Family / Display
1800 /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular
1801 /// fashion. When this bit is set, an interrupt is generated by the BTS
1802 /// facility when the BTS buffer is full. Introduced at Display Family /
1803 /// Display Model 06_0EH.
1807 /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.
1808 /// Introduced at Display Family / Display Model 06_0FH.
1810 UINT32 BTS_OFF_OS
: 1;
1812 /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.
1813 /// Introduced at Display Family / Display Model 06_0FH.
1815 UINT32 BTS_OFF_USR
: 1;
1817 /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a
1818 /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1820 UINT32 FREEZE_LBRS_ON_PMI
: 1;
1822 /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the
1823 /// global counter control MSR are frozen (address 38FH) on a PMI request.
1824 /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1826 UINT32 FREEZE_PERFMON_ON_PMI
: 1;
1828 /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to
1829 /// receive and generate PMI on behalf of the uncore. Introduced at
1830 /// Display Family / Display Model 06_1AH.
1832 UINT32 ENABLE_UNCORE_PMI
: 1;
1834 /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace
1835 /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.
1837 UINT32 FREEZE_WHILE_SMM
: 1;
1839 /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If
1840 /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).
1842 UINT32 RTM_DEBUG
: 1;
1843 UINT32 Reserved2
: 16;
1844 UINT32 Reserved3
: 32;
1847 /// All bit fields as a 32-bit value
1851 /// All bit fields as a 64-bit value
1854 } MSR_IA32_DEBUGCTL_REGISTER
;
1857 SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.
1858 If IA32_MTRRCAP.SMRR[11] = 1.
1860 @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)
1861 @param EAX Lower 32-bits of MSR value.
1862 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1863 @param EDX Upper 32-bits of MSR value.
1864 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1866 <b>Example usage</b>
1868 MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;
1870 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);
1871 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);
1873 @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.
1875 #define MSR_IA32_SMRR_PHYSBASE 0x000001F2
1878 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE
1882 /// Individual bit fields
1886 /// [Bits 7:0] Type. Specifies memory type of the range.
1889 UINT32 Reserved1
: 4;
1891 /// [Bits 31:12] PhysBase. SMRR physical Base Address.
1893 UINT32 PhysBase
: 20;
1894 UINT32 Reserved2
: 32;
1897 /// All bit fields as a 32-bit value
1901 /// All bit fields as a 64-bit value
1904 } MSR_IA32_SMRR_PHYSBASE_REGISTER
;
1907 SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If
1908 IA32_MTRRCAP[SMRR] = 1.
1910 @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)
1911 @param EAX Lower 32-bits of MSR value.
1912 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1913 @param EDX Upper 32-bits of MSR value.
1914 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1916 <b>Example usage</b>
1918 MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;
1920 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);
1921 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);
1923 @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.
1925 #define MSR_IA32_SMRR_PHYSMASK 0x000001F3
1928 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK
1932 /// Individual bit fields
1935 UINT32 Reserved1
: 11;
1937 /// [Bit 11] Valid Enable range mask.
1941 /// [Bits 31:12] PhysMask SMRR address range mask.
1943 UINT32 PhysMask
: 20;
1944 UINT32 Reserved2
: 32;
1947 /// All bit fields as a 32-bit value
1951 /// All bit fields as a 64-bit value
1954 } MSR_IA32_SMRR_PHYSMASK_REGISTER
;
1957 DCA Capability (R). If CPUID.01H: ECX[18] = 1.
1959 @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)
1960 @param EAX Lower 32-bits of MSR value.
1961 @param EDX Upper 32-bits of MSR value.
1963 <b>Example usage</b>
1967 Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);
1969 @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.
1971 #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
1974 If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.
1976 @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)
1977 @param EAX Lower 32-bits of MSR value.
1978 @param EDX Upper 32-bits of MSR value.
1980 <b>Example usage</b>
1984 Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);
1985 AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);
1987 @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.
1989 #define MSR_IA32_CPU_DCA_CAP 0x000001F9
1992 DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.
1994 @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)
1995 @param EAX Lower 32-bits of MSR value.
1996 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
1997 @param EDX Upper 32-bits of MSR value.
1998 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
2000 <b>Example usage</b>
2002 MSR_IA32_DCA_0_CAP_REGISTER Msr;
2004 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);
2005 AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);
2007 @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.
2009 #define MSR_IA32_DCA_0_CAP 0x000001FA
2012 MSR information returned for MSR index #MSR_IA32_DCA_0_CAP
2016 /// Individual bit fields
2020 /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no
2021 /// defeatures are set.
2023 UINT32 DCA_ACTIVE
: 1;
2025 /// [Bits 2:1] TRANSACTION.
2027 UINT32 TRANSACTION
: 2;
2029 /// [Bits 6:3] DCA_TYPE.
2031 UINT32 DCA_TYPE
: 4;
2033 /// [Bits 10:7] DCA_QUEUE_SIZE.
2035 UINT32 DCA_QUEUE_SIZE
: 4;
2036 UINT32 Reserved1
: 2;
2038 /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW
2041 UINT32 DCA_DELAY
: 4;
2042 UINT32 Reserved2
: 7;
2044 /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.
2046 UINT32 SW_BLOCK
: 1;
2047 UINT32 Reserved3
: 1;
2049 /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).
2051 UINT32 HW_BLOCK
: 1;
2052 UINT32 Reserved4
: 5;
2053 UINT32 Reserved5
: 32;
2056 /// All bit fields as a 32-bit value
2060 /// All bit fields as a 64-bit value
2063 } MSR_IA32_DCA_0_CAP_REGISTER
;
2066 MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".
2067 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2069 @param ECX MSR_IA32_MTRR_PHYSBASEn
2070 @param EAX Lower 32-bits of MSR value.
2071 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
2072 @param EDX Upper 32-bits of MSR value.
2073 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
2075 <b>Example usage</b>
2077 MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;
2079 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
2080 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);
2082 @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.
2083 MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.
2084 MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.
2085 MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.
2086 MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.
2087 MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.
2088 MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.
2089 MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.
2090 MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.
2091 MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.
2094 #define MSR_IA32_MTRR_PHYSBASE0 0x00000200
2095 #define MSR_IA32_MTRR_PHYSBASE1 0x00000202
2096 #define MSR_IA32_MTRR_PHYSBASE2 0x00000204
2097 #define MSR_IA32_MTRR_PHYSBASE3 0x00000206
2098 #define MSR_IA32_MTRR_PHYSBASE4 0x00000208
2099 #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
2100 #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
2101 #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
2102 #define MSR_IA32_MTRR_PHYSBASE8 0x00000210
2103 #define MSR_IA32_MTRR_PHYSBASE9 0x00000212
2107 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
2108 #MSR_IA32_MTRR_PHYSBASE9
2112 /// Individual bit fields
2116 /// [Bits 7:0] Type. Specifies memory type of the range.
2119 UINT32 Reserved1
: 4;
2121 /// [Bits 31:12] PhysBase. MTRR physical Base Address.
2123 UINT32 PhysBase
: 20;
2125 /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.
2126 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2127 /// maximum physical address range supported by the processor. It is
2128 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2129 /// leaf 80000008H, the processor supports 36-bit physical address size,
2130 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2132 UINT32 PhysBaseHi
: 32;
2135 /// All bit fields as a 64-bit value
2138 } MSR_IA32_MTRR_PHYSBASE_REGISTER
;
2141 MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".
2142 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2144 @param ECX MSR_IA32_MTRR_PHYSMASKn
2145 @param EAX Lower 32-bits of MSR value.
2146 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2147 @param EDX Upper 32-bits of MSR value.
2148 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2150 <b>Example usage</b>
2152 MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;
2154 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
2155 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);
2157 @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.
2158 MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.
2159 MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.
2160 MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.
2161 MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.
2162 MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.
2163 MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.
2164 MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.
2165 MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.
2166 MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.
2169 #define MSR_IA32_MTRR_PHYSMASK0 0x00000201
2170 #define MSR_IA32_MTRR_PHYSMASK1 0x00000203
2171 #define MSR_IA32_MTRR_PHYSMASK2 0x00000205
2172 #define MSR_IA32_MTRR_PHYSMASK3 0x00000207
2173 #define MSR_IA32_MTRR_PHYSMASK4 0x00000209
2174 #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
2175 #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
2176 #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
2177 #define MSR_IA32_MTRR_PHYSMASK8 0x00000211
2178 #define MSR_IA32_MTRR_PHYSMASK9 0x00000213
2182 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to
2183 #MSR_IA32_MTRR_PHYSMASK9
2187 /// Individual bit fields
2190 UINT32 Reserved1
: 11;
2192 /// [Bit 11] Valid Enable range mask.
2196 /// [Bits 31:12] PhysMask. MTRR address range mask.
2198 UINT32 PhysMask
: 20;
2200 /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.
2201 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2202 /// maximum physical address range supported by the processor. It is
2203 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2204 /// leaf 80000008H, the processor supports 36-bit physical address size,
2205 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2207 UINT32 PhysMaskHi
: 32;
2210 /// All bit fields as a 64-bit value
2213 } MSR_IA32_MTRR_PHYSMASK_REGISTER
;
2216 MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.
2218 @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)
2219 @param EAX Lower 32-bits of MSR value.
2220 @param EDX Upper 32-bits of MSR value.
2222 <b>Example usage</b>
2226 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);
2227 AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);
2229 @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.
2231 #define MSR_IA32_MTRR_FIX64K_00000 0x00000250
2234 MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.
2236 @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)
2237 @param EAX Lower 32-bits of MSR value.
2238 @param EDX Upper 32-bits of MSR value.
2240 <b>Example usage</b>
2244 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);
2245 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);
2247 @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.
2249 #define MSR_IA32_MTRR_FIX16K_80000 0x00000258
2252 MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.
2254 @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)
2255 @param EAX Lower 32-bits of MSR value.
2256 @param EDX Upper 32-bits of MSR value.
2258 <b>Example usage</b>
2262 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);
2263 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);
2265 @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.
2267 #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
2270 See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.
2272 @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)
2273 @param EAX Lower 32-bits of MSR value.
2274 @param EDX Upper 32-bits of MSR value.
2276 <b>Example usage</b>
2280 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);
2281 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);
2283 @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.
2285 #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
2288 MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.
2290 @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)
2291 @param EAX Lower 32-bits of MSR value.
2292 @param EDX Upper 32-bits of MSR value.
2294 <b>Example usage</b>
2298 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);
2299 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);
2301 @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.
2303 #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
2306 MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.
2308 @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)
2309 @param EAX Lower 32-bits of MSR value.
2310 @param EDX Upper 32-bits of MSR value.
2312 <b>Example usage</b>
2316 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);
2317 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);
2319 @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.
2321 #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
2324 MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.
2326 @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)
2327 @param EAX Lower 32-bits of MSR value.
2328 @param EDX Upper 32-bits of MSR value.
2330 <b>Example usage</b>
2334 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);
2335 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);
2337 @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.
2339 #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
2342 MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.
2344 @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)
2345 @param EAX Lower 32-bits of MSR value.
2346 @param EDX Upper 32-bits of MSR value.
2348 <b>Example usage</b>
2352 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);
2353 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);
2355 @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.
2357 #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
2360 MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.
2362 @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)
2363 @param EAX Lower 32-bits of MSR value.
2364 @param EDX Upper 32-bits of MSR value.
2366 <b>Example usage</b>
2370 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);
2371 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);
2373 @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.
2375 #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
2378 MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.
2380 @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)
2381 @param EAX Lower 32-bits of MSR value.
2382 @param EDX Upper 32-bits of MSR value.
2384 <b>Example usage</b>
2388 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);
2389 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);
2391 @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.
2393 #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
2396 MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.
2398 @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)
2399 @param EAX Lower 32-bits of MSR value.
2400 @param EDX Upper 32-bits of MSR value.
2402 <b>Example usage</b>
2406 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);
2407 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);
2409 @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.
2411 #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
2414 IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.
2416 @param ECX MSR_IA32_PAT (0x00000277)
2417 @param EAX Lower 32-bits of MSR value.
2418 Described by the type MSR_IA32_PAT_REGISTER.
2419 @param EDX Upper 32-bits of MSR value.
2420 Described by the type MSR_IA32_PAT_REGISTER.
2422 <b>Example usage</b>
2424 MSR_IA32_PAT_REGISTER Msr;
2426 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);
2427 AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);
2429 @note MSR_IA32_PAT is defined as IA32_PAT in SDM.
2431 #define MSR_IA32_PAT 0x00000277
2434 MSR information returned for MSR index #MSR_IA32_PAT
2438 /// Individual bit fields
2445 UINT32 Reserved1
: 5;
2447 /// [Bits 10:8] PA1.
2450 UINT32 Reserved2
: 5;
2452 /// [Bits 18:16] PA2.
2455 UINT32 Reserved3
: 5;
2457 /// [Bits 26:24] PA3.
2460 UINT32 Reserved4
: 5;
2462 /// [Bits 34:32] PA4.
2465 UINT32 Reserved5
: 5;
2467 /// [Bits 42:40] PA5.
2470 UINT32 Reserved6
: 5;
2472 /// [Bits 50:48] PA6.
2475 UINT32 Reserved7
: 5;
2477 /// [Bits 58:56] PA7.
2480 UINT32 Reserved8
: 5;
2483 /// All bit fields as a 64-bit value
2486 } MSR_IA32_PAT_REGISTER
;
2489 Provides the programming interface to use corrected MC error signaling
2490 capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.
2492 @param ECX MSR_IA32_MCn_CTL2
2493 @param EAX Lower 32-bits of MSR value.
2494 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2495 @param EDX Upper 32-bits of MSR value.
2496 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2498 <b>Example usage</b>
2500 MSR_IA32_MC_CTL2_REGISTER Msr;
2502 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
2503 AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);
2505 @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.
2506 MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.
2507 MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.
2508 MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.
2509 MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
2510 MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.
2511 MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.
2512 MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.
2513 MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.
2514 MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.
2515 MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.
2516 MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.
2517 MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.
2518 MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.
2519 MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.
2520 MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.
2521 MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.
2522 MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.
2523 MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.
2524 MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.
2525 MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.
2526 MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.
2527 MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.
2528 MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.
2529 MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.
2530 MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.
2531 MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.
2532 MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.
2533 MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.
2534 MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.
2535 MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.
2536 MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.
2539 #define MSR_IA32_MC0_CTL2 0x00000280
2540 #define MSR_IA32_MC1_CTL2 0x00000281
2541 #define MSR_IA32_MC2_CTL2 0x00000282
2542 #define MSR_IA32_MC3_CTL2 0x00000283
2543 #define MSR_IA32_MC4_CTL2 0x00000284
2544 #define MSR_IA32_MC5_CTL2 0x00000285
2545 #define MSR_IA32_MC6_CTL2 0x00000286
2546 #define MSR_IA32_MC7_CTL2 0x00000287
2547 #define MSR_IA32_MC8_CTL2 0x00000288
2548 #define MSR_IA32_MC9_CTL2 0x00000289
2549 #define MSR_IA32_MC10_CTL2 0x0000028A
2550 #define MSR_IA32_MC11_CTL2 0x0000028B
2551 #define MSR_IA32_MC12_CTL2 0x0000028C
2552 #define MSR_IA32_MC13_CTL2 0x0000028D
2553 #define MSR_IA32_MC14_CTL2 0x0000028E
2554 #define MSR_IA32_MC15_CTL2 0x0000028F
2555 #define MSR_IA32_MC16_CTL2 0x00000290
2556 #define MSR_IA32_MC17_CTL2 0x00000291
2557 #define MSR_IA32_MC18_CTL2 0x00000292
2558 #define MSR_IA32_MC19_CTL2 0x00000293
2559 #define MSR_IA32_MC20_CTL2 0x00000294
2560 #define MSR_IA32_MC21_CTL2 0x00000295
2561 #define MSR_IA32_MC22_CTL2 0x00000296
2562 #define MSR_IA32_MC23_CTL2 0x00000297
2563 #define MSR_IA32_MC24_CTL2 0x00000298
2564 #define MSR_IA32_MC25_CTL2 0x00000299
2565 #define MSR_IA32_MC26_CTL2 0x0000029A
2566 #define MSR_IA32_MC27_CTL2 0x0000029B
2567 #define MSR_IA32_MC28_CTL2 0x0000029C
2568 #define MSR_IA32_MC29_CTL2 0x0000029D
2569 #define MSR_IA32_MC30_CTL2 0x0000029E
2570 #define MSR_IA32_MC31_CTL2 0x0000029F
2574 MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2
2575 to #MSR_IA32_MC31_CTL2
2579 /// Individual bit fields
2583 /// [Bits 14:0] Corrected error count threshold.
2585 UINT32 CorrectedErrorCountThreshold
: 15;
2586 UINT32 Reserved1
: 15;
2588 /// [Bit 30] CMCI_EN.
2591 UINT32 Reserved2
: 1;
2592 UINT32 Reserved3
: 32;
2595 /// All bit fields as a 32-bit value
2599 /// All bit fields as a 64-bit value
2602 } MSR_IA32_MC_CTL2_REGISTER
;
2605 MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.
2607 @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)
2608 @param EAX Lower 32-bits of MSR value.
2609 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2610 @param EDX Upper 32-bits of MSR value.
2611 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2613 <b>Example usage</b>
2615 MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;
2617 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
2618 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);
2620 @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.
2622 #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
2625 MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE
2629 /// Individual bit fields
2633 /// [Bits 2:0] Default Memory Type.
2636 UINT32 Reserved1
: 7;
2638 /// [Bit 10] Fixed Range MTRR Enable.
2642 /// [Bit 11] MTRR Enable.
2645 UINT32 Reserved2
: 20;
2646 UINT32 Reserved3
: 32;
2649 /// All bit fields as a 32-bit value
2653 /// All bit fields as a 64-bit value
2656 } MSR_IA32_MTRR_DEF_TYPE_REGISTER
;
2659 Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If
2660 CPUID.0AH: EDX[4:0] > 0.
2662 @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)
2663 @param EAX Lower 32-bits of MSR value.
2664 @param EDX Upper 32-bits of MSR value.
2666 <b>Example usage</b>
2670 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);
2671 AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);
2673 @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.
2675 #define MSR_IA32_FIXED_CTR0 0x00000309
2678 Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If
2679 CPUID.0AH: EDX[4:0] > 1.
2681 @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)
2682 @param EAX Lower 32-bits of MSR value.
2683 @param EDX Upper 32-bits of MSR value.
2685 <b>Example usage</b>
2689 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);
2690 AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);
2692 @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.
2694 #define MSR_IA32_FIXED_CTR1 0x0000030A
2697 Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If
2698 CPUID.0AH: EDX[4:0] > 2.
2700 @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)
2701 @param EAX Lower 32-bits of MSR value.
2702 @param EDX Upper 32-bits of MSR value.
2704 <b>Example usage</b>
2708 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);
2709 AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);
2711 @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.
2713 #define MSR_IA32_FIXED_CTR2 0x0000030B
2716 RO. If CPUID.01H: ECX[15] = 1.
2718 @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)
2719 @param EAX Lower 32-bits of MSR value.
2720 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2721 @param EDX Upper 32-bits of MSR value.
2722 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2724 <b>Example usage</b>
2726 MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;
2728 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);
2729 AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);
2731 @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.
2733 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
2736 MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES
2740 /// Individual bit fields
2744 /// [Bits 5:0] LBR format.
2748 /// [Bit 6] PEBS Trap.
2750 UINT32 PEBS_TRAP
: 1;
2752 /// [Bit 7] PEBSSaveArchRegs.
2754 UINT32 PEBS_ARCH_REG
: 1;
2756 /// [Bits 11:8] PEBS Record Format.
2758 UINT32 PEBS_REC_FMT
: 4;
2760 /// [Bit 12] 1: Freeze while SMM is supported.
2762 UINT32 SMM_FREEZE
: 1;
2764 /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
2766 UINT32 FW_WRITE
: 1;
2767 UINT32 Reserved1
: 18;
2768 UINT32 Reserved2
: 32;
2771 /// All bit fields as a 32-bit value
2775 /// All bit fields as a 64-bit value
2778 } MSR_IA32_PERF_CAPABILITIES_REGISTER
;
2781 Fixed-Function Performance Counter Control (R/W) Counter increments while
2782 the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with
2783 the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]
2786 @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)
2787 @param EAX Lower 32-bits of MSR value.
2788 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2789 @param EDX Upper 32-bits of MSR value.
2790 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2792 <b>Example usage</b>
2794 MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;
2796 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);
2797 AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);
2799 @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.
2801 #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
2804 MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL
2808 /// Individual bit fields
2812 /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
2816 /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
2820 /// [Bit 2] AnyThread: When set to 1, it enables counting the associated
2821 /// event conditions occurring across all logical processors sharing a
2822 /// processor core. When set to 0, the counter only increments the
2823 /// associated event conditions occurring in the logical processor which
2824 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2826 UINT32 AnyThread0
: 1;
2828 /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.
2832 /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.
2836 /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.
2840 /// [Bit 6] AnyThread: When set to 1, it enables counting the associated
2841 /// event conditions occurring across all logical processors sharing a
2842 /// processor core. When set to 0, the counter only increments the
2843 /// associated event conditions occurring in the logical processor which
2844 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2846 UINT32 AnyThread1
: 1;
2848 /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.
2852 /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
2856 /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
2860 /// [Bit 10] AnyThread: When set to 1, it enables counting the associated
2861 /// event conditions occurring across all logical processors sharing a
2862 /// processor core. When set to 0, the counter only increments the
2863 /// associated event conditions occurring in the logical processor which
2864 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2866 UINT32 AnyThread2
: 1;
2868 /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.
2871 UINT32 Reserved1
: 20;
2872 UINT32 Reserved2
: 32;
2875 /// All bit fields as a 32-bit value
2879 /// All bit fields as a 64-bit value
2882 } MSR_IA32_FIXED_CTR_CTRL_REGISTER
;
2885 Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.
2887 @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)
2888 @param EAX Lower 32-bits of MSR value.
2889 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2890 @param EDX Upper 32-bits of MSR value.
2891 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2893 <b>Example usage</b>
2895 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
2897 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);
2899 @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
2901 #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
2904 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS
2908 /// Individual bit fields
2912 /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:
2915 UINT32 Ovf_PMC0
: 1;
2917 /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:
2920 UINT32 Ovf_PMC1
: 1;
2922 /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:
2925 UINT32 Ovf_PMC2
: 1;
2927 /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:
2930 UINT32 Ovf_PMC3
: 1;
2931 UINT32 Reserved1
: 28;
2933 /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If
2934 /// CPUID.0AH: EAX[7:0] > 1.
2936 UINT32 Ovf_FixedCtr0
: 1;
2938 /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If
2939 /// CPUID.0AH: EAX[7:0] > 1.
2941 UINT32 Ovf_FixedCtr1
: 1;
2943 /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If
2944 /// CPUID.0AH: EAX[7:0] > 1.
2946 UINT32 Ovf_FixedCtr2
: 1;
2947 UINT32 Reserved2
: 20;
2949 /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory
2950 /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
2951 /// && IA32_RTIT_CTL.ToPA = 1.
2953 UINT32 Trace_ToPA_PMI
: 1;
2954 UINT32 Reserved3
: 2;
2956 /// [Bit 58] LBR_Frz: LBRs are frozen due to -
2957 /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If
2958 /// CPUID.0AH: EAX[7:0] > 3.
2962 /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due
2963 /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU
2964 /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.
2968 /// [Bit 60] ASCI: Data in the performance counters in the core PMU may
2969 /// include contributions from the direct or indirect operation intel SGX
2970 /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.
2974 /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:
2977 UINT32 Ovf_Uncore
: 1;
2979 /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:
2984 /// [Bit 63] CondChgd: status bits of this register has changed. If
2985 /// CPUID.0AH: EAX[7:0] > 0.
2987 UINT32 CondChgd
: 1;
2990 /// All bit fields as a 64-bit value
2993 } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER
;
2996 Global Performance Counter Control (R/W) Counter increments while the result
2997 of ANDing respective enable bit in this MSR with the corresponding OS or USR
2998 bits in the general-purpose or fixed counter control MSR is true. If
2999 CPUID.0AH: EAX[7:0] > 0.
3001 @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)
3002 @param EAX Lower 32-bits of MSR value.
3003 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
3004 @param EDX Upper 32-bits of MSR value.
3005 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
3007 <b>Example usage</b>
3009 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
3011 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);
3012 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
3014 @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
3016 #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
3019 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL
3023 /// Individual bit fields
3027 /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.
3028 /// Enable bitmask. Only the first n-1 bits are valid.
3029 /// Bits n..31 are reserved.
3031 UINT32 EN_PMCn
: 32;
3033 /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.
3034 /// Enable bitmask. Only the first n-1 bits are valid.
3035 /// Bits 31:n are reserved.
3037 UINT32 EN_FIXED_CTRn
: 32;
3040 /// All bit fields as a 64-bit value
3043 } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
;
3046 Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >
3047 0 && CPUID.0AH: EAX[7:0] <= 3.
3049 @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
3050 @param EAX Lower 32-bits of MSR value.
3051 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
3052 @param EDX Upper 32-bits of MSR value.
3053 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
3055 <b>Example usage</b>
3057 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
3059 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);
3060 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
3062 @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
3064 #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
3067 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL
3071 /// Individual bit fields
3075 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3076 /// Clear bitmask. Only the first n-1 bits are valid.
3077 /// Bits 31:n are reserved.
3079 UINT32 Ovf_PMCn
: 32;
3081 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3082 /// If CPUID.0AH: EDX[4:0] > n.
3083 /// Clear bitmask. Only the first n-1 bits are valid.
3084 /// Bits 22:n are reserved.
3086 UINT32 Ovf_FIXED_CTRn
: 23;
3088 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3089 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.
3091 UINT32 Trace_ToPA_PMI
: 1;
3092 UINT32 Reserved2
: 5;
3094 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3095 /// Display Model 06_2EH.
3097 UINT32 Ovf_Uncore
: 1;
3099 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3103 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3105 UINT32 CondChgd
: 1;
3108 /// All bit fields as a 64-bit value
3111 } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
3114 Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:
3117 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
3118 @param EAX Lower 32-bits of MSR value.
3119 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
3120 @param EDX Upper 32-bits of MSR value.
3121 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
3123 <b>Example usage</b>
3125 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
3127 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);
3128 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
3130 @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
3132 #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
3135 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET
3139 /// Individual bit fields
3143 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3144 /// Clear bitmask. Only the first n-1 bits are valid.
3145 /// Bits 31:n are reserved.
3147 UINT32 Ovf_PMCn
: 32;
3149 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3150 /// If CPUID.0AH: EDX[4:0] > n.
3151 /// Clear bitmask. Only the first n-1 bits are valid.
3152 /// Bits 22:n are reserved.
3154 UINT32 Ovf_FIXED_CTRn
: 23;
3156 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3157 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.
3159 UINT32 Trace_ToPA_PMI
: 1;
3160 UINT32 Reserved2
: 2;
3162 /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3166 /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3170 /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.
3174 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3175 /// Display Model 06_2EH.
3177 UINT32 Ovf_Uncore
: 1;
3179 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3183 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3185 UINT32 CondChgd
: 1;
3188 /// All bit fields as a 64-bit value
3191 } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
3194 Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:
3197 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
3198 @param EAX Lower 32-bits of MSR value.
3199 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3200 @param EDX Upper 32-bits of MSR value.
3201 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3203 <b>Example usage</b>
3205 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
3207 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);
3208 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
3210 @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
3212 #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
3215 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET
3219 /// Individual bit fields
3223 /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.
3224 /// Set bitmask. Only the first n-1 bits are valid.
3225 /// Bits 31:n are reserved.
3227 UINT32 Ovf_PMCn
: 32;
3229 /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.
3230 /// If CPUID.0AH: EAX[7:0] > n.
3231 /// Set bitmask. Only the first n-1 bits are valid.
3232 /// Bits 22:n are reserved.
3234 UINT32 Ovf_FIXED_CTRn
: 23;
3236 /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.
3238 UINT32 Trace_ToPA_PMI
: 1;
3239 UINT32 Reserved2
: 2;
3241 /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3245 /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3249 /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.
3253 /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.
3255 UINT32 Ovf_Uncore
: 1;
3257 /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.
3260 UINT32 Reserved3
: 1;
3263 /// All bit fields as a 64-bit value
3266 } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
3269 Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >
3272 @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)
3273 @param EAX Lower 32-bits of MSR value.
3274 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3275 @param EDX Upper 32-bits of MSR value.
3276 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3278 <b>Example usage</b>
3280 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;
3282 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);
3284 @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.
3286 #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
3289 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE
3293 /// Individual bit fields
3297 /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.
3298 /// Status bitmask. Only the first n-1 bits are valid.
3299 /// Bits 31:n are reserved.
3301 UINT32 IA32_PERFEVTSELn
: 32;
3303 /// [Bits 62:32] IA32_FIXED_CTRn in use.
3304 /// If CPUID.0AH: EAX[7:0] > n.
3305 /// Status bitmask. Only the first n-1 bits are valid.
3306 /// Bits 30:n are reserved.
3308 UINT32 IA32_FIXED_CTRn
: 31;
3310 /// [Bit 63] PMI in use.
3315 /// All bit fields as a 64-bit value
3318 } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
;
3323 @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)
3324 @param EAX Lower 32-bits of MSR value.
3325 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3326 @param EDX Upper 32-bits of MSR value.
3327 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3329 <b>Example usage</b>
3331 MSR_IA32_PEBS_ENABLE_REGISTER Msr;
3333 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);
3334 AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);
3336 @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.
3338 #define MSR_IA32_PEBS_ENABLE 0x000003F1
3341 MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE
3345 /// Individual bit fields
3349 /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /
3350 /// Display Model 06_0FH.
3354 /// [Bits 3:1] Reserved or Model specific.
3356 UINT32 Reserved1
: 3;
3357 UINT32 Reserved2
: 28;
3359 /// [Bits 35:32] Reserved or Model specific.
3361 UINT32 Reserved3
: 4;
3362 UINT32 Reserved4
: 28;
3365 /// All bit fields as a 64-bit value
3368 } MSR_IA32_PEBS_ENABLE_REGISTER
;
3371 MCn_CTL. If IA32_MCG_CAP.CNT > n.
3373 @param ECX MSR_IA32_MCn_CTL
3374 @param EAX Lower 32-bits of MSR value.
3375 @param EDX Upper 32-bits of MSR value.
3377 <b>Example usage</b>
3381 Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
3382 AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);
3384 @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.
3385 MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.
3386 MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.
3387 MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.
3388 MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
3389 MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.
3390 MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.
3391 MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.
3392 MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.
3393 MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.
3394 MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.
3395 MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.
3396 MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.
3397 MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.
3398 MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.
3399 MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.
3400 MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.
3401 MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.
3402 MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.
3403 MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.
3404 MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.
3405 MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.
3406 MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.
3407 MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.
3408 MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.
3409 MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.
3410 MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.
3411 MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.
3412 MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.
3415 #define MSR_IA32_MC0_CTL 0x00000400
3416 #define MSR_IA32_MC1_CTL 0x00000404
3417 #define MSR_IA32_MC2_CTL 0x00000408
3418 #define MSR_IA32_MC3_CTL 0x0000040C
3419 #define MSR_IA32_MC4_CTL 0x00000410
3420 #define MSR_IA32_MC5_CTL 0x00000414
3421 #define MSR_IA32_MC6_CTL 0x00000418
3422 #define MSR_IA32_MC7_CTL 0x0000041C
3423 #define MSR_IA32_MC8_CTL 0x00000420
3424 #define MSR_IA32_MC9_CTL 0x00000424
3425 #define MSR_IA32_MC10_CTL 0x00000428
3426 #define MSR_IA32_MC11_CTL 0x0000042C
3427 #define MSR_IA32_MC12_CTL 0x00000430
3428 #define MSR_IA32_MC13_CTL 0x00000434
3429 #define MSR_IA32_MC14_CTL 0x00000438
3430 #define MSR_IA32_MC15_CTL 0x0000043C
3431 #define MSR_IA32_MC16_CTL 0x00000440
3432 #define MSR_IA32_MC17_CTL 0x00000444
3433 #define MSR_IA32_MC18_CTL 0x00000448
3434 #define MSR_IA32_MC19_CTL 0x0000044C
3435 #define MSR_IA32_MC20_CTL 0x00000450
3436 #define MSR_IA32_MC21_CTL 0x00000454
3437 #define MSR_IA32_MC22_CTL 0x00000458
3438 #define MSR_IA32_MC23_CTL 0x0000045C
3439 #define MSR_IA32_MC24_CTL 0x00000460
3440 #define MSR_IA32_MC25_CTL 0x00000464
3441 #define MSR_IA32_MC26_CTL 0x00000468
3442 #define MSR_IA32_MC27_CTL 0x0000046C
3443 #define MSR_IA32_MC28_CTL 0x00000470
3447 MCn_STATUS. If IA32_MCG_CAP.CNT > n.
3449 @param ECX MSR_IA32_MCn_STATUS
3450 @param EAX Lower 32-bits of MSR value.
3451 @param EDX Upper 32-bits of MSR value.
3453 <b>Example usage</b>
3457 Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
3458 AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);
3460 @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.
3461 MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.
3462 MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.
3463 MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.
3464 MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.
3465 MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.
3466 MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.
3467 MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.
3468 MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.
3469 MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.
3470 MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.
3471 MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.
3472 MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.
3473 MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.
3474 MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.
3475 MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.
3476 MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.
3477 MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.
3478 MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.
3479 MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.
3480 MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.
3481 MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.
3482 MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.
3483 MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.
3484 MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.
3485 MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.
3486 MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.
3487 MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.
3488 MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.
3491 #define MSR_IA32_MC0_STATUS 0x00000401
3492 #define MSR_IA32_MC1_STATUS 0x00000405
3493 #define MSR_IA32_MC2_STATUS 0x00000409
3494 #define MSR_IA32_MC3_STATUS 0x0000040D
3495 #define MSR_IA32_MC4_STATUS 0x00000411
3496 #define MSR_IA32_MC5_STATUS 0x00000415
3497 #define MSR_IA32_MC6_STATUS 0x00000419
3498 #define MSR_IA32_MC7_STATUS 0x0000041D
3499 #define MSR_IA32_MC8_STATUS 0x00000421
3500 #define MSR_IA32_MC9_STATUS 0x00000425
3501 #define MSR_IA32_MC10_STATUS 0x00000429
3502 #define MSR_IA32_MC11_STATUS 0x0000042D
3503 #define MSR_IA32_MC12_STATUS 0x00000431
3504 #define MSR_IA32_MC13_STATUS 0x00000435
3505 #define MSR_IA32_MC14_STATUS 0x00000439
3506 #define MSR_IA32_MC15_STATUS 0x0000043D
3507 #define MSR_IA32_MC16_STATUS 0x00000441
3508 #define MSR_IA32_MC17_STATUS 0x00000445
3509 #define MSR_IA32_MC18_STATUS 0x00000449
3510 #define MSR_IA32_MC19_STATUS 0x0000044D
3511 #define MSR_IA32_MC20_STATUS 0x00000451
3512 #define MSR_IA32_MC21_STATUS 0x00000455
3513 #define MSR_IA32_MC22_STATUS 0x00000459
3514 #define MSR_IA32_MC23_STATUS 0x0000045D
3515 #define MSR_IA32_MC24_STATUS 0x00000461
3516 #define MSR_IA32_MC25_STATUS 0x00000465
3517 #define MSR_IA32_MC26_STATUS 0x00000469
3518 #define MSR_IA32_MC27_STATUS 0x0000046D
3519 #define MSR_IA32_MC28_STATUS 0x00000471
3523 MCn_ADDR. If IA32_MCG_CAP.CNT > n.
3525 @param ECX MSR_IA32_MCn_ADDR
3526 @param EAX Lower 32-bits of MSR value.
3527 @param EDX Upper 32-bits of MSR value.
3529 <b>Example usage</b>
3533 Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
3534 AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);
3536 @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.
3537 MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.
3538 MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.
3539 MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.
3540 MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.
3541 MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.
3542 MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.
3543 MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.
3544 MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.
3545 MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.
3546 MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.
3547 MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.
3548 MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.
3549 MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.
3550 MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.
3551 MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.
3552 MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.
3553 MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.
3554 MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.
3555 MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.
3556 MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.
3557 MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.
3558 MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.
3559 MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.
3560 MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.
3561 MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.
3562 MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.
3563 MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.
3564 MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.
3567 #define MSR_IA32_MC0_ADDR 0x00000402
3568 #define MSR_IA32_MC1_ADDR 0x00000406
3569 #define MSR_IA32_MC2_ADDR 0x0000040A
3570 #define MSR_IA32_MC3_ADDR 0x0000040E
3571 #define MSR_IA32_MC4_ADDR 0x00000412
3572 #define MSR_IA32_MC5_ADDR 0x00000416
3573 #define MSR_IA32_MC6_ADDR 0x0000041A
3574 #define MSR_IA32_MC7_ADDR 0x0000041E
3575 #define MSR_IA32_MC8_ADDR 0x00000422
3576 #define MSR_IA32_MC9_ADDR 0x00000426
3577 #define MSR_IA32_MC10_ADDR 0x0000042A
3578 #define MSR_IA32_MC11_ADDR 0x0000042E
3579 #define MSR_IA32_MC12_ADDR 0x00000432
3580 #define MSR_IA32_MC13_ADDR 0x00000436
3581 #define MSR_IA32_MC14_ADDR 0x0000043A
3582 #define MSR_IA32_MC15_ADDR 0x0000043E
3583 #define MSR_IA32_MC16_ADDR 0x00000442
3584 #define MSR_IA32_MC17_ADDR 0x00000446
3585 #define MSR_IA32_MC18_ADDR 0x0000044A
3586 #define MSR_IA32_MC19_ADDR 0x0000044E
3587 #define MSR_IA32_MC20_ADDR 0x00000452
3588 #define MSR_IA32_MC21_ADDR 0x00000456
3589 #define MSR_IA32_MC22_ADDR 0x0000045A
3590 #define MSR_IA32_MC23_ADDR 0x0000045E
3591 #define MSR_IA32_MC24_ADDR 0x00000462
3592 #define MSR_IA32_MC25_ADDR 0x00000466
3593 #define MSR_IA32_MC26_ADDR 0x0000046A
3594 #define MSR_IA32_MC27_ADDR 0x0000046E
3595 #define MSR_IA32_MC28_ADDR 0x00000472
3599 MCn_MISC. If IA32_MCG_CAP.CNT > n.
3601 @param ECX MSR_IA32_MCn_MISC
3602 @param EAX Lower 32-bits of MSR value.
3603 @param EDX Upper 32-bits of MSR value.
3605 <b>Example usage</b>
3609 Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
3610 AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);
3612 @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.
3613 MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.
3614 MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.
3615 MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.
3616 MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.
3617 MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.
3618 MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
3619 MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.
3620 MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.
3621 MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.
3622 MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.
3623 MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.
3624 MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.
3625 MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.
3626 MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.
3627 MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.
3628 MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.
3629 MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.
3630 MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.
3631 MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.
3632 MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.
3633 MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.
3634 MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.
3635 MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.
3636 MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.
3637 MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.
3638 MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.
3639 MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.
3640 MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.
3643 #define MSR_IA32_MC0_MISC 0x00000403
3644 #define MSR_IA32_MC1_MISC 0x00000407
3645 #define MSR_IA32_MC2_MISC 0x0000040B
3646 #define MSR_IA32_MC3_MISC 0x0000040F
3647 #define MSR_IA32_MC4_MISC 0x00000413
3648 #define MSR_IA32_MC5_MISC 0x00000417
3649 #define MSR_IA32_MC6_MISC 0x0000041B
3650 #define MSR_IA32_MC7_MISC 0x0000041F
3651 #define MSR_IA32_MC8_MISC 0x00000423
3652 #define MSR_IA32_MC9_MISC 0x00000427
3653 #define MSR_IA32_MC10_MISC 0x0000042B
3654 #define MSR_IA32_MC11_MISC 0x0000042F
3655 #define MSR_IA32_MC12_MISC 0x00000433
3656 #define MSR_IA32_MC13_MISC 0x00000437
3657 #define MSR_IA32_MC14_MISC 0x0000043B
3658 #define MSR_IA32_MC15_MISC 0x0000043F
3659 #define MSR_IA32_MC16_MISC 0x00000443
3660 #define MSR_IA32_MC17_MISC 0x00000447
3661 #define MSR_IA32_MC18_MISC 0x0000044B
3662 #define MSR_IA32_MC19_MISC 0x0000044F
3663 #define MSR_IA32_MC20_MISC 0x00000453
3664 #define MSR_IA32_MC21_MISC 0x00000457
3665 #define MSR_IA32_MC22_MISC 0x0000045B
3666 #define MSR_IA32_MC23_MISC 0x0000045F
3667 #define MSR_IA32_MC24_MISC 0x00000463
3668 #define MSR_IA32_MC25_MISC 0x00000467
3669 #define MSR_IA32_MC26_MISC 0x0000046B
3670 #define MSR_IA32_MC27_MISC 0x0000046F
3671 #define MSR_IA32_MC28_MISC 0x00000473
3675 Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic
3676 VMX Information.". If CPUID.01H:ECX.[5] = 1.
3678 @param ECX MSR_IA32_VMX_BASIC (0x00000480)
3679 @param EAX Lower 32-bits of MSR value.
3680 @param EDX Upper 32-bits of MSR value.
3682 <b>Example usage</b>
3684 MSR_IA32_VMX_BASIC_REGISTER Msr;
3686 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
3688 @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
3690 #define MSR_IA32_VMX_BASIC 0x00000480
3693 MSR information returned for MSR index #MSR_IA32_VMX_BASIC
3697 /// Individual bit fields
3701 /// [Bits 30:0] VMCS revision identifier used by the processor. Processors
3702 /// that use the same VMCS revision identifier use the same size for VMCS
3703 /// regions (see subsequent item on bits 44:32).
3705 /// @note Earlier versions of this manual specified that the VMCS revision
3706 /// identifier was a 32-bit field in bits 31:0 of this MSR. For all
3707 /// processors produced prior to this change, bit 31 of this MSR was read
3710 UINT32 VmcsRevisonId
: 31;
3711 UINT32 MustBeZero
: 1;
3713 /// [Bit 44:32] Reports the number of bytes that software should allocate
3714 /// for the VMXON region and any VMCS region. It is a value greater than
3715 /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).
3717 UINT32 VmcsSize
: 13;
3718 UINT32 Reserved1
: 3;
3720 /// [Bit 48] Indicates the width of the physical addresses that may be used
3721 /// for the VMXON region, each VMCS, and data structures referenced by
3722 /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX
3723 /// transitions). If the bit is 0, these addresses are limited to the
3724 /// processor's physical-address width. If the bit is 1, these addresses
3725 /// are limited to 32 bits. This bit is always 0 for processors that
3726 /// support Intel 64 architecture.
3728 /// @note On processors that support Intel 64 architecture, the pointer
3729 /// must not set bits beyond the processor's physical address width.
3731 UINT32 VmcsAddressWidth
: 1;
3733 /// [Bit 49] If bit 49 is read as 1, the logical processor supports the
3734 /// dual-monitor treatment of system-management interrupts and
3735 /// system-management mode. See Section 34.15 for details of this treatment.
3737 UINT32 DualMonitor
: 1;
3739 /// [Bit 53:50] report the memory type that should be used for the VMCS,
3740 /// for data structures referenced by pointers in the VMCS (I/O bitmaps,
3741 /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG
3742 /// header. If software needs to access these data structures (e.g., to
3743 /// modify the contents of the MSR bitmaps), it can configure the paging
3744 /// structures to map them into the linear-address space. If it does so,
3745 /// it should establish mappings that use the memory type reported bits
3746 /// 53:50 in this MSR.
3748 /// As of this writing, all processors that support VMX operation indicate
3749 /// the write-back type.
3751 /// If software needs to access these data structures (e.g., to modify
3752 /// the contents of the MSR bitmaps), it can configure the paging
3753 /// structures to map them into the linear-address space. If it does so,
3754 /// it should establish mappings that use the memory type reported in this
3757 /// @note Alternatively, software may map any of these regions or
3758 /// structures with the UC memory type. (This may be necessary for the MSEG
3759 /// header.) Doing so is discouraged unless necessary as it will cause the
3760 /// performance of software accesses to those structures to suffer.
3763 UINT32 MemoryType
: 4;
3765 /// [Bit 54] If bit 54 is read as 1, the processor reports information in
3766 /// the VM-exit instruction-information field on VM exitsdue to execution
3767 /// of the INS and OUTS instructions (see Section 27.2.4). This reporting
3768 /// is done only if this bit is read as 1.
3770 UINT32 InsOutsReporting
: 1;
3772 /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may
3773 /// be cleared to 0. See Appendix A.2 for details. It also reports support
3774 /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,
3775 /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and
3776 /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,
3777 /// Appendix A.4, and Appendix A.5 for details.
3779 UINT32 VmxControls
: 1;
3780 UINT32 Reserved2
: 8;
3783 /// All bit fields as a 64-bit value
3786 } MSR_IA32_VMX_BASIC_REGISTER
;
3789 /// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType
3791 #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00
3792 #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06
3798 Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
3799 Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.
3801 @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)
3802 @param EAX Lower 32-bits of MSR value.
3803 @param EDX Upper 32-bits of MSR value.
3805 <b>Example usage</b>
3809 Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);
3811 @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.
3813 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
3816 Capability Reporting Register of Primary Processor-based VM-execution
3817 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
3818 Controls.". If CPUID.01H:ECX.[5] = 1.
3820 @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)
3821 @param EAX Lower 32-bits of MSR value.
3822 @param EDX Upper 32-bits of MSR value.
3824 <b>Example usage</b>
3828 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);
3830 @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.
3832 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
3835 Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,
3836 "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.
3838 @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)
3839 @param EAX Lower 32-bits of MSR value.
3840 @param EDX Upper 32-bits of MSR value.
3842 <b>Example usage</b>
3846 Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);
3848 @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.
3850 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
3853 Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,
3854 "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.
3856 @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)
3857 @param EAX Lower 32-bits of MSR value.
3858 @param EDX Upper 32-bits of MSR value.
3860 <b>Example usage</b>
3864 Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);
3866 @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.
3868 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
3871 Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,
3872 "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.
3874 @param ECX MSR_IA32_VMX_MISC (0x00000485)
3875 @param EAX Lower 32-bits of MSR value.
3876 @param EDX Upper 32-bits of MSR value.
3878 <b>Example usage</b>
3880 IA32_VMX_MISC_REGISTER Msr;
3882 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);
3884 @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.
3886 #define MSR_IA32_VMX_MISC 0x00000485
3889 MSR information returned for MSR index #IA32_VMX_MISC
3893 /// Individual bit fields
3897 /// [Bits 4:0] Reports a value X that specifies the relationship between the
3898 /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).
3899 /// Specifically, the VMX-preemption timer (if it is active) counts down by
3900 /// 1 every time bit X in the TSC changes due to a TSC increment.
3902 UINT32 VmxTimerRatio
: 5;
3904 /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA
3905 /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more
3906 /// details. This bit is read as 1 on any logical processor that supports
3907 /// the 1-setting of the "unrestricted guest" VM-execution control.
3909 UINT32 VmExitEferLma
: 1;
3911 /// [Bit 6] reports (if set) the support for activity state 1 (HLT).
3913 UINT32 HltActivityStateSupported
: 1;
3915 /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).
3917 UINT32 ShutdownActivityStateSupported
: 1;
3919 /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).
3921 UINT32 WaitForSipiActivityStateSupported
: 1;
3922 UINT32 Reserved1
: 5;
3924 /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used
3925 /// in VMX operation. If the processor supports Intel PT but does not allow
3926 /// it to be used in VMX operation, execution of VMXON clears
3927 /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);
3928 /// any attempt to set that bit while in VMX operation (including VMX root
3929 /// operation) using the WRMSR instruction causes a general-protection
3932 UINT32 ProcessorTraceSupported
: 1;
3934 /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-
3935 /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).
3936 /// See Section 34.15.6.3.
3938 UINT32 SmBaseMsrSupported
: 1;
3940 /// [Bits 24:16] Indicate the number of CR3-target values supported by the
3941 /// processor. This number is a value between 0 and 256, inclusive (bit 24
3942 /// is set if and only if bits 23:16 are clear).
3944 UINT32 NumberOfCr3TargetValues
: 9;
3946 /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum
3947 /// number of MSRs that should appear in the VM-exit MSR-store list, the
3948 /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if
3949 /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the
3950 /// recommended maximum number of MSRs to be included in each list. If the
3951 /// limit is exceeded, undefined processor behavior may result (including a
3952 /// machine check during the VMX transition).
3954 UINT32 MsrStoreListMaximum
: 3;
3956 /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set
3957 /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1
3958 /// (see Section 34.14.4).
3960 UINT32 BlockSmiSupported
: 1;
3962 /// [Bit 29] read as 1, software can use VMWRITE to write to any supported
3963 /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit
3964 /// information fields.
3966 UINT32 VmWriteSupported
: 1;
3968 /// [Bit 30] If read as 1, VM entry allows injection of a software
3969 /// interrupt, software exception, or privileged software exception with an
3970 /// instruction length of 0.
3972 UINT32 VmInjectSupported
: 1;
3973 UINT32 Reserved2
: 1;
3975 /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the
3978 UINT32 MsegRevisionIdentifier
: 32;
3981 /// All bit fields as a 64-bit value
3984 } IA32_VMX_MISC_REGISTER
;
3987 Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
3988 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
3990 @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)
3991 @param EAX Lower 32-bits of MSR value.
3992 @param EDX Upper 32-bits of MSR value.
3994 <b>Example usage</b>
3998 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);
4000 @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.
4002 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
4005 Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,
4006 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
4008 @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)
4009 @param EAX Lower 32-bits of MSR value.
4010 @param EDX Upper 32-bits of MSR value.
4012 <b>Example usage</b>
4016 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);
4018 @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.
4020 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
4023 Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,
4024 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
4026 @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)
4027 @param EAX Lower 32-bits of MSR value.
4028 @param EDX Upper 32-bits of MSR value.
4030 <b>Example usage</b>
4034 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);
4036 @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.
4038 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
4041 Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,
4042 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
4044 @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)
4045 @param EAX Lower 32-bits of MSR value.
4046 @param EDX Upper 32-bits of MSR value.
4048 <b>Example usage</b>
4052 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);
4054 @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.
4056 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
4059 Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix
4060 A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.
4062 @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)
4063 @param EAX Lower 32-bits of MSR value.
4064 @param EDX Upper 32-bits of MSR value.
4066 <b>Example usage</b>
4070 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);
4072 @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.
4074 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
4077 Capability Reporting Register of Secondary Processor-based VM-execution
4078 Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution
4079 Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).
4081 @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)
4082 @param EAX Lower 32-bits of MSR value.
4083 @param EDX Upper 32-bits of MSR value.
4085 <b>Example usage</b>
4089 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);
4091 @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.
4093 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
4096 Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,
4097 "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C
4098 TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).
4100 @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)
4101 @param EAX Lower 32-bits of MSR value.
4102 @param EDX Upper 32-bits of MSR value.
4104 <b>Example usage</b>
4108 Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);
4110 @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.
4112 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
4115 Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
4116 See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (
4117 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4119 @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)
4120 @param EAX Lower 32-bits of MSR value.
4121 @param EDX Upper 32-bits of MSR value.
4123 <b>Example usage</b>
4127 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);
4129 @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.
4131 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
4134 Capability Reporting Register of Primary Processor-based VM-execution Flex
4135 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
4136 Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4138 @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)
4139 @param EAX Lower 32-bits of MSR value.
4140 @param EDX Upper 32-bits of MSR value.
4142 <b>Example usage</b>
4146 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
4148 @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.
4150 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
4153 Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix
4154 A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4156 @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)
4157 @param EAX Lower 32-bits of MSR value.
4158 @param EDX Upper 32-bits of MSR value.
4160 <b>Example usage</b>
4164 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);
4166 @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.
4168 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
4171 Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix
4172 A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4174 @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)
4175 @param EAX Lower 32-bits of MSR value.
4176 @param EDX Upper 32-bits of MSR value.
4178 <b>Example usage</b>
4182 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);
4184 @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.
4186 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
4189 Capability Reporting Register of VMfunction Controls (R/O). If(
4190 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4192 @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)
4193 @param EAX Lower 32-bits of MSR value.
4194 @param EDX Upper 32-bits of MSR value.
4196 <b>Example usage</b>
4200 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);
4202 @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.
4204 #define MSR_IA32_VMX_VMFUNC 0x00000491
4207 Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&
4208 IA32_PERF_CAPABILITIES[ 13] = 1.
4210 @param ECX MSR_IA32_A_PMCn
4211 @param EAX Lower 32-bits of MSR value.
4212 @param EDX Upper 32-bits of MSR value.
4214 <b>Example usage</b>
4218 Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
4219 AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);
4221 @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.
4222 MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.
4223 MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.
4224 MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.
4225 MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.
4226 MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.
4227 MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.
4228 MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.
4231 #define MSR_IA32_A_PMC0 0x000004C1
4232 #define MSR_IA32_A_PMC1 0x000004C2
4233 #define MSR_IA32_A_PMC2 0x000004C3
4234 #define MSR_IA32_A_PMC3 0x000004C4
4235 #define MSR_IA32_A_PMC4 0x000004C5
4236 #define MSR_IA32_A_PMC5 0x000004C6
4237 #define MSR_IA32_A_PMC6 0x000004C7
4238 #define MSR_IA32_A_PMC7 0x000004C8
4242 (R/W). If IA32_MCG_CAP.LMCE_P =1.
4244 @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)
4245 @param EAX Lower 32-bits of MSR value.
4246 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
4247 @param EDX Upper 32-bits of MSR value.
4248 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
4250 <b>Example usage</b>
4252 MSR_IA32_MCG_EXT_CTL_REGISTER Msr;
4254 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
4255 AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);
4257 @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.
4259 #define MSR_IA32_MCG_EXT_CTL 0x000004D0
4262 MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL
4266 /// Individual bit fields
4270 /// [Bit 0] LMCE_EN.
4273 UINT32 Reserved1
: 31;
4274 UINT32 Reserved2
: 32;
4277 /// All bit fields as a 32-bit value
4281 /// All bit fields as a 64-bit value
4284 } MSR_IA32_MCG_EXT_CTL_REGISTER
;
4287 Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,
4288 ECX=0H): EBX[2] = 1.
4290 @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)
4291 @param EAX Lower 32-bits of MSR value.
4292 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
4293 @param EDX Upper 32-bits of MSR value.
4294 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
4296 <b>Example usage</b>
4298 MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;
4300 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);
4302 @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.
4304 #define MSR_IA32_SGX_SVN_STATUS 0x00000500
4307 MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS
4311 /// Individual bit fields
4315 /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated
4316 /// Code Modules (ACMs)".
4319 UINT32 Reserved1
: 15;
4321 /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with
4322 /// Authenticated Code Modules (ACMs)".
4324 UINT32 SGX_SVN_SINIT
: 8;
4325 UINT32 Reserved2
: 8;
4326 UINT32 Reserved3
: 32;
4329 /// All bit fields as a 32-bit value
4333 /// All bit fields as a 64-bit value
4336 } MSR_IA32_SGX_SVN_STATUS_REGISTER
;
4339 Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
4340 && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)
4343 @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)
4344 @param EAX Lower 32-bits of MSR value.
4345 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
4346 @param EDX Upper 32-bits of MSR value.
4347 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
4349 <b>Example usage</b>
4351 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;
4353 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
4354 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);
4356 @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.
4358 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
4361 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE
4365 /// Individual bit fields
4368 UINT32 Reserved
: 7;
4370 /// [Bits 31:7] Base physical address.
4374 /// [Bits 63:32] Base physical address.
4379 /// All bit fields as a 64-bit value
4382 } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER
;
4385 Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,
4386 ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)
4387 (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).
4389 @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)
4390 @param EAX Lower 32-bits of MSR value.
4391 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
4392 @param EDX Upper 32-bits of MSR value.
4393 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
4395 <b>Example usage</b>
4397 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;
4399 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
4400 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);
4402 @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.
4404 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
4407 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS
4411 /// Individual bit fields
4414 UINT32 Reserved
: 7;
4416 /// [Bits 31:7] MaskOrTableOffset.
4418 UINT32 MaskOrTableOffset
: 25;
4420 /// [Bits 63:32] Output Offset.
4422 UINT32 OutputOffset
: 32;
4425 /// All bit fields as a 64-bit value
4428 } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
;
4431 Format of ToPA table entries.
4435 /// Individual bit fields
4439 /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4442 UINT32 Reserved1
: 1;
4444 /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4447 UINT32 Reserved2
: 1;
4449 /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4452 UINT32 Reserved3
: 1;
4454 /// [Bit 6:9] Indicates the size of the associated output region. See Section
4455 /// 35.2.6.2, "Table of Physical Addresses (ToPA)".
4458 UINT32 Reserved4
: 2;
4460 /// [Bit 12:31] Output Region Base Physical Address low part.
4461 /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.
4462 /// ATTENTION: The size of the address field is determined by the processor's
4463 /// physical-address width (MAXPHYADDR) in bits, as reported in
4464 /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.
4465 /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
4466 /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4470 /// [Bit 32:63] Output Region Base Physical Address high part.
4471 /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.
4472 /// ATTENTION: The size of the address field is determined by the processor's
4473 /// physical-address width (MAXPHYADDR) in bits, as reported in
4474 /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.
4475 /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
4476 /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4481 /// All bit fields as a 64-bit value
4484 } RTIT_TOPA_TABLE_ENTRY
;
4487 /// The size of the associated output region usd by Topa.
4490 RtitTopaMemorySize4K
= 0,
4491 RtitTopaMemorySize8K
,
4492 RtitTopaMemorySize16K
,
4493 RtitTopaMemorySize32K
,
4494 RtitTopaMemorySize64K
,
4495 RtitTopaMemorySize128K
,
4496 RtitTopaMemorySize256K
,
4497 RtitTopaMemorySize512K
,
4498 RtitTopaMemorySize1M
,
4499 RtitTopaMemorySize2M
,
4500 RtitTopaMemorySize4M
,
4501 RtitTopaMemorySize8M
,
4502 RtitTopaMemorySize16M
,
4503 RtitTopaMemorySize32M
,
4504 RtitTopaMemorySize64M
,
4505 RtitTopaMemorySize128M
4506 } RTIT_TOPA_MEMORY_SIZE
;
4509 Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4511 @param ECX MSR_IA32_RTIT_CTL (0x00000570)
4512 @param EAX Lower 32-bits of MSR value.
4513 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
4514 @param EDX Upper 32-bits of MSR value.
4515 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
4517 <b>Example usage</b>
4519 MSR_IA32_RTIT_CTL_REGISTER Msr;
4521 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
4522 AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);
4524 @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
4526 #define MSR_IA32_RTIT_CTL 0x00000570
4529 MSR information returned for MSR index #MSR_IA32_RTIT_CTL
4533 /// Individual bit fields
4537 /// [Bit 0] TraceEn.
4541 /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4553 /// [Bit 4] PwrEvtEn.
4555 UINT32 PwrEvtEn
: 1;
4557 /// [Bit 5] FUPonPTW.
4559 UINT32 FUPonPTW
: 1;
4561 /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
4563 UINT32 FabricEn
: 1;
4565 /// [Bit 7] CR3 filter.
4573 /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4581 /// [Bit 11] DisRETC.
4589 /// [Bit 13] BranchEn.
4591 UINT32 BranchEn
: 1;
4593 /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4596 UINT32 Reserved3
: 1;
4598 /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4600 UINT32 CYCThresh
: 4;
4601 UINT32 Reserved4
: 1;
4603 /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4606 UINT32 Reserved5
: 4;
4608 /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
4610 UINT32 ADDR0_CFG
: 4;
4612 /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).
4614 UINT32 ADDR1_CFG
: 4;
4616 /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).
4618 UINT32 ADDR2_CFG
: 4;
4620 /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
4622 UINT32 ADDR3_CFG
: 4;
4623 UINT32 Reserved6
: 16;
4626 /// All bit fields as a 64-bit value
4629 } MSR_IA32_RTIT_CTL_REGISTER
;
4632 Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4634 @param ECX MSR_IA32_RTIT_STATUS (0x00000571)
4635 @param EAX Lower 32-bits of MSR value.
4636 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4637 @param EDX Upper 32-bits of MSR value.
4638 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4640 <b>Example usage</b>
4642 MSR_IA32_RTIT_STATUS_REGISTER Msr;
4644 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
4645 AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);
4647 @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.
4649 #define MSR_IA32_RTIT_STATUS 0x00000571
4652 MSR information returned for MSR index #MSR_IA32_RTIT_STATUS
4656 /// Individual bit fields
4660 /// [Bit 0] FilterEn, (writes ignored).
4661 /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).
4663 UINT32 FilterEn
: 1;
4665 /// [Bit 1] ContexEn, (writes ignored).
4667 UINT32 ContexEn
: 1;
4669 /// [Bit 2] TriggerEn, (writes ignored).
4671 UINT32 TriggerEn
: 1;
4672 UINT32 Reserved1
: 1;
4678 /// [Bit 5] Stopped.
4681 UINT32 Reserved2
: 26;
4683 /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).
4685 UINT32 PacketByteCnt
: 17;
4686 UINT32 Reserved3
: 15;
4689 /// All bit fields as a 64-bit value
4692 } MSR_IA32_RTIT_STATUS_REGISTER
;
4695 Trace Filter CR3 Match Register (R/W).
4696 If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4698 @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)
4699 @param EAX Lower 32-bits of MSR value.
4700 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4701 @param EDX Upper 32-bits of MSR value.
4702 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4704 <b>Example usage</b>
4706 MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;
4708 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);
4709 AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);
4711 @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.
4713 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
4716 MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH
4720 /// Individual bit fields
4723 UINT32 Reserved
: 5;
4725 /// [Bits 31:5] CR3[63:5] value to match.
4729 /// [Bits 63:32] CR3[63:5] value to match.
4734 /// All bit fields as a 64-bit value
4737 } MSR_IA32_RTIT_CR3_MATCH_REGISTER
;
4740 Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4742 @param ECX MSR_IA32_RTIT_ADDRn_A
4743 @param EAX Lower 32-bits of MSR value.
4744 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4745 @param EDX Upper 32-bits of MSR value.
4746 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4748 <b>Example usage</b>
4750 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4752 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
4753 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);
4755 @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.
4756 MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.
4757 MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.
4758 MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.
4761 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
4762 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
4763 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
4764 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
4768 Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4770 @param ECX MSR_IA32_RTIT_ADDRn_B
4771 @param EAX Lower 32-bits of MSR value.
4772 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4773 @param EDX Upper 32-bits of MSR value.
4774 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4776 <b>Example usage</b>
4778 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4780 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
4781 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);
4783 @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.
4784 MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.
4785 MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.
4786 MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.
4789 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
4790 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
4791 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
4792 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
4796 MSR information returned for MSR indexes
4797 #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and
4798 #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B
4802 /// Individual bit fields
4806 /// [Bits 31:0] Virtual Address.
4808 UINT32 VirtualAddress
: 32;
4810 /// [Bits 47:32] Virtual Address.
4812 UINT32 VirtualAddressHi
: 16;
4814 /// [Bits 63:48] SignExt_VA.
4816 UINT32 SignExt_VA
: 16;
4819 /// All bit fields as a 64-bit value
4822 } MSR_IA32_RTIT_ADDR_REGISTER
;
4825 DS Save Area (R/W) Points to the linear address of the first byte of the DS
4826 buffer management area, which is used to manage the BTS and PEBS buffers.
4827 See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(
4828 CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS
4829 buffer management area, if IA-32e mode is active.
4831 @param ECX MSR_IA32_DS_AREA (0x00000600)
4832 @param EAX Lower 32-bits of MSR value.
4833 Described by the type MSR_IA32_DS_AREA_REGISTER.
4834 @param EDX Upper 32-bits of MSR value.
4835 Described by the type MSR_IA32_DS_AREA_REGISTER.
4837 <b>Example usage</b>
4841 Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);
4842 AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);
4844 @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.
4846 #define MSR_IA32_DS_AREA 0x00000600
4849 TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =
4852 @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)
4853 @param EAX Lower 32-bits of MSR value.
4854 @param EDX Upper 32-bits of MSR value.
4856 <b>Example usage</b>
4860 Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);
4861 AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);
4863 @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.
4865 #define MSR_IA32_TSC_DEADLINE 0x000006E0
4868 Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.
4870 @param ECX MSR_IA32_PM_ENABLE (0x00000770)
4871 @param EAX Lower 32-bits of MSR value.
4872 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4873 @param EDX Upper 32-bits of MSR value.
4874 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4876 <b>Example usage</b>
4878 MSR_IA32_PM_ENABLE_REGISTER Msr;
4880 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);
4881 AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);
4883 @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.
4885 #define MSR_IA32_PM_ENABLE 0x00000770
4888 MSR information returned for MSR index #MSR_IA32_PM_ENABLE
4892 /// Individual bit fields
4896 /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If
4897 /// CPUID.06H:EAX.[7] = 1.
4899 UINT32 HWP_ENABLE
: 1;
4900 UINT32 Reserved1
: 31;
4901 UINT32 Reserved2
: 32;
4904 /// All bit fields as a 32-bit value
4908 /// All bit fields as a 64-bit value
4911 } MSR_IA32_PM_ENABLE_REGISTER
;
4914 HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.
4916 @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)
4917 @param EAX Lower 32-bits of MSR value.
4918 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
4919 @param EDX Upper 32-bits of MSR value.
4920 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
4922 <b>Example usage</b>
4924 MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;
4926 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);
4928 @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.
4930 #define MSR_IA32_HWP_CAPABILITIES 0x00000771
4933 MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES
4937 /// Individual bit fields
4941 /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance
4942 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4944 UINT32 Highest_Performance
: 8;
4946 /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP
4947 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4949 UINT32 Guaranteed_Performance
: 8;
4951 /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP
4952 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4954 UINT32 Most_Efficient_Performance
: 8;
4956 /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance
4957 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
4959 UINT32 Lowest_Performance
: 8;
4960 UINT32 Reserved
: 32;
4963 /// All bit fields as a 32-bit value
4967 /// All bit fields as a 64-bit value
4970 } MSR_IA32_HWP_CAPABILITIES_REGISTER
;
4973 Power Management Control Hints for All Logical Processors in a Package
4974 (R/W). If CPUID.06H:EAX.[11] = 1.
4976 @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)
4977 @param EAX Lower 32-bits of MSR value.
4978 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
4979 @param EDX Upper 32-bits of MSR value.
4980 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
4982 <b>Example usage</b>
4984 MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;
4986 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);
4987 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);
4989 @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.
4991 #define MSR_IA32_HWP_REQUEST_PKG 0x00000772
4994 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG
4998 /// Individual bit fields
5002 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
5003 /// CPUID.06H:EAX.[11] = 1.
5005 UINT32 Minimum_Performance
: 8;
5007 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
5008 /// CPUID.06H:EAX.[11] = 1.
5010 UINT32 Maximum_Performance
: 8;
5012 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
5013 /// If CPUID.06H:EAX.[11] = 1.
5015 UINT32 Desired_Performance
: 8;
5017 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
5018 /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
5020 UINT32 Energy_Performance_Preference
: 8;
5022 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
5023 /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
5025 UINT32 Activity_Window
: 10;
5026 UINT32 Reserved
: 22;
5029 /// All bit fields as a 64-bit value
5032 } MSR_IA32_HWP_REQUEST_PKG_REGISTER
;
5035 Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.
5037 @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)
5038 @param EAX Lower 32-bits of MSR value.
5039 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
5040 @param EDX Upper 32-bits of MSR value.
5041 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
5043 <b>Example usage</b>
5045 MSR_IA32_HWP_INTERRUPT_REGISTER Msr;
5047 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);
5048 AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);
5050 @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.
5052 #define MSR_IA32_HWP_INTERRUPT 0x00000773
5055 MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT
5059 /// Individual bit fields
5063 /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP
5064 /// Notifications". If CPUID.06H:EAX.[8] = 1.
5066 UINT32 EN_Guaranteed_Performance_Change
: 1;
5068 /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".
5069 /// If CPUID.06H:EAX.[8] = 1.
5071 UINT32 EN_Excursion_Minimum
: 1;
5072 UINT32 Reserved1
: 30;
5073 UINT32 Reserved2
: 32;
5076 /// All bit fields as a 32-bit value
5080 /// All bit fields as a 64-bit value
5083 } MSR_IA32_HWP_INTERRUPT_REGISTER
;
5086 Power Management Control Hints to a Logical Processor (R/W). If
5087 CPUID.06H:EAX.[7] = 1.
5089 @param ECX MSR_IA32_HWP_REQUEST (0x00000774)
5090 @param EAX Lower 32-bits of MSR value.
5091 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
5092 @param EDX Upper 32-bits of MSR value.
5093 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
5095 <b>Example usage</b>
5097 MSR_IA32_HWP_REQUEST_REGISTER Msr;
5099 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);
5100 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);
5102 @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.
5104 #define MSR_IA32_HWP_REQUEST 0x00000774
5107 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST
5111 /// Individual bit fields
5115 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
5116 /// CPUID.06H:EAX.[7] = 1.
5118 UINT32 Minimum_Performance
: 8;
5120 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
5121 /// CPUID.06H:EAX.[7] = 1.
5123 UINT32 Maximum_Performance
: 8;
5125 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
5126 /// If CPUID.06H:EAX.[7] = 1.
5128 UINT32 Desired_Performance
: 8;
5130 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
5131 /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.
5133 UINT32 Energy_Performance_Preference
: 8;
5135 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
5136 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.
5138 UINT32 Activity_Window
: 10;
5140 /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If
5141 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.
5143 UINT32 Package_Control
: 1;
5144 UINT32 Reserved
: 21;
5147 /// All bit fields as a 64-bit value
5150 } MSR_IA32_HWP_REQUEST_REGISTER
;
5153 Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If
5154 CPUID.06H:EAX.[7] = 1.
5156 @param ECX MSR_IA32_HWP_STATUS (0x00000777)
5157 @param EAX Lower 32-bits of MSR value.
5158 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
5159 @param EDX Upper 32-bits of MSR value.
5160 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
5162 <b>Example usage</b>
5164 MSR_IA32_HWP_STATUS_REGISTER Msr;
5166 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);
5167 AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);
5169 @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.
5171 #define MSR_IA32_HWP_STATUS 0x00000777
5174 MSR information returned for MSR index #MSR_IA32_HWP_STATUS
5178 /// Individual bit fields
5182 /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,
5183 /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
5185 UINT32 Guaranteed_Performance_Change
: 1;
5186 UINT32 Reserved1
: 1;
5188 /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP
5189 /// Feedback". If CPUID.06H:EAX.[7] = 1.
5191 UINT32 Excursion_To_Minimum
: 1;
5192 UINT32 Reserved2
: 29;
5193 UINT32 Reserved3
: 32;
5196 /// All bit fields as a 32-bit value
5200 /// All bit fields as a 64-bit value
5203 } MSR_IA32_HWP_STATUS_REGISTER
;
5206 x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1
5207 && IA32_APIC_BASE.[10] = 1.
5209 @param ECX MSR_IA32_X2APIC_APICID (0x00000802)
5210 @param EAX Lower 32-bits of MSR value.
5211 @param EDX Upper 32-bits of MSR value.
5213 <b>Example usage</b>
5217 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);
5219 @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.
5221 #define MSR_IA32_X2APIC_APICID 0x00000802
5224 x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5225 IA32_APIC_BASE.[10] = 1.
5227 @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)
5228 @param EAX Lower 32-bits of MSR value.
5229 @param EDX Upper 32-bits of MSR value.
5231 <b>Example usage</b>
5235 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);
5237 @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.
5239 #define MSR_IA32_X2APIC_VERSION 0x00000803
5242 x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5243 IA32_APIC_BASE.[10] = 1.
5245 @param ECX MSR_IA32_X2APIC_TPR (0x00000808)
5246 @param EAX Lower 32-bits of MSR value.
5247 @param EDX Upper 32-bits of MSR value.
5249 <b>Example usage</b>
5253 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);
5254 AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);
5256 @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.
5258 #define MSR_IA32_X2APIC_TPR 0x00000808
5261 x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5262 IA32_APIC_BASE.[10] = 1.
5264 @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)
5265 @param EAX Lower 32-bits of MSR value.
5266 @param EDX Upper 32-bits of MSR value.
5268 <b>Example usage</b>
5272 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);
5274 @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.
5276 #define MSR_IA32_X2APIC_PPR 0x0000080A
5279 x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]
5282 @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)
5283 @param EAX Lower 32-bits of MSR value.
5284 @param EDX Upper 32-bits of MSR value.
5286 <b>Example usage</b>
5291 AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);
5293 @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.
5295 #define MSR_IA32_X2APIC_EOI 0x0000080B
5298 x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5299 IA32_APIC_BASE.[10] = 1.
5301 @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)
5302 @param EAX Lower 32-bits of MSR value.
5303 @param EDX Upper 32-bits of MSR value.
5305 <b>Example usage</b>
5309 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);
5311 @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.
5313 #define MSR_IA32_X2APIC_LDR 0x0000080D
5316 x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1
5317 && IA32_APIC_BASE.[10] = 1.
5319 @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)
5320 @param EAX Lower 32-bits of MSR value.
5321 @param EDX Upper 32-bits of MSR value.
5323 <b>Example usage</b>
5327 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);
5328 AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);
5330 @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.
5332 #define MSR_IA32_X2APIC_SIVR 0x0000080F
5335 x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).
5336 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5338 @param ECX MSR_IA32_X2APIC_ISRn
5339 @param EAX Lower 32-bits of MSR value.
5340 @param EDX Upper 32-bits of MSR value.
5342 <b>Example usage</b>
5346 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);
5348 @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.
5349 MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.
5350 MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.
5351 MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.
5352 MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.
5353 MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.
5354 MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.
5355 MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.
5358 #define MSR_IA32_X2APIC_ISR0 0x00000810
5359 #define MSR_IA32_X2APIC_ISR1 0x00000811
5360 #define MSR_IA32_X2APIC_ISR2 0x00000812
5361 #define MSR_IA32_X2APIC_ISR3 0x00000813
5362 #define MSR_IA32_X2APIC_ISR4 0x00000814
5363 #define MSR_IA32_X2APIC_ISR5 0x00000815
5364 #define MSR_IA32_X2APIC_ISR6 0x00000816
5365 #define MSR_IA32_X2APIC_ISR7 0x00000817
5369 x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).
5370 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5372 @param ECX MSR_IA32_X2APIC_TMRn
5373 @param EAX Lower 32-bits of MSR value.
5374 @param EDX Upper 32-bits of MSR value.
5376 <b>Example usage</b>
5380 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);
5382 @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.
5383 MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.
5384 MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.
5385 MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.
5386 MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.
5387 MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.
5388 MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.
5389 MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.
5392 #define MSR_IA32_X2APIC_TMR0 0x00000818
5393 #define MSR_IA32_X2APIC_TMR1 0x00000819
5394 #define MSR_IA32_X2APIC_TMR2 0x0000081A
5395 #define MSR_IA32_X2APIC_TMR3 0x0000081B
5396 #define MSR_IA32_X2APIC_TMR4 0x0000081C
5397 #define MSR_IA32_X2APIC_TMR5 0x0000081D
5398 #define MSR_IA32_X2APIC_TMR6 0x0000081E
5399 #define MSR_IA32_X2APIC_TMR7 0x0000081F
5403 x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).
5404 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5406 @param ECX MSR_IA32_X2APIC_IRRn
5407 @param EAX Lower 32-bits of MSR value.
5408 @param EDX Upper 32-bits of MSR value.
5410 <b>Example usage</b>
5414 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);
5416 @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.
5417 MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.
5418 MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.
5419 MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.
5420 MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.
5421 MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.
5422 MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.
5423 MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.
5426 #define MSR_IA32_X2APIC_IRR0 0x00000820
5427 #define MSR_IA32_X2APIC_IRR1 0x00000821
5428 #define MSR_IA32_X2APIC_IRR2 0x00000822
5429 #define MSR_IA32_X2APIC_IRR3 0x00000823
5430 #define MSR_IA32_X2APIC_IRR4 0x00000824
5431 #define MSR_IA32_X2APIC_IRR5 0x00000825
5432 #define MSR_IA32_X2APIC_IRR6 0x00000826
5433 #define MSR_IA32_X2APIC_IRR7 0x00000827
5437 x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5438 IA32_APIC_BASE.[10] = 1.
5440 @param ECX MSR_IA32_X2APIC_ESR (0x00000828)
5441 @param EAX Lower 32-bits of MSR value.
5442 @param EDX Upper 32-bits of MSR value.
5444 <b>Example usage</b>
5448 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);
5449 AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);
5451 @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.
5453 #define MSR_IA32_X2APIC_ESR 0x00000828
5456 x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If
5457 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5459 @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)
5460 @param EAX Lower 32-bits of MSR value.
5461 @param EDX Upper 32-bits of MSR value.
5463 <b>Example usage</b>
5467 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);
5468 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);
5470 @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.
5472 #define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
5475 x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5476 IA32_APIC_BASE.[10] = 1.
5478 @param ECX MSR_IA32_X2APIC_ICR (0x00000830)
5479 @param EAX Lower 32-bits of MSR value.
5480 @param EDX Upper 32-bits of MSR value.
5482 <b>Example usage</b>
5486 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
5487 AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);
5489 @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.
5491 #define MSR_IA32_X2APIC_ICR 0x00000830
5494 x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5495 IA32_APIC_BASE.[10] = 1.
5497 @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)
5498 @param EAX Lower 32-bits of MSR value.
5499 @param EDX Upper 32-bits of MSR value.
5501 <b>Example usage</b>
5505 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);
5506 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);
5508 @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.
5510 #define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
5513 x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =
5514 1 && IA32_APIC_BASE.[10] = 1.
5516 @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)
5517 @param EAX Lower 32-bits of MSR value.
5518 @param EDX Upper 32-bits of MSR value.
5520 <b>Example usage</b>
5524 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);
5525 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);
5527 @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.
5529 #define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
5532 x2APIC LVT Performance Monitor Interrupt Register (R/W). If
5533 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5535 @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)
5536 @param EAX Lower 32-bits of MSR value.
5537 @param EDX Upper 32-bits of MSR value.
5539 <b>Example usage</b>
5543 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);
5544 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);
5546 @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.
5548 #define MSR_IA32_X2APIC_LVT_PMI 0x00000834
5551 x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5552 IA32_APIC_BASE.[10] = 1.
5554 @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)
5555 @param EAX Lower 32-bits of MSR value.
5556 @param EDX Upper 32-bits of MSR value.
5558 <b>Example usage</b>
5562 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);
5563 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);
5565 @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.
5567 #define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
5570 x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5571 IA32_APIC_BASE.[10] = 1.
5573 @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)
5574 @param EAX Lower 32-bits of MSR value.
5575 @param EDX Upper 32-bits of MSR value.
5577 <b>Example usage</b>
5581 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);
5582 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);
5584 @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.
5586 #define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
5589 x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5590 IA32_APIC_BASE.[10] = 1.
5592 @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)
5593 @param EAX Lower 32-bits of MSR value.
5594 @param EDX Upper 32-bits of MSR value.
5596 <b>Example usage</b>
5600 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);
5601 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);
5603 @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.
5605 #define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
5608 x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5609 IA32_APIC_BASE.[10] = 1.
5611 @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)
5612 @param EAX Lower 32-bits of MSR value.
5613 @param EDX Upper 32-bits of MSR value.
5615 <b>Example usage</b>
5619 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);
5620 AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);
5622 @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.
5624 #define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
5627 x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5628 IA32_APIC_BASE.[10] = 1.
5630 @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)
5631 @param EAX Lower 32-bits of MSR value.
5632 @param EDX Upper 32-bits of MSR value.
5634 <b>Example usage</b>
5638 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);
5640 @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.
5642 #define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
5645 x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5646 IA32_APIC_BASE.[10] = 1.
5648 @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)
5649 @param EAX Lower 32-bits of MSR value.
5650 @param EDX Upper 32-bits of MSR value.
5652 <b>Example usage</b>
5656 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);
5657 AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);
5659 @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.
5661 #define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
5664 x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&
5665 IA32_APIC_BASE.[10] = 1.
5667 @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)
5668 @param EAX Lower 32-bits of MSR value.
5669 @param EDX Upper 32-bits of MSR value.
5671 <b>Example usage</b>
5676 AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);
5678 @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.
5680 #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
5683 Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.
5685 @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)
5686 @param EAX Lower 32-bits of MSR value.
5687 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5688 @param EDX Upper 32-bits of MSR value.
5689 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5691 <b>Example usage</b>
5693 MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;
5695 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
5696 AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);
5698 @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.
5700 #define MSR_IA32_DEBUG_INTERFACE 0x00000C80
5703 MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE
5707 /// Individual bit fields
5711 /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.
5712 /// Default is 0. If CPUID.01H:ECX.[11] = 1.
5715 UINT32 Reserved1
: 29;
5717 /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The
5718 /// lock bit is set automatically on the first SMI assertion even if not
5719 /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.
5723 /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to
5724 /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.
5726 UINT32 DebugOccurred
: 1;
5727 UINT32 Reserved2
: 32;
5730 /// All bit fields as a 32-bit value
5734 /// All bit fields as a 64-bit value
5737 } MSR_IA32_DEBUG_INTERFACE_REGISTER
;
5740 L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).
5742 @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)
5743 @param EAX Lower 32-bits of MSR value.
5744 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5745 @param EDX Upper 32-bits of MSR value.
5746 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5748 <b>Example usage</b>
5750 MSR_IA32_L3_QOS_CFG_REGISTER Msr;
5752 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);
5753 AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);
5755 @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
5757 #define MSR_IA32_L3_QOS_CFG 0x00000C81
5760 MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG
5764 /// Individual bit fields
5768 /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate
5769 /// in Code and Data Prioritization (CDP) mode.
5772 UINT32 Reserved1
: 31;
5773 UINT32 Reserved2
: 32;
5776 /// All bit fields as a 32-bit value
5780 /// All bit fields as a 64-bit value
5783 } MSR_IA32_L3_QOS_CFG_REGISTER
;
5786 L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).
5788 @param ECX MSR_IA32_L2_QOS_CFG (0x00000C82)
5789 @param EAX Lower 32-bits of MSR value.
5790 Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
5791 @param EDX Upper 32-bits of MSR value.
5792 Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
5794 <b>Example usage</b>
5796 MSR_IA32_L2_QOS_CFG_REGISTER Msr;
5798 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);
5799 AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);
5801 @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.
5803 #define MSR_IA32_L2_QOS_CFG 0x00000C82
5806 MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG
5810 /// Individual bit fields
5814 /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate
5815 /// in Code and Data Prioritization (CDP) mode.
5818 UINT32 Reserved1
: 31;
5819 UINT32 Reserved2
: 32;
5822 /// All bit fields as a 32-bit value
5826 /// All bit fields as a 64-bit value
5829 } MSR_IA32_L2_QOS_CFG_REGISTER
;
5832 Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
5835 @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)
5836 @param EAX Lower 32-bits of MSR value.
5837 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5838 @param EDX Upper 32-bits of MSR value.
5839 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5841 <b>Example usage</b>
5843 MSR_IA32_QM_EVTSEL_REGISTER Msr;
5845 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);
5846 AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);
5848 @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
5850 #define MSR_IA32_QM_EVTSEL 0x00000C8D
5853 MSR information returned for MSR index #MSR_IA32_QM_EVTSEL
5857 /// Individual bit fields
5861 /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via
5865 UINT32 Reserved
: 24;
5867 /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to
5868 /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (
5869 /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
5871 UINT32 ResourceMonitoringID
: 32;
5874 /// All bit fields as a 64-bit value
5877 } MSR_IA32_QM_EVTSEL_REGISTER
;
5880 Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1
5883 @param ECX MSR_IA32_QM_CTR (0x00000C8E)
5884 @param EAX Lower 32-bits of MSR value.
5885 Described by the type MSR_IA32_QM_CTR_REGISTER.
5886 @param EDX Upper 32-bits of MSR value.
5887 Described by the type MSR_IA32_QM_CTR_REGISTER.
5889 <b>Example usage</b>
5891 MSR_IA32_QM_CTR_REGISTER Msr;
5893 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);
5895 @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.
5897 #define MSR_IA32_QM_CTR 0x00000C8E
5900 MSR information returned for MSR index #MSR_IA32_QM_CTR
5904 /// Individual bit fields
5908 /// [Bits 31:0] Resource Monitored Data.
5910 UINT32 ResourceMonitoredData
: 32;
5912 /// [Bits 61:32] Resource Monitored Data.
5914 UINT32 ResourceMonitoredDataHi
: 30;
5916 /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not
5917 /// available or not monitored for this resource or RMID.
5919 UINT32 Unavailable
: 1;
5921 /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was
5922 /// written to IA32_PQR_QM_EVTSEL.
5927 /// All bit fields as a 64-bit value
5930 } MSR_IA32_QM_CTR_REGISTER
;
5933 Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]
5934 =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).
5936 @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)
5937 @param EAX Lower 32-bits of MSR value.
5938 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
5939 @param EDX Upper 32-bits of MSR value.
5940 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
5942 <b>Example usage</b>
5944 MSR_IA32_PQR_ASSOC_REGISTER Msr;
5946 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);
5947 AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);
5949 @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
5951 #define MSR_IA32_PQR_ASSOC 0x00000C8F
5954 MSR information returned for MSR index #MSR_IA32_PQR_ASSOC
5958 /// Individual bit fields
5962 /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware
5963 /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`
5964 /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
5966 UINT32 ResourceMonitoringID
: 32;
5968 /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on
5969 /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,
5970 /// ECX=0):EBX.[15] = 1 ).
5975 /// All bit fields as a 64-bit value
5978 } MSR_IA32_PQR_ASSOC_REGISTER
;
5981 Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,
5982 ECX=0H):EBX[14] = 1).
5984 @param ECX MSR_IA32_BNDCFGS (0x00000D90)
5985 @param EAX Lower 32-bits of MSR value.
5986 Described by the type MSR_IA32_BNDCFGS_REGISTER.
5987 @param EDX Upper 32-bits of MSR value.
5988 Described by the type MSR_IA32_BNDCFGS_REGISTER.
5990 <b>Example usage</b>
5992 MSR_IA32_BNDCFGS_REGISTER Msr;
5994 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);
5995 AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);
5997 @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.
5999 #define MSR_IA32_BNDCFGS 0x00000D90
6002 MSR information returned for MSR index #MSR_IA32_BNDCFGS
6006 /// Individual bit fields
6010 /// [Bit 0] EN: Enable Intel MPX in supervisor mode.
6014 /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch
6015 /// instructions in the absence of the BND prefix.
6017 UINT32 BNDPRESERVE
: 1;
6018 UINT32 Reserved
: 10;
6020 /// [Bits 31:12] Base Address of Bound Directory.
6024 /// [Bits 63:32] Base Address of Bound Directory.
6029 /// All bit fields as a 64-bit value
6032 } MSR_IA32_BNDCFGS_REGISTER
;
6035 Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.
6037 @param ECX MSR_IA32_XSS (0x00000DA0)
6038 @param EAX Lower 32-bits of MSR value.
6039 Described by the type MSR_IA32_XSS_REGISTER.
6040 @param EDX Upper 32-bits of MSR value.
6041 Described by the type MSR_IA32_XSS_REGISTER.
6043 <b>Example usage</b>
6045 MSR_IA32_XSS_REGISTER Msr;
6047 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);
6048 AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);
6050 @note MSR_IA32_XSS is defined as IA32_XSS in SDM.
6052 #define MSR_IA32_XSS 0x00000DA0
6055 MSR information returned for MSR index #MSR_IA32_XSS
6059 /// Individual bit fields
6062 UINT32 Reserved1
: 8;
6064 /// [Bit 8] Trace Packet Configuration State (R/W).
6066 UINT32 TracePacketConfigurationState
: 1;
6067 UINT32 Reserved2
: 23;
6068 UINT32 Reserved3
: 32;
6071 /// All bit fields as a 32-bit value
6075 /// All bit fields as a 64-bit value
6078 } MSR_IA32_XSS_REGISTER
;
6081 Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.
6083 @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)
6084 @param EAX Lower 32-bits of MSR value.
6085 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
6086 @param EDX Upper 32-bits of MSR value.
6087 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
6089 <b>Example usage</b>
6091 MSR_IA32_PKG_HDC_CTL_REGISTER Msr;
6093 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);
6094 AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);
6096 @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.
6098 #define MSR_IA32_PKG_HDC_CTL 0x00000DB0
6101 MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL
6105 /// Individual bit fields
6109 /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled
6110 /// logical processors in the package. See Section 14.5.2, "Package level
6111 /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.
6113 UINT32 HDC_Pkg_Enable
: 1;
6114 UINT32 Reserved1
: 31;
6115 UINT32 Reserved2
: 32;
6118 /// All bit fields as a 32-bit value
6122 /// All bit fields as a 64-bit value
6125 } MSR_IA32_PKG_HDC_CTL_REGISTER
;
6128 Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.
6130 @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)
6131 @param EAX Lower 32-bits of MSR value.
6132 Described by the type MSR_IA32_PM_CTL1_REGISTER.
6133 @param EDX Upper 32-bits of MSR value.
6134 Described by the type MSR_IA32_PM_CTL1_REGISTER.
6136 <b>Example usage</b>
6138 MSR_IA32_PM_CTL1_REGISTER Msr;
6140 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);
6141 AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);
6143 @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.
6145 #define MSR_IA32_PM_CTL1 0x00000DB1
6148 MSR information returned for MSR index #MSR_IA32_PM_CTL1
6152 /// Individual bit fields
6156 /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for
6157 /// package level HDC control. See Section 14.5.3.
6158 /// If CPUID.06H:EAX.[13] = 1.
6160 UINT32 HDC_Allow_Block
: 1;
6161 UINT32 Reserved1
: 31;
6162 UINT32 Reserved2
: 32;
6165 /// All bit fields as a 32-bit value
6169 /// All bit fields as a 64-bit value
6172 } MSR_IA32_PM_CTL1_REGISTER
;
6175 Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.
6176 Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical
6177 processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.
6179 @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)
6180 @param EAX Lower 32-bits of MSR value.
6181 @param EDX Upper 32-bits of MSR value.
6183 <b>Example usage</b>
6187 Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);
6189 @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.
6191 #define MSR_IA32_THREAD_STALL 0x00000DB2
6194 Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]
6195 CPUID.80000001H:EDX.[2 9]).
6197 @param ECX MSR_IA32_EFER (0xC0000080)
6198 @param EAX Lower 32-bits of MSR value.
6199 Described by the type MSR_IA32_EFER_REGISTER.
6200 @param EDX Upper 32-bits of MSR value.
6201 Described by the type MSR_IA32_EFER_REGISTER.
6203 <b>Example usage</b>
6205 MSR_IA32_EFER_REGISTER Msr;
6207 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
6208 AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);
6210 @note MSR_IA32_EFER is defined as IA32_EFER in SDM.
6212 #define MSR_IA32_EFER 0xC0000080
6215 MSR information returned for MSR index #MSR_IA32_EFER
6219 /// Individual bit fields
6223 /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET
6224 /// instructions in 64-bit mode.
6227 UINT32 Reserved1
: 7;
6229 /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode
6233 UINT32 Reserved2
: 1;
6235 /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode
6236 /// is active when set.
6240 /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).
6243 UINT32 Reserved3
: 20;
6244 UINT32 Reserved4
: 32;
6247 /// All bit fields as a 32-bit value
6251 /// All bit fields as a 64-bit value
6254 } MSR_IA32_EFER_REGISTER
;
6257 System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
6259 @param ECX MSR_IA32_STAR (0xC0000081)
6260 @param EAX Lower 32-bits of MSR value.
6261 @param EDX Upper 32-bits of MSR value.
6263 <b>Example usage</b>
6267 Msr = AsmReadMsr64 (MSR_IA32_STAR);
6268 AsmWriteMsr64 (MSR_IA32_STAR, Msr);
6270 @note MSR_IA32_STAR is defined as IA32_STAR in SDM.
6272 #define MSR_IA32_STAR 0xC0000081
6275 IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
6277 @param ECX MSR_IA32_LSTAR (0xC0000082)
6278 @param EAX Lower 32-bits of MSR value.
6279 @param EDX Upper 32-bits of MSR value.
6281 <b>Example usage</b>
6285 Msr = AsmReadMsr64 (MSR_IA32_LSTAR);
6286 AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);
6288 @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.
6290 #define MSR_IA32_LSTAR 0xC0000082
6293 IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL
6294 instruction is not recognized in compatibility mode. If
6295 CPUID.80000001:EDX.[29] = 1.
6297 @param ECX MSR_IA32_CSTAR (0xC0000083)
6298 @param EAX Lower 32-bits of MSR value.
6299 @param EDX Upper 32-bits of MSR value.
6301 <b>Example usage</b>
6305 Msr = AsmReadMsr64 (MSR_IA32_CSTAR);
6306 AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);
6308 @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.
6310 #define MSR_IA32_CSTAR 0xC0000083
6313 System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
6315 @param ECX MSR_IA32_FMASK (0xC0000084)
6316 @param EAX Lower 32-bits of MSR value.
6317 @param EDX Upper 32-bits of MSR value.
6319 <b>Example usage</b>
6323 Msr = AsmReadMsr64 (MSR_IA32_FMASK);
6324 AsmWriteMsr64 (MSR_IA32_FMASK, Msr);
6326 @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.
6328 #define MSR_IA32_FMASK 0xC0000084
6331 Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.
6333 @param ECX MSR_IA32_FS_BASE (0xC0000100)
6334 @param EAX Lower 32-bits of MSR value.
6335 @param EDX Upper 32-bits of MSR value.
6337 <b>Example usage</b>
6341 Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);
6342 AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);
6344 @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.
6346 #define MSR_IA32_FS_BASE 0xC0000100
6349 Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
6351 @param ECX MSR_IA32_GS_BASE (0xC0000101)
6352 @param EAX Lower 32-bits of MSR value.
6353 @param EDX Upper 32-bits of MSR value.
6355 <b>Example usage</b>
6359 Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);
6360 AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);
6362 @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.
6364 #define MSR_IA32_GS_BASE 0xC0000101
6367 Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
6369 @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)
6370 @param EAX Lower 32-bits of MSR value.
6371 @param EDX Upper 32-bits of MSR value.
6373 <b>Example usage</b>
6377 Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);
6378 AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);
6380 @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.
6382 #define MSR_IA32_KERNEL_GS_BASE 0xC0000102
6385 Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.
6387 @param ECX MSR_IA32_TSC_AUX (0xC0000103)
6388 @param EAX Lower 32-bits of MSR value.
6389 Described by the type MSR_IA32_TSC_AUX_REGISTER.
6390 @param EDX Upper 32-bits of MSR value.
6391 Described by the type MSR_IA32_TSC_AUX_REGISTER.
6393 <b>Example usage</b>
6395 MSR_IA32_TSC_AUX_REGISTER Msr;
6397 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);
6398 AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);
6400 @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.
6402 #define MSR_IA32_TSC_AUX 0xC0000103
6405 MSR information returned for MSR index #MSR_IA32_TSC_AUX
6409 /// Individual bit fields
6413 /// [Bits 31:0] AUX: Auxiliary signature of TSC.
6416 UINT32 Reserved
: 32;
6419 /// All bit fields as a 32-bit value
6423 /// All bit fields as a 64-bit value
6426 } MSR_IA32_TSC_AUX_REGISTER
;