2 Intel CPUID leaf definitions.
4 Provides defines for CPUID leaf indexes. Data structures are provided for
5 registers returned by a CPUID leaf that contain one or more bit fields.
6 If a register returned is a single 32-bit value, then a data structure is
7 not provided for that register.
9 Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
14 November 2018, CPUID instruction.
18 #ifndef __INTEL_CPUID_H__
19 #define __INTEL_CPUID_H__
22 CPUID Signature Information
24 @param EAX CPUID_SIGNATURE (0x00)
26 @retval EAX Returns the highest value the CPUID instruction recognizes for
27 returning basic processor information. The value is returned is
29 @retval EBX First 4 characters of a vendor identification string.
30 @retval ECX Last 4 characters of a vendor identification string.
31 @retval EDX Middle 4 characters of a vendor identification string.
40 AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
43 #define CPUID_SIGNATURE 0x00
46 /// @{ CPUID signature values returned by Intel processors
48 #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')
49 #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')
50 #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')
56 CPUID Version Information
58 @param EAX CPUID_VERSION_INFO (0x01)
60 @retval EAX Returns Model, Family, Stepping Information described by the
61 type CPUID_VERSION_INFO_EAX.
62 @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by
63 the type CPUID_VERSION_INFO_EBX.
64 @retval ECX CPU Feature Information described by the type
65 CPUID_VERSION_INFO_ECX.
66 @retval EDX CPU Feature Information described by the type
67 CPUID_VERSION_INFO_EDX.
71 CPUID_VERSION_INFO_EAX Eax;
72 CPUID_VERSION_INFO_EBX Ebx;
73 CPUID_VERSION_INFO_ECX Ecx;
74 CPUID_VERSION_INFO_EDX Edx;
76 AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
79 #define CPUID_VERSION_INFO 0x01
82 CPUID Version Information returned in EAX for CPUID leaf
87 /// Individual bit fields
90 UINT32 SteppingId
: 4; ///< [Bits 3:0] Stepping ID
91 UINT32 Model
: 4; ///< [Bits 7:4] Model
92 UINT32 FamilyId
: 4; ///< [Bits 11:8] Family
93 UINT32 ProcessorType
: 2; ///< [Bits 13:12] Processor Type
94 UINT32 Reserved1
: 2; ///< [Bits 15:14] Reserved
95 UINT32 ExtendedModelId
: 4; ///< [Bits 19:16] Extended Model ID
96 UINT32 ExtendedFamilyId
: 8; ///< [Bits 27:20] Extended Family ID
97 UINT32 Reserved2
: 4; ///< Reserved
100 /// All bit fields as a 32-bit value
103 } CPUID_VERSION_INFO_EAX
;
106 /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType
108 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00
109 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01
110 #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02
116 CPUID Version Information returned in EBX for CPUID leaf
121 /// Individual bit fields
125 /// [Bits 7:0] Provides an entry into a brand string table that contains
126 /// brand strings for IA-32 processors.
128 UINT32 BrandIndex
: 8;
130 /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
131 /// and CLFLUSHOPT instructions in 8-byte increments. This field was
132 /// introduced in the Pentium 4 processor.
134 UINT32 CacheLineSize
: 8;
136 /// [Bits 23:16] Maximum number of addressable IDs for logical processors
137 /// in this physical package.
140 /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is
141 /// the number of unique initial APICIDs reserved for addressing different
142 /// logical processors in a physical package. This field is only valid if
143 /// CPUID.1.EDX.HTT[bit 28]= 1.
145 UINT32 MaximumAddressableIdsForLogicalProcessors
: 8;
147 /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
148 /// processor during power up. This field was introduced in the Pentium 4
151 UINT32 InitialLocalApicId
: 8;
154 /// All bit fields as a 32-bit value
157 } CPUID_VERSION_INFO_EBX
;
160 CPUID Version Information returned in ECX for CPUID leaf
165 /// Individual bit fields
169 /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the
170 /// processor supports this technology
174 /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
175 /// instruction. Carryless Multiplication
177 UINT32 PCLMULQDQ
: 1;
179 /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports
180 /// DS area using 64-bit layout.
184 /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports
189 /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor
190 /// supports the extensions to the Debug Store feature to allow for branch
191 /// message storage qualified by CPL
195 /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the
196 /// processor supports this technology.
200 /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
201 /// supports this technology
205 /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates
206 /// that the processor supports this technology
210 /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor
211 /// supports this technology
215 /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
216 /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
217 /// extensions are not present in the processor.
221 /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode
222 /// can be set to either adaptive mode or shared mode. A value of 0 indicates
223 /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
224 /// Bit 24 (L1 Data Cache Context Mode) for details
228 /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
229 /// MSR for silicon debug
233 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
234 /// Add) extensions using YMM state.
238 /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature
241 UINT32 CMPXCHG16B
: 1;
243 /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor
244 /// supports changing IA32_MISC_ENABLE[Bit 23].
246 UINT32 xTPR_Update_Control
: 1;
248 /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the
249 /// processor supports the performance and debug feature indication MSR
250 /// IA32_PERF_CAPABILITIES.
255 /// [Bit 17] Process-context identifiers. A value of 1 indicates that the
256 /// processor supports PCIDs and that software may set CR4.PCIDE to 1.
260 /// [Bit 18] A value of 1 indicates the processor supports the ability to
261 /// prefetch data from a memory mapped device. Direct Cache Access.
265 /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
269 /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
273 /// [Bit 21] A value of 1 indicates that the processor supports x2APIC
278 /// [Bit 22] A value of 1 indicates that the processor supports MOVBE
283 /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
288 /// [Bit 24] A value of 1 indicates that the processor's local APIC timer
289 /// supports one-shot operation using a TSC deadline value.
291 UINT32 TSC_Deadline
: 1;
293 /// [Bit 25] A value of 1 indicates that the processor supports the AESNI
294 /// instruction extensions.
298 /// [Bit 26] A value of 1 indicates that the processor supports the
299 /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
300 /// instructions, and XCR0.
304 /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
305 /// to enable XSETBV/XGETBV instructions to access XCR0 and to support
306 /// processor extended state management using XSAVE/XRSTOR.
310 /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
315 /// [Bit 29] A value of 1 indicates that processor supports 16-bit
316 /// floating-point conversion instructions.
320 /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
324 /// [Bit 31] Always returns 0.
329 /// All bit fields as a 32-bit value
332 } CPUID_VERSION_INFO_ECX
;
335 CPUID Version Information returned in EDX for CPUID leaf
340 /// Individual bit fields
344 /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
348 /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
349 /// including CR4.VME for controlling the feature, CR4.PVI for protected
350 /// mode virtual interrupts, software interrupt indirection, expansion of
351 /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
352 /// EFLAGS.VIP flags.
356 /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including
357 /// CR4.DE for controlling the feature, and optional trapping of accesses to
362 /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,
363 /// including CR4.PSE for controlling the feature, the defined dirty bit in
364 /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
369 /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,
370 /// including CR4.TSD for controlling privilege.
374 /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The
375 /// RDMSR and WRMSR instructions are supported. Some of the MSRs are
376 /// implementation dependent.
380 /// [Bit 6] Physical Address Extension. Physical addresses greater than 32
381 /// bits are supported: extended page table entry formats, an extra level in
382 /// the page translation tables is defined, 2-MByte pages are supported
383 /// instead of 4 Mbyte pages if PAE bit is 1.
387 /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine
388 /// Checks, including CR4.MCE for controlling the feature. This feature does
389 /// not define the model-specific implementations of machine-check error
390 /// logging, reporting, and processor shutdowns. Machine Check exception
391 /// handlers may have to depend on processor version to do model specific
392 /// processing of the exception, or test for the presence of the Machine
397 /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)
398 /// instruction is supported (implicitly locked and atomic).
402 /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable
403 /// Interrupt Controller (APIC), responding to memory mapped commands in the
404 /// physical address range FFFE0000H to FFFE0FFFH (by default - some
405 /// processors permit the APIC to be relocated).
408 UINT32 Reserved1
: 1;
410 /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT
411 /// and associated MSRs are supported.
415 /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap
416 /// MSR contains feature bits that describe what memory types are supported,
417 /// how many variable MTRRs are supported, and whether fixed MTRRs are
422 /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure
423 /// entries that map a page, indicating TLB entries that are common to
424 /// different processes and need not be flushed. The CR4.PGE bit controls
429 /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine
430 /// Check Architecture of reporting machine errors is supported. The MCG_CAP
431 /// MSR contains feature bits describing how many banks of error reporting
432 /// MSRs are supported.
436 /// [Bit 15] Conditional Move Instructions. The conditional move instruction
437 /// CMOV is supported. In addition, if x87 FPU is present as indicated by the
438 /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
442 /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This
443 /// feature augments the Memory Type Range Registers (MTRRs), allowing an
444 /// operating system to specify attributes of memory accessed through a
445 /// linear address on a 4KB granularity.
449 /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical
450 /// memory beyond 4 GBytes are supported with 32-bit paging. This feature
451 /// indicates that upper bits of the physical address of a 4-MByte page are
452 /// encoded in bits 20:13 of the page-directory entry. Such physical
453 /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
457 /// [Bit 18] Processor Serial Number. The processor supports the 96-bit
458 /// processor identification number feature and the feature is enabled.
462 /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.
465 UINT32 Reserved2
: 1;
467 /// [Bit 21] Debug Store. The processor supports the ability to write debug
468 /// information into a memory resident buffer. This feature is used by the
469 /// branch trace store (BTS) and precise event-based sampling (PEBS)
474 /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The
475 /// processor implements internal MSRs that allow processor temperature to
476 /// be monitored and processor performance to be modulated in predefined
477 /// duty cycles under software control.
481 /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX
486 /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
487 /// instructions are supported for fast save and restore of the floating
488 /// point context. Presence of this bit also indicates that CR4.OSFXSR is
489 /// available for an operating system to indicate that it supports the
490 /// FXSAVE and FXRSTOR instructions.
494 /// [Bit 25] SSE. The processor supports the SSE extensions.
498 /// [Bit 26] SSE2. The processor supports the SSE2 extensions.
502 /// [Bit 27] Self Snoop. The processor supports the management of
503 /// conflicting memory types by performing a snoop of its own cache
504 /// structure for transactions issued to the bus.
508 /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT
509 /// indicates there is only a single logical processor in the package and
510 /// software should assume only a single APIC ID is reserved. A value of 1
511 /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of
512 /// addressable IDs for logical processors in this package) is valid for the
517 /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor
518 /// automatic thermal control circuitry (TCC).
521 UINT32 Reserved3
: 1;
523 /// [Bit 31] Pending Break Enable. The processor supports the use of the
524 /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
525 /// asserted) to signal the processor that an interrupt is pending and that
526 /// the processor should return to normal operation to handle the interrupt.
527 /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
532 /// All bit fields as a 32-bit value
535 } CPUID_VERSION_INFO_EDX
;
538 CPUID Cache and TLB Information
540 @param EAX CPUID_CACHE_INFO (0x02)
542 @retval EAX Cache and TLB Information described by the type
543 CPUID_CACHE_INFO_CACHE_TLB.
544 CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns
545 0x01 and must be ignored. Only valid if
546 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
547 @retval EBX Cache and TLB Information described by the type
548 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
549 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
550 @retval ECX Cache and TLB Information described by the type
551 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
552 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
553 @retval EDX Cache and TLB Information described by the type
554 CPUID_CACHE_INFO_CACHE_TLB. Only valid if
555 CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
559 CPUID_CACHE_INFO_CACHE_TLB Eax;
560 CPUID_CACHE_INFO_CACHE_TLB Ebx;
561 CPUID_CACHE_INFO_CACHE_TLB Ecx;
562 CPUID_CACHE_INFO_CACHE_TLB Edx;
564 AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
567 <b>Cache Descriptor values</b>
569 <tr><th>Value </th><th> Type </th><th> Description </th></tr>
570 <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>
571 <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>
572 <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>
573 <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>
574 <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>
575 <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>
576 <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,
577 32 byte line size</td></tr>
578 <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,
579 32 byte line size</td></tr>
580 <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,
581 64 byte line size</td></tr>
582 <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>
583 <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>
584 <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
585 <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>
586 <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>
587 <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>
588 <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>
589 <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,
590 2 lines per sector</td></tr>
591 <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,
592 2 lines per sector</td></tr>
593 <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>
594 <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,
595 2 lines per sector</td></tr>
596 <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,
597 2 lines per sector</td></tr>
598 <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,
599 64 byte line size</td></tr>
600 <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,
601 64 byte line size</td></tr>
602 <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,
603 no 3rd-level cache</td></tr>
604 <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>
605 <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>
606 <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>
607 <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>
608 <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>
609 <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>
610 <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>
611 <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>
612 <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
613 (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>
614 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
615 <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>
616 <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>
617 <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>
618 <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>
619 <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>
620 <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>
621 <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>
622 <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>
623 <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>
624 <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>
625 <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
626 <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
627 <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
628 <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
629 <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
630 <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
631 <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
632 <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
633 <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
634 <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,
635 32 entries and a separate array with 1 GByte pages, 4-way set associative,
637 <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>
638 <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
639 <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
640 <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
641 <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>
642 <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>
643 <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>
644 <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>
645 <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>
646 <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>
647 <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>
648 <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>
649 <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>
650 <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,
651 2 lines per sector</td></tr>
652 <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,
653 2 lines per sector</td></tr>
654 <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,
655 2 lines per sector</td></tr>
656 <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,
657 2 lines per sector</td></tr>
658 <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>
659 <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>
660 <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>
661 <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>
662 <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>
663 <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>
664 <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>
665 <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
666 <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
667 <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>
668 <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
669 <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>
670 <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>
671 <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
672 <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>
673 <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>
674 <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,
675 128 entries</td></tr>
676 <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>
677 <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>
678 <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,
679 1024 entries</td></tr>
680 <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
681 <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,
682 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
683 <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>
684 <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
685 <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
686 <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
687 <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>
688 <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
689 <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>
690 <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>
691 <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>
692 <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>
693 <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>
694 <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>
695 <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
696 <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>
697 <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>
698 <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>
699 <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>
700 <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>
701 <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>
702 <tr><td> 0xFE </td><td> General </td><td> CPUID leaf 2 does not report TLB descriptor information; use CPUID
703 leaf 18H to query TLB and other address translation parameters.</td></tr>
704 <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,
705 use CPUID leaf 4 to query cache parameters</td></tr>
708 #define CPUID_CACHE_INFO 0x02
711 CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
712 leaf #CPUID_CACHE_INFO.
716 /// Individual bit fields
719 UINT32 Reserved
: 31;
721 /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
722 /// if 1, then none of the cache descriptor bytes in the register are valid.
727 /// Array of Cache and TLB descriptor bytes
729 UINT8 CacheDescriptor
[4];
731 /// All bit fields as a 32-bit value
734 } CPUID_CACHE_INFO_CACHE_TLB
;
737 CPUID Processor Serial Number
739 Processor serial number (PSN) is not supported in the Pentium 4 processor
740 or later. On all models, use the PSN flag (returned using CPUID) to check
741 for PSN support before accessing the feature.
743 @param EAX CPUID_SERIAL_NUMBER (0x03)
745 @retval EAX Reserved.
746 @retval EBX Reserved.
747 @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in
748 Pentium III processor only; otherwise, the value in this
749 register is reserved.)
750 @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in
751 Pentium III processor only; otherwise, the value in this
752 register is reserved.)
759 AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
762 #define CPUID_SERIAL_NUMBER 0x03
765 CPUID Cache Parameters
767 @param EAX CPUID_CACHE_PARAMS (0x04)
768 @param ECX Cache Level. Valid values start at 0. Software can enumerate
769 the deterministic cache parameters for each level of the cache
770 hierarchy starting with an index value of 0, until the
771 parameters report the value associated with the CacheType
772 field in CPUID_CACHE_PARAMS_EAX is 0.
774 @retval EAX Returns cache type information described by the type
775 CPUID_CACHE_PARAMS_EAX.
776 @retval EBX Returns cache line and associativity information described by
777 the type CPUID_CACHE_PARAMS_EBX.
778 @retval ECX Returns the number of sets in the cache.
779 @retval EDX Returns cache WINVD/INVD behavior described by the type
780 CPUID_CACHE_PARAMS_EDX.
785 CPUID_CACHE_PARAMS_EAX Eax;
786 CPUID_CACHE_PARAMS_EBX Ebx;
788 CPUID_CACHE_PARAMS_EDX Edx;
793 CPUID_CACHE_PARAMS, CacheLevel,
794 &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
797 } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
800 #define CPUID_CACHE_PARAMS 0x04
803 CPUID Cache Parameters Information returned in EAX for CPUID leaf
808 /// Individual bit fields
812 /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
813 /// then there is no information for the requested cache level.
815 UINT32 CacheType
: 5;
817 /// [Bits 7:5] Cache level (Starts at 1).
819 UINT32 CacheLevel
: 3;
821 /// [Bit 8] Self Initializing cache level (does not need SW initialization).
823 UINT32 SelfInitializingCache
: 1;
825 /// [Bit 9] Fully Associative cache.
827 UINT32 FullyAssociativeCache
: 1;
829 /// [Bits 13:10] Reserved.
833 /// [Bits 25:14] Maximum number of addressable IDs for logical processors
834 /// sharing this cache.
836 /// Add one to the return value to get the result.
837 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])
838 /// is the number of unique initial APIC IDs reserved for addressing
839 /// different logical processors sharing this cache.
841 UINT32 MaximumAddressableIdsForLogicalProcessors
: 12;
843 /// [Bits 31:26] Maximum number of addressable IDs for processor cores in
844 /// the physical package.
846 /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])
847 /// is the number of unique Core_IDs reserved for addressing different
848 /// processor cores in a physical package. Core ID is a subset of bits of
849 /// the initial APIC ID.
850 /// The returned value is constant for valid initial values in ECX. Valid
851 /// ECX values start from 0.
853 UINT32 MaximumAddressableIdsForProcessorCores
: 6;
856 /// All bit fields as a 32-bit value
859 } CPUID_CACHE_PARAMS_EAX
;
862 /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType
864 #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00
865 #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01
866 #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02
867 #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03
873 CPUID Cache Parameters Information returned in EBX for CPUID leaf
878 /// Individual bit fields
882 /// [Bits 11:0] System Coherency Line Size. Add one to the return value to
885 UINT32 LineSize
: 12;
887 /// [Bits 21:12] Physical Line Partitions. Add one to the return value to
890 UINT32 LinePartitions
: 10;
892 /// [Bits 31:22] Ways of associativity. Add one to the return value to get
898 /// All bit fields as a 32-bit value
901 } CPUID_CACHE_PARAMS_EBX
;
904 CPUID Cache Parameters Information returned in EDX for CPUID leaf
909 /// Individual bit fields
913 /// [Bit 0] Write-Back Invalidate/Invalidate.
914 /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level
915 /// caches for threads sharing this cache.
916 /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
917 /// non-originating threads sharing this cache.
919 UINT32 Invalidate
: 1;
921 /// [Bit 1] Cache Inclusiveness.
922 /// 0 = Cache is not inclusive of lower cache levels.
923 /// 1 = Cache is inclusive of lower cache levels.
925 UINT32 CacheInclusiveness
: 1;
927 /// [Bit 2] Complex Cache Indexing.
928 /// 0 = Direct mapped cache.
929 /// 1 = A complex function is used to index the cache, potentially using all
932 UINT32 ComplexCacheIndexing
: 1;
933 UINT32 Reserved
: 29;
936 /// All bit fields as a 32-bit value
939 } CPUID_CACHE_PARAMS_EDX
;
942 CPUID MONITOR/MWAIT Information
944 @param EAX CPUID_MONITOR_MWAIT (0x05)
946 @retval EAX Smallest monitor-line size in bytes described by the type
947 CPUID_MONITOR_MWAIT_EAX.
948 @retval EBX Largest monitor-line size in bytes described by the type
949 CPUID_MONITOR_MWAIT_EBX.
950 @retval ECX Enumeration of Monitor-Mwait extensions support described by
951 the type CPUID_MONITOR_MWAIT_ECX.
952 @retval EDX Sub C-states supported described by the type
953 CPUID_MONITOR_MWAIT_EDX.
957 CPUID_MONITOR_MWAIT_EAX Eax;
958 CPUID_MONITOR_MWAIT_EBX Ebx;
959 CPUID_MONITOR_MWAIT_ECX Ecx;
960 CPUID_MONITOR_MWAIT_EDX Edx;
962 AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
965 #define CPUID_MONITOR_MWAIT 0x05
968 CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
969 #CPUID_MONITOR_MWAIT.
973 /// Individual bit fields
977 /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
978 /// monitor granularity).
980 UINT32 SmallestMonitorLineSize
: 16;
981 UINT32 Reserved
: 16;
984 /// All bit fields as a 32-bit value
987 } CPUID_MONITOR_MWAIT_EAX
;
990 CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf
991 #CPUID_MONITOR_MWAIT.
995 /// Individual bit fields
999 /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
1000 /// monitor granularity).
1002 UINT32 LargestMonitorLineSize
: 16;
1003 UINT32 Reserved
: 16;
1006 /// All bit fields as a 32-bit value
1009 } CPUID_MONITOR_MWAIT_EBX
;
1012 CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf
1013 #CPUID_MONITOR_MWAIT.
1017 /// Individual bit fields
1021 /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,
1022 /// and EDX are valid.
1024 UINT32 ExtensionsSupported
: 1;
1026 /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
1027 /// interrupts disabled.
1029 UINT32 InterruptAsBreak
: 1;
1030 UINT32 Reserved
: 30;
1033 /// All bit fields as a 32-bit value
1036 } CPUID_MONITOR_MWAIT_ECX
;
1039 CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf
1040 #CPUID_MONITOR_MWAIT.
1043 The definition of C0 through C7 states for MWAIT extension are
1044 processor-specific C-states, not ACPI C-states.
1048 /// Individual bit fields
1052 /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
1054 UINT32 C0States
: 4;
1056 /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
1058 UINT32 C1States
: 4;
1060 /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
1062 UINT32 C2States
: 4;
1064 /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
1066 UINT32 C3States
: 4;
1068 /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
1070 UINT32 C4States
: 4;
1072 /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
1074 UINT32 C5States
: 4;
1076 /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
1078 UINT32 C6States
: 4;
1080 /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
1082 UINT32 C7States
: 4;
1085 /// All bit fields as a 32-bit value
1088 } CPUID_MONITOR_MWAIT_EDX
;
1091 CPUID Thermal and Power Management
1093 @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)
1095 @retval EAX Thermal and power management features described by the type
1096 CPUID_THERMAL_POWER_MANAGEMENT_EAX.
1097 @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor
1098 described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.
1099 @retval ECX Performance features described by the type
1100 CPUID_THERMAL_POWER_MANAGEMENT_ECX.
1101 @retval EDX Reserved.
1103 <b>Example usage</b>
1105 CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
1106 CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
1107 CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
1109 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
1112 #define CPUID_THERMAL_POWER_MANAGEMENT 0x06
1115 CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
1116 #CPUID_THERMAL_POWER_MANAGEMENT.
1120 /// Individual bit fields
1124 /// [Bit 0] Digital temperature sensor is supported if set.
1126 UINT32 DigitalTemperatureSensor
: 1;
1128 /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
1130 UINT32 TurboBoostTechnology
: 1;
1132 /// [Bit 2] APIC-Timer-always-running feature is supported if set.
1135 UINT32 Reserved1
: 1;
1137 /// [Bit 4] Power limit notification controls are supported if set.
1141 /// [Bit 5] Clock modulation duty cycle extension is supported if set.
1145 /// [Bit 6] Package thermal management is supported if set.
1149 /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
1150 /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
1154 /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
1156 UINT32 HWP_Notification
: 1;
1158 /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
1160 UINT32 HWP_Activity_Window
: 1;
1162 /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
1164 UINT32 HWP_Energy_Performance_Preference
: 1;
1166 /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
1168 UINT32 HWP_Package_Level_Request
: 1;
1169 UINT32 Reserved2
: 1;
1171 /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
1172 /// IA32_THREAD_STALL MSRs are supported if set.
1176 /// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.
1178 UINT32 TurboBoostMaxTechnology30
: 1;
1180 /// [Bit 15] HWP Capabilities.
1181 /// Highest Performance change is supported if set.
1183 UINT32 HWPCapabilities
: 1;
1185 /// [Bit 16] HWP PECI override is supported if set.
1187 UINT32 HWPPECIOverride
: 1;
1189 /// [Bit 17] Flexible HWP is supported if set.
1191 UINT32 FlexibleHWP
: 1;
1193 /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.
1195 UINT32 FastAccessMode
: 1;
1196 UINT32 Reserved4
: 1;
1198 /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.
1200 UINT32 IgnoringIdleLogicalProcessorHWPRequest
: 1;
1201 UINT32 Reserved5
: 11;
1204 /// All bit fields as a 32-bit value
1207 } CPUID_THERMAL_POWER_MANAGEMENT_EAX
;
1210 CPUID Thermal and Power Management Information returned in EBX for CPUID leaf
1211 #CPUID_THERMAL_POWER_MANAGEMENT.
1215 /// Individual bit fields
1219 /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
1221 UINT32 InterruptThresholds
: 4;
1222 UINT32 Reserved
: 28;
1225 /// All bit fields as a 32-bit value
1228 } CPUID_THERMAL_POWER_MANAGEMENT_EBX
;
1231 CPUID Thermal and Power Management Information returned in ECX for CPUID leaf
1232 #CPUID_THERMAL_POWER_MANAGEMENT.
1236 /// Individual bit fields
1240 /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF
1241 /// and IA32_APERF). The capability to provide a measure of delivered
1242 /// processor performance (since last reset of the counters), as a percentage
1243 /// of the expected processor performance when running at the TSC frequency.
1245 UINT32 HardwareCoordinationFeedback
: 1;
1246 UINT32 Reserved1
: 2;
1248 /// [Bit 3] If this bit is set, then the processor supports performance-energy
1249 /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
1252 UINT32 PerformanceEnergyBias
: 1;
1253 UINT32 Reserved2
: 28;
1256 /// All bit fields as a 32-bit value
1259 } CPUID_THERMAL_POWER_MANAGEMENT_ECX
;
1262 CPUID Structured Extended Feature Flags Enumeration
1264 @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
1265 @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).
1268 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
1269 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.
1271 @retval EAX The maximum input value for ECX to retrieve sub-leaf information.
1272 @retval EBX Structured Extended Feature Flags described by the type
1273 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
1274 @retval ECX Structured Extended Feature Flags described by the type
1275 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
1276 @retval EDX Reserved.
1278 <b>Example usage</b>
1281 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
1282 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
1286 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1287 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
1288 &Eax, NULL, NULL, NULL
1290 for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
1292 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
1294 NULL, &Ebx.Uint32, &Ecx.Uint32, NULL
1299 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07
1302 /// CPUID Structured Extended Feature Flags Enumeration sub-leaf
1304 #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00
1307 CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf
1308 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1309 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1313 /// Individual bit fields
1317 /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
1319 UINT32 FSGSBASE
: 1;
1321 /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
1323 UINT32 IA32_TSC_ADJUST
: 1;
1325 /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT
1326 /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".
1330 /// [Bit 3] If 1 indicates the processor supports the first group of advanced
1331 /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
1335 /// [Bit 4] Hardware Lock Elision
1339 /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
1343 /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
1345 UINT32 FDP_EXCPTN_ONLY
: 1;
1347 /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
1351 /// [Bit 8] If 1 indicates the processor supports the second group of
1352 /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
1353 /// SARX, SHLX, SHRX)
1357 /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
1359 UINT32 EnhancedRepMovsbStosb
: 1;
1361 /// [Bit 10] If 1, supports INVPCID instruction for system software that
1362 /// manages process-context identifiers.
1366 /// [Bit 11] Restricted Transactional Memory
1370 /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
1371 /// Monitoring capability if 1.
1375 /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
1377 UINT32 DeprecateFpuCsDs
: 1;
1379 /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
1383 /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
1384 /// Allocation capability if 1.
1388 /// [Bit 16] AVX512F.
1392 /// [Bit 17] AVX512DQ.
1394 UINT32 AVX512DQ
: 1;
1396 /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
1400 /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
1405 /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
1406 /// instructions) if 1.
1410 /// [Bit 21] AVX512_IFMA.
1412 UINT32 AVX512_IFMA
: 1;
1413 UINT32 Reserved6
: 1;
1415 /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
1417 UINT32 CLFLUSHOPT
: 1;
1419 /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.
1423 /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
1426 UINT32 IntelProcessorTrace
: 1;
1428 /// [Bit 26] AVX512PF. (Intel Xeon Phi only.).
1430 UINT32 AVX512PF
: 1;
1432 /// [Bit 27] AVX512ER. (Intel Xeon Phi only.).
1434 UINT32 AVX512ER
: 1;
1436 /// [Bit 28] AVX512CD.
1438 UINT32 AVX512CD
: 1;
1440 /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)
1441 /// SHA Extensions) if 1.
1445 /// [Bit 30] AVX512BW.
1447 UINT32 AVX512BW
: 1;
1449 /// [Bit 31] AVX512VL.
1451 UINT32 AVX512VL
: 1;
1454 /// All bit fields as a 32-bit value
1457 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
;
1460 CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf
1461 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1462 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1466 /// Individual bit fields
1470 /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
1471 /// (Intel Xeon Phi only.)
1473 UINT32 PREFETCHWT1
: 1;
1475 /// [Bit 1] AVX512_VBMI.
1477 UINT32 AVX512_VBMI
: 1;
1479 /// [Bit 2] Supports user-mode instruction prevention if 1.
1483 /// [Bit 3] Supports protection keys for user-mode pages if 1.
1487 /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
1488 /// RDPKRU/WRPKRU instructions).
1491 UINT32 Reserved5
: 9;
1493 /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
1495 UINT32 AVX512_VPOPCNTDQ
: 1;
1496 UINT32 Reserved7
: 1;
1498 /// [Bits 16] Supports 5-level paging if 1.
1500 UINT32 FiveLevelPage
: 1;
1502 /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
1507 /// [Bit 22] RDPID and IA32_TSC_AUX are available if 1.
1510 UINT32 Reserved3
: 7;
1512 /// [Bit 30] Supports SGX Launch Configuration if 1.
1515 UINT32 Reserved4
: 1;
1518 /// All bit fields as a 32-bit value
1521 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
;
1524 CPUID Structured Extended Feature Flags Enumeration in EDX for CPUID leaf
1525 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
1526 #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
1530 /// Individual bit fields
1534 /// [Bit 1:0] Reserved.
1536 UINT32 Reserved1
: 2;
1538 /// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.)
1540 UINT32 AVX512_4VNNIW
: 1;
1542 /// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)
1544 UINT32 AVX512_4FMAPS
: 1;
1546 /// [Bit 14:4] Reserved.
1548 UINT32 Reserved4
: 11;
1550 /// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part.
1554 /// [Bit 25:16] Reserved.
1556 UINT32 Reserved5
: 10;
1558 /// [Bit 26] Enumerates support for indirect branch restricted speculation
1559 /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors
1560 /// that set this bit support the IA32_SPEC_CTRL MSR and the IA32_PRED_CMD
1561 /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and
1562 /// IA32_PRED_CMD[0] (IBPB).
1564 UINT32 EnumeratesSupportForIBRSAndIBPB
: 1;
1566 /// [Bit 27] Enumerates support for single thread indirect branch
1567 /// predictors (STIBP). Processors that set this bit support the
1568 /// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1]
1571 UINT32 EnumeratesSupportForSTIBP
: 1;
1573 /// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit
1574 /// support the IA32_FLUSH_CMD MSR. They allow software to set
1575 /// IA32_FLUSH_CMD[0] (L1D_FLUSH).
1577 UINT32 EnumeratesSupportForL1D_FLUSH
: 1;
1579 /// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR.
1581 UINT32 EnumeratesSupportForCapability
: 1;
1583 /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.
1585 UINT32 EnumeratesSupportForCoreCapabilitiesMsr
: 1;
1587 /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).
1588 /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow
1589 /// software to set IA32_SPEC_CTRL[2] (SSBD).
1591 UINT32 EnumeratesSupportForSSBD
: 1;
1594 /// All bit fields as a 32-bit value
1597 } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX
;
1600 CPUID Direct Cache Access Information
1602 @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)
1604 @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
1605 @retval EBX Reserved.
1606 @retval ECX Reserved.
1607 @retval EDX Reserved.
1609 <b>Example usage</b>
1613 AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
1616 #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09
1619 CPUID Architectural Performance Monitoring
1621 @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)
1623 @retval EAX Architectural Performance Monitoring information described by
1624 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.
1625 @retval EBX Architectural Performance Monitoring information described by
1626 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.
1627 @retval ECX Reserved.
1628 @retval EDX Architectural Performance Monitoring information described by
1629 the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.
1631 <b>Example usage</b>
1633 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;
1634 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;
1635 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;
1637 AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
1640 #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A
1643 CPUID Architectural Performance Monitoring EAX for CPUID leaf
1644 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1648 /// Individual bit fields
1652 /// [Bit 7:0] Version ID of architectural performance monitoring.
1654 UINT32 ArchPerfMonVerID
: 8;
1656 /// [Bits 15:8] Number of general-purpose performance monitoring counter
1657 /// per logical processor.
1659 /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous
1660 /// block of MSR address space. Each performance event select register is
1661 /// paired with a corresponding performance counter in the 0C1H address
1664 UINT32 PerformanceMonitorCounters
: 8;
1666 /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
1668 /// The bit width of an IA32_PMCx MSR. This the number of valid bits for
1669 /// read operation. On write operations, the lower-order 32 bits of the MSR
1670 /// may be written with any value, and the high-order bits are sign-extended
1671 /// from the value of bit 31.
1673 UINT32 PerformanceMonitorCounterWidth
: 8;
1675 /// [Bits 31:24] Length of EBX bit vector to enumerate architectural
1676 /// performance monitoring events.
1678 UINT32 EbxBitVectorLength
: 8;
1681 /// All bit fields as a 32-bit value
1684 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
;
1687 CPUID Architectural Performance Monitoring EBX for CPUID leaf
1688 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1692 /// Individual bit fields
1696 /// [Bit 0] Core cycle event not available if 1.
1698 UINT32 UnhaltedCoreCycles
: 1;
1700 /// [Bit 1] Instruction retired event not available if 1.
1702 UINT32 InstructionsRetired
: 1;
1704 /// [Bit 2] Reference cycles event not available if 1.
1706 UINT32 UnhaltedReferenceCycles
: 1;
1708 /// [Bit 3] Last-level cache reference event not available if 1.
1710 UINT32 LastLevelCacheReferences
: 1;
1712 /// [Bit 4] Last-level cache misses event not available if 1.
1714 UINT32 LastLevelCacheMisses
: 1;
1716 /// [Bit 5] Branch instruction retired event not available if 1.
1718 UINT32 BranchInstructionsRetired
: 1;
1720 /// [Bit 6] Branch mispredict retired event not available if 1.
1722 UINT32 AllBranchMispredictRetired
: 1;
1723 UINT32 Reserved
: 25;
1726 /// All bit fields as a 32-bit value
1729 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
;
1732 CPUID Architectural Performance Monitoring EDX for CPUID leaf
1733 #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
1737 /// Individual bit fields
1741 /// [Bits 4:0] Number of fixed-function performance counters
1742 /// (if Version ID > 1).
1744 UINT32 FixedFunctionPerformanceCounters
: 5;
1746 /// [Bits 12:5] Bit width of fixed-function performance counters
1747 /// (if Version ID > 1).
1749 UINT32 FixedFunctionPerformanceCounterWidth
: 8;
1750 UINT32 Reserved1
: 2;
1752 /// [Bits 15] AnyThread deprecation.
1754 UINT32 AnyThreadDeprecation
: 1;
1755 UINT32 Reserved2
: 16;
1758 /// All bit fields as a 32-bit value
1761 } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
;
1764 CPUID Extended Topology Information
1767 CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first
1768 checking for the existence of Leaf 1FH before using leaf 0BH.
1769 Most of Leaf 0BH output depends on the initial value in ECX. The EDX output
1770 of leaf 0BH is always valid and does not vary with input value in ECX. Output
1771 value in ECX[7:0] always equals input value in ECX[7:0].
1772 Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index
1773 enumerates a higher-level topological entity in hierarchical order.
1774 For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and
1776 If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],
1777 other input values with ECX > n also return 0 in ECX[15:8].
1779 @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)
1780 @param ECX Level number
1782 @retval EAX Extended topology information described by the type
1783 CPUID_EXTENDED_TOPOLOGY_EAX.
1784 @retval EBX Extended topology information described by the type
1785 CPUID_EXTENDED_TOPOLOGY_EBX.
1786 @retval ECX Extended topology information described by the type
1787 CPUID_EXTENDED_TOPOLOGY_ECX.
1788 @retval EDX x2APIC ID the current logical processor.
1790 <b>Example usage</b>
1792 CPUID_EXTENDED_TOPOLOGY_EAX Eax;
1793 CPUID_EXTENDED_TOPOLOGY_EBX Ebx;
1794 CPUID_EXTENDED_TOPOLOGY_ECX Ecx;
1801 CPUID_EXTENDED_TOPOLOGY, LevelNumber,
1802 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
1805 } while (Eax.Bits.ApicIdShift != 0);
1808 #define CPUID_EXTENDED_TOPOLOGY 0x0B
1811 CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1815 /// Individual bit fields
1819 /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique
1820 /// topology ID of the next level type. All logical processors with the
1821 /// same next level ID share current level.
1824 /// Software should use this field (EAX[4:0]) to enumerate processor
1825 /// topology of the system.
1827 UINT32 ApicIdShift
: 5;
1828 UINT32 Reserved
: 27;
1831 /// All bit fields as a 32-bit value
1834 } CPUID_EXTENDED_TOPOLOGY_EAX
;
1837 CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1841 /// Individual bit fields
1845 /// [Bits 15:0] Number of logical processors at this level type. The number
1846 /// reflects configuration as shipped by Intel.
1849 /// Software must not use EBX[15:0] to enumerate processor topology of the
1850 /// system. This value in this field (EBX[15:0]) is only intended for
1851 /// display/diagnostic purposes. The actual number of logical processors
1852 /// available to BIOS/OS/Applications may be different from the value of
1853 /// EBX[15:0], depending on software and platform hardware configurations.
1855 UINT32 LogicalProcessors
: 16;
1856 UINT32 Reserved
: 16;
1859 /// All bit fields as a 32-bit value
1862 } CPUID_EXTENDED_TOPOLOGY_EBX
;
1865 CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
1869 /// Individual bit fields
1873 /// [Bits 7:0] Level number. Same value in ECX input.
1875 UINT32 LevelNumber
: 8;
1877 /// [Bits 15:8] Level type.
1880 /// The value of the "level type" field is not related to level numbers in
1881 /// any way, higher "level type" values do not mean higher levels.
1883 UINT32 LevelType
: 8;
1884 UINT32 Reserved
: 16;
1887 /// All bit fields as a 32-bit value
1890 } CPUID_EXTENDED_TOPOLOGY_ECX
;
1893 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
1895 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00
1896 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01
1897 #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02
1903 CPUID Extended State Information
1905 @param EAX CPUID_EXTENDED_STATE (0x0D)
1906 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).
1907 CPUID_EXTENDED_STATE_SUB_LEAF (0x01).
1908 CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
1909 Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
1911 #define CPUID_EXTENDED_STATE 0x0D
1914 CPUID Extended State Information Main Leaf
1916 @param EAX CPUID_EXTENDED_STATE (0x0D)
1917 @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
1919 @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]
1920 can be set to 1 only if EAX[n] is 1. The format of the extended
1921 state main leaf is described by the type
1922 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.
1923 @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1924 area) required by enabled features in XCR0. May be different than
1925 ECX if some features at the end of the XSAVE save area are not
1927 @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
1928 area) of the XSAVE/XRSTOR save area required by all supported
1929 features in the processor, i.e., all the valid bit fields in XCR0.
1930 @retval EDX Reports the supported bits of the upper 32 bits of XCR0.
1931 XCR0[n+32] can be set to 1 only if EDX[n] is 1.
1933 <b>Example usage</b>
1935 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
1941 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
1942 &Eax.Uint32, &Ebx, &Ecx, &Edx
1946 #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00
1949 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
1950 sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.
1954 /// Individual bit fields
1958 /// [Bit 0] x87 state.
1962 /// [Bit 1] SSE state.
1966 /// [Bit 2] AVX state.
1970 /// [Bits 4:3] MPX state.
1974 /// [Bits 7:5] AVX-512 state.
1978 /// [Bit 8] Used for IA32_XSS.
1980 UINT32 IA32_XSS
: 1;
1982 /// [Bit 9] PKRU state.
1985 UINT32 Reserved1
: 3;
1987 /// [Bit 13] Used for IA32_XSS, part 2.
1989 UINT32 IA32_XSS_2
: 1;
1990 UINT32 Reserved2
: 18;
1993 /// All bit fields as a 32-bit value
1996 } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
;
1999 CPUID Extended State Information Sub Leaf
2001 @param EAX CPUID_EXTENDED_STATE (0x0D)
2002 @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
2004 @retval EAX The format of the extended state sub-leaf is described by the
2005 type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.
2006 @retval EBX The size in bytes of the XSAVE area containing all states
2007 enabled by XCRO | IA32_XSS.
2008 @retval ECX The format of the extended state sub-leaf is described by the
2009 type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.
2010 @retval EDX Reports the supported bits of the upper 32 bits of the
2011 IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.
2013 <b>Example usage</b>
2015 CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
2017 CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
2021 CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
2022 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
2026 #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01
2029 CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
2030 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
2034 /// Individual bit fields
2038 /// [Bit 0] XSAVEOPT is available.
2040 UINT32 XSAVEOPT
: 1;
2042 /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
2046 /// [Bit 2] Supports XGETBV with ECX = 1 if set.
2050 /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
2053 UINT32 Reserved
: 28;
2056 /// All bit fields as a 32-bit value
2059 } CPUID_EXTENDED_STATE_SUB_LEAF_EAX
;
2062 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
2063 sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
2067 /// Individual bit fields
2071 /// [Bits 7:0] Used for XCR0.
2075 /// [Bit 8] PT STate.
2079 /// [Bit 9] Used for XCR0.
2082 UINT32 Reserved1
: 3;
2084 /// [Bit 13] HWP state.
2086 UINT32 HWPState
: 1;
2087 UINT32 Reserved8
: 18;
2090 /// All bit fields as a 32-bit value
2093 } CPUID_EXTENDED_STATE_SUB_LEAF_ECX
;
2096 CPUID Extended State Information Size and Offset Sub Leaf
2099 Leaf 0DH output depends on the initial value in ECX.
2100 Each sub-leaf index (starting at position 2) is supported if it corresponds to
2101 a supported bit in either the XCR0 register or the IA32_XSS MSR.
2102 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
2103 n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1
2104 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0
2105 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
2107 @param EAX CPUID_EXTENDED_STATE (0x0D)
2108 @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based
2109 on supported bits in XCR0 or IA32_XSS_MSR.
2111 @retval EAX The size in bytes (from the offset specified in EBX) of the save
2112 area for an extended state feature associated with a valid
2114 @retval EBX The offset in bytes of this extended state component's save area
2115 from the beginning of the XSAVE/XRSTOR area. This field reports
2116 0 if the sub-leaf index, n, does not map to a valid bit in the
2118 @retval ECX The format of the extended state components's save area as
2119 described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.
2120 This field reports 0 if the sub-leaf index, n, is invalid.
2121 @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;
2122 otherwise it is reserved.
2124 <b>Example usage</b>
2128 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;
2132 for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
2134 CPUID_EXTENDED_STATE, SubLeaf,
2135 &Eax, &Ebx, &Ecx.Uint32, &Edx
2140 #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02
2143 CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
2144 sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.
2148 /// Individual bit fields
2152 /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is
2153 /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
2158 /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
2159 /// this extended state component located on the next 64-byte boundary
2160 /// following the preceding state component (otherwise, it is located
2161 /// immediately following the preceding state component).
2163 UINT32 Compacted
: 1;
2164 UINT32 Reserved
: 30;
2167 /// All bit fields as a 32-bit value
2170 } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
;
2173 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
2175 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
2176 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).
2177 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).
2180 #define CPUID_INTEL_RDT_MONITORING 0x0F
2183 CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
2184 Enumeration Sub-leaf
2186 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
2187 @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)
2189 @retval EAX Reserved.
2190 @retval EBX Maximum range (zero-based) of RMID within this physical
2191 processor of all types.
2192 @retval ECX Reserved.
2193 @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by
2194 the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.
2196 <b>Example usage</b>
2199 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
2202 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
2203 NULL, &Ebx, NULL, &Edx.Uint32
2207 #define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00
2210 CPUID Intel RDT Monitoring Information EDX for CPUID leaf
2211 #CPUID_INTEL_RDT_MONITORING, sub-leaf
2212 #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.
2216 /// Individual bit fields
2219 UINT32 Reserved1
: 1;
2221 /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.
2223 UINT32 L3CacheRDT_M
: 1;
2224 UINT32 Reserved2
: 30;
2227 /// All bit fields as a 32-bit value
2230 } CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX
;
2233 CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf
2235 @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)
2236 @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)
2238 @retval EAX Reserved.
2239 @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
2240 @retval ECX Maximum range (zero-based) of RMID of this resource type.
2241 @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the
2242 type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.
2244 <b>Example usage</b>
2248 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;
2251 CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
2252 NULL, &Ebx, &Ecx, &Edx.Uint32
2256 #define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01
2259 CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf
2260 #CPUID_INTEL_RDT_MONITORING, sub-leaf
2261 #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.
2265 /// Individual bit fields
2269 /// [Bit 0] Supports L3 occupancy monitoring if 1.
2271 UINT32 L3CacheOccupancyMonitoring
: 1;
2273 /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.
2275 UINT32 L3CacheTotalBandwidthMonitoring
: 1;
2277 /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.
2279 UINT32 L3CacheLocalBandwidthMonitoring
: 1;
2280 UINT32 Reserved
: 29;
2283 /// All bit fields as a 32-bit value
2286 } CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
;
2289 CPUID Intel Resource Director Technology (Intel RDT) Allocation Information
2291 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10).
2292 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
2293 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).
2294 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).
2296 #define CPUID_INTEL_RDT_ALLOCATION 0x10
2299 Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf
2301 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2302 @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
2304 @retval EAX Reserved.
2305 @retval EBX L3 and L2 Cache Allocation Technology information described by
2306 the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.
2307 @retval ECX Reserved.
2308 @retval EDX Reserved.
2310 <b>Example usage</b>
2312 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;
2315 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
2316 NULL, &Ebx.Uint32, NULL, NULL
2320 #define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00
2323 CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf
2324 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2325 #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.
2329 /// Individual bit fields
2332 UINT32 Reserved1
: 1;
2334 /// [Bit 1] Supports L3 Cache Allocation Technology if 1.
2336 UINT32 L3CacheAllocation
: 1;
2338 /// [Bit 2] Supports L2 Cache Allocation Technology if 1.
2340 UINT32 L2CacheAllocation
: 1;
2342 /// [Bit 3] Supports Memory Bandwidth Allocation if 1.
2344 UINT32 MemoryBandwidth
: 1;
2345 UINT32 Reserved3
: 28;
2348 /// All bit fields as a 32-bit value
2351 } CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
;
2354 L3 Cache Allocation Technology Enumeration Sub-leaf
2356 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2357 @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)
2359 @retval EAX RESID L3 Cache Allocation Technology information described by
2360 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.
2361 @retval EBX Bit-granular map of isolation/contention of allocation units.
2362 @retval ECX RESID L3 Cache Allocation Technology information described by
2363 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.
2364 @retval EDX RESID L3 Cache Allocation Technology information described by
2365 the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.
2367 <b>Example usage</b>
2369 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;
2371 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;
2372 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
2375 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
2376 &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
2380 #define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01
2383 CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf
2384 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2385 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
2389 /// Individual bit fields
2393 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
2394 /// using minus-one notation.
2396 UINT32 CapacityLength
: 5;
2397 UINT32 Reserved
: 27;
2400 /// All bit fields as a 32-bit value
2403 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX
;
2406 CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf
2407 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2408 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
2412 /// Individual bit fields
2415 UINT32 Reserved3
: 2;
2417 /// [Bit 2] Code and Data Prioritization Technology supported if 1.
2419 UINT32 CodeDataPrioritization
: 1;
2420 UINT32 Reserved2
: 29;
2423 /// All bit fields as a 32-bit value
2426 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
;
2429 CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf
2430 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2431 #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
2435 /// Individual bit fields
2439 /// [Bits 15:0] Highest COS number supported for this ResID.
2441 UINT32 HighestCosNumber
: 16;
2442 UINT32 Reserved
: 16;
2445 /// All bit fields as a 32-bit value
2448 } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX
;
2451 L2 Cache Allocation Technology Enumeration Sub-leaf
2453 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2454 @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)
2456 @retval EAX RESID L2 Cache Allocation Technology information described by
2457 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.
2458 @retval EBX Bit-granular map of isolation/contention of allocation units.
2459 @retval ECX Reserved.
2460 @retval EDX RESID L2 Cache Allocation Technology information described by
2461 the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.
2463 <b>Example usage</b>
2465 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;
2467 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
2470 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
2471 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2475 #define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02
2478 CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf
2479 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2480 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
2484 /// Individual bit fields
2488 /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
2489 /// using minus-one notation.
2491 UINT32 CapacityLength
: 5;
2492 UINT32 Reserved
: 27;
2495 /// All bit fields as a 32-bit value
2498 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX
;
2501 CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf
2502 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2503 #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
2507 /// Individual bit fields
2511 /// [Bits 15:0] Highest COS number supported for this ResID.
2513 UINT32 HighestCosNumber
: 16;
2514 UINT32 Reserved
: 16;
2517 /// All bit fields as a 32-bit value
2520 } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX
;
2523 Memory Bandwidth Allocation Enumeration Sub-leaf
2525 @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)
2526 @param ECX CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03)
2528 @retval EAX RESID memory bandwidth Allocation Technology information
2529 described by the type
2530 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX.
2531 @retval EBX Reserved.
2532 @retval ECX RESID memory bandwidth Allocation Technology information
2533 described by the type
2534 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX.
2535 @retval EDX RESID memory bandwidth Allocation Technology information
2536 described by the type
2537 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX.
2539 <b>Example usage</b>
2541 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax;
2543 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx;
2544 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;
2548 CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,
2549 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2553 #define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03
2556 CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf
2557 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2558 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
2562 /// Individual bit fields
2566 /// [Bits 11:0] Reports the maximum MBA throttling value supported for
2567 /// the corresponding ResID using minus-one notation.
2569 UINT32 MaximumMBAThrottling
: 12;
2570 UINT32 Reserved
: 20;
2573 /// All bit fields as a 32-bit value
2576 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX
;
2579 CPUID memory bandwidth Allocation Technology Information ECX for CPUID leaf
2580 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2581 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
2585 /// Individual bit fields
2589 /// [Bits 1:0] Reserved.
2591 UINT32 Reserved1
: 2;
2593 /// [Bits 3] Reports whether the response of the delay values is linear.
2596 UINT32 Reserved2
: 29;
2599 /// All bit fields as a 32-bit value
2602 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX
;
2605 CPUID memory bandwidth Allocation Technology Information EDX for CPUID leaf
2606 #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
2607 #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
2611 /// Individual bit fields
2615 /// [Bits 15:0] Highest COS number supported for this ResID.
2617 UINT32 HighestCosNumber
: 16;
2618 UINT32 Reserved
: 16;
2621 /// All bit fields as a 32-bit value
2624 } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX
;
2627 Intel SGX resource capability and configuration.
2628 See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".
2630 If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying
2631 CPUID with EAX=12H on Intel SGX resource capability and configuration.
2633 @param EAX CPUID_INTEL_SGX (0x12)
2634 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).
2635 CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).
2636 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).
2637 Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])
2638 until the sub-leaf type is invalid.
2641 #define CPUID_INTEL_SGX 0x12
2644 Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
2645 Enumerates Intel SGX capability, including enclave instruction opcode support.
2647 @param EAX CPUID_INTEL_SGX (0x12)
2648 @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)
2650 @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
2651 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.
2652 @retval EBX MISCSELECT: Reports the bit vector of supported extended features
2653 that can be written to the MISC region of the SSA.
2654 @retval ECX Reserved.
2655 @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
2656 described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.
2658 <b>Example usage</b>
2660 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;
2662 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
2665 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
2666 &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
2670 #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00
2673 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,
2674 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
2678 /// Individual bit fields
2682 /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.
2686 /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.
2689 UINT32 Reserved1
: 3;
2691 /// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves
2692 /// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT.
2696 /// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC,
2697 /// ERDINFO, ELDBC, and ELDUC.
2700 UINT32 Reserved2
: 25;
2703 /// All bit fields as a 32-bit value
2706 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
;
2709 Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,
2710 sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
2714 /// Individual bit fields
2718 /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes
2719 /// when not in 64-bit mode.
2721 UINT32 MaxEnclaveSize_Not64
: 8;
2723 /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes
2724 /// when operating in 64-bit mode.
2726 UINT32 MaxEnclaveSize_64
: 8;
2727 UINT32 Reserved
: 16;
2730 /// All bit fields as a 32-bit value
2733 } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX
;
2736 Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
2737 Enumerates Intel SGX capability of processor state configuration and enclave
2738 configuration in the SECS structure.
2740 @param EAX CPUID_INTEL_SGX (0x12)
2741 @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)
2743 @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can
2744 set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE
2745 only if EAX[n] is 1, where n < 32.
2746 @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can
2747 set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE
2748 only if EBX[n] is 1, where n < 32.
2749 @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can
2750 set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE
2751 only if ECX[n] is 1, where n < 32.
2752 @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can
2753 set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE
2754 only if EDX[n] is 1, where n < 32.
2756 <b>Example usage</b>
2764 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
2765 &Eax, &Ebx, &Ecx, &Edx
2769 #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01
2772 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
2773 Enumerates available EPC resources.
2775 @param EAX CPUID_INTEL_SGX (0x12)
2776 @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)
2778 @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2779 Resources is described by the type
2780 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.
2781 @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2782 Resources is described by the type
2783 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.
2784 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2785 Resources is described by the type
2786 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.
2787 @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
2788 Resources is described by the type
2789 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.
2791 <b>Example usage</b>
2793 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;
2794 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;
2795 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;
2796 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;
2799 CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,
2800 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
2804 #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02
2807 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID
2808 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2812 /// Individual bit fields
2816 /// [Bit 3:0] Sub-leaf-type encoding.
2817 /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.
2818 /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)
2819 /// in EBX:EAX and EDX:ECX.
2820 /// All other encoding are reserved.
2822 UINT32 SubLeafType
: 4;
2823 UINT32 Reserved
: 8;
2825 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of
2826 /// the base of the EPC section.
2828 UINT32 LowAddressOfEpcSection
: 20;
2831 /// All bit fields as a 32-bit value
2834 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX
;
2837 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID
2838 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2842 /// Individual bit fields
2846 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of
2847 /// the base of the EPC section.
2849 UINT32 HighAddressOfEpcSection
: 20;
2850 UINT32 Reserved
: 12;
2853 /// All bit fields as a 32-bit value
2856 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX
;
2859 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID
2860 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2864 /// Individual bit fields
2868 /// [Bit 3:0] The EPC section encoding.
2869 /// 0000b: Not valid.
2870 /// 0001b: The EPC section is confidentiality, integrity and replay protected.
2871 /// All other encoding are reserved.
2873 UINT32 EpcSection
: 4;
2874 UINT32 Reserved
: 8;
2876 /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the
2877 /// corresponding EPC section within the Processor Reserved Memory.
2879 UINT32 LowSizeOfEpcSection
: 20;
2882 /// All bit fields as a 32-bit value
2885 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX
;
2888 Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID
2889 leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
2893 /// Individual bit fields
2897 /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the
2898 /// corresponding EPC section within the Processor Reserved Memory.
2900 UINT32 HighSizeOfEpcSection
: 20;
2901 UINT32 Reserved
: 12;
2904 /// All bit fields as a 32-bit value
2907 } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX
;
2910 CPUID Intel Processor Trace Information
2912 @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)
2913 @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).
2914 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
2917 #define CPUID_INTEL_PROCESSOR_TRACE 0x14
2920 CPUID Intel Processor Trace Information Main Leaf
2922 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
2923 @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)
2925 @retval EAX Reports the maximum sub-leaf supported in leaf 14H.
2926 @retval EBX Returns Intel processor trace information described by the
2927 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.
2928 @retval ECX Returns Intel processor trace information described by the
2929 type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.
2930 @retval EDX Reserved.
2932 <b>Example usage</b>
2935 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;
2936 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
2939 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
2940 &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
2944 #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00
2947 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2948 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
2952 /// Individual bit fields
2956 /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
2957 /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
2959 UINT32 Cr3Filter
: 1;
2961 /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate
2964 UINT32 ConfigurablePsb
: 1;
2966 /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,
2967 /// and preservation of Intel PT MSRs across warm reset.
2969 UINT32 IpTraceStopFiltering
: 1;
2971 /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of
2972 /// COFI-based packets.
2976 /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set
2977 /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE
2978 /// can generate packets.
2982 /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set
2983 /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet
2986 UINT32 PowerEventTrace
: 1;
2987 UINT32 Reserved
: 26;
2990 /// All bit fields as a 32-bit value
2993 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
;
2996 CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
2997 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
3001 /// Individual bit fields
3005 /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence
3006 /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
3007 /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
3011 /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
3012 /// the maximum allowed by the MaskOrTableOffset field of
3013 /// IA32_RTIT_OUTPUT_MASK_PTRS.
3017 /// [Bit 2] If 1, indicates support of Single-Range Output scheme.
3019 UINT32 SingleRangeOutput
: 1;
3021 /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.
3023 UINT32 TraceTransportSubsystem
: 1;
3024 UINT32 Reserved
: 27;
3026 /// [Bit 31] If 1, generated packets which contain IP payloads have LIP
3027 /// values, which include the CS base component.
3032 /// All bit fields as a 32-bit value
3035 } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
;
3038 CPUID Intel Processor Trace Information Sub-leaf
3040 @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
3041 @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)
3043 @retval EAX Returns Intel processor trace information described by the
3044 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.
3045 @retval EBX Returns Intel processor trace information described by the
3046 type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.
3047 @retval ECX Reserved.
3048 @retval EDX Reserved.
3050 <b>Example usage</b>
3052 UINT32 MaximumSubLeaf;
3054 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;
3055 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;
3058 CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
3059 &MaximumSubLeaf, NULL, NULL, NULL
3062 for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
3064 CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
3065 &Eax.Uint32, &Ebx.Uint32, NULL, NULL
3070 #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01
3073 CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
3074 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
3078 /// Individual bit fields
3082 /// [Bits 2:0] Number of configurable Address Ranges for filtering.
3084 UINT32 ConfigurableAddressRanges
: 3;
3085 UINT32 Reserved
: 13;
3087 /// [Bits 31:16] Bitmap of supported MTC period encodings
3089 UINT32 MtcPeriodEncodings
: 16;
3092 /// All bit fields as a 32-bit value
3095 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
;
3098 CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
3099 sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
3103 /// Individual bit fields
3107 /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
3109 UINT32 CycleThresholdEncodings
: 16;
3111 /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
3113 UINT32 PsbFrequencyEncodings
: 16;
3116 /// All bit fields as a 32-bit value
3119 } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
;
3122 CPUID Time Stamp Counter and Nominal Core Crystal Clock Information
3125 If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
3126 EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core
3127 crystal clock frequency.
3128 If ECX is 0, the nominal core crystal clock frequency is not enumerated.
3129 "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
3130 The core crystal clock may differ from the reference clock, bus clock, or core
3133 @param EAX CPUID_TIME_STAMP_COUNTER (0x15)
3135 @retval EAX An unsigned integer which is the denominator of the
3136 TSC/"core crystal clock" ratio
3137 @retval EBX An unsigned integer which is the numerator of the
3138 TSC/"core crystal clock" ratio.
3139 @retval ECX An unsigned integer which is the nominal frequency
3140 of the core crystal clock in Hz.
3141 @retval EDX Reserved.
3143 <b>Example usage</b>
3149 AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
3152 #define CPUID_TIME_STAMP_COUNTER 0x15
3155 CPUID Processor Frequency Information
3158 Data is returned from this interface in accordance with the processor's
3159 specification and does not reflect actual values. Suitable use of this data
3160 includes the display of processor information in like manner to the processor
3161 brand string and for determining the appropriate range to use when displaying
3162 processor information e.g. frequency history graphs. The returned information
3163 should not be used for any other purpose as the returned information does not
3164 accurately correlate to information / counters returned by other processor
3165 interfaces. While a processor may support the Processor Frequency Information
3166 leaf, fields that return a value of zero are not supported.
3168 @param EAX CPUID_TIME_STAMP_COUNTER (0x16)
3170 @retval EAX Returns processor base frequency information described by the
3171 type CPUID_PROCESSOR_FREQUENCY_EAX.
3172 @retval EBX Returns maximum frequency information described by the type
3173 CPUID_PROCESSOR_FREQUENCY_EBX.
3174 @retval ECX Returns bus frequency information described by the type
3175 CPUID_PROCESSOR_FREQUENCY_ECX.
3176 @retval EDX Reserved.
3178 <b>Example usage</b>
3180 CPUID_PROCESSOR_FREQUENCY_EAX Eax;
3181 CPUID_PROCESSOR_FREQUENCY_EBX Ebx;
3182 CPUID_PROCESSOR_FREQUENCY_ECX Ecx;
3184 AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
3187 #define CPUID_PROCESSOR_FREQUENCY 0x16
3190 CPUID Processor Frequency Information EAX for CPUID leaf
3191 #CPUID_PROCESSOR_FREQUENCY.
3195 /// Individual bit fields
3199 /// [Bits 15:0] Processor Base Frequency (in MHz).
3201 UINT32 ProcessorBaseFrequency
: 16;
3202 UINT32 Reserved
: 16;
3205 /// All bit fields as a 32-bit value
3208 } CPUID_PROCESSOR_FREQUENCY_EAX
;
3211 CPUID Processor Frequency Information EBX for CPUID leaf
3212 #CPUID_PROCESSOR_FREQUENCY.
3216 /// Individual bit fields
3220 /// [Bits 15:0] Maximum Frequency (in MHz).
3222 UINT32 MaximumFrequency
: 16;
3223 UINT32 Reserved
: 16;
3226 /// All bit fields as a 32-bit value
3229 } CPUID_PROCESSOR_FREQUENCY_EBX
;
3232 CPUID Processor Frequency Information ECX for CPUID leaf
3233 #CPUID_PROCESSOR_FREQUENCY.
3237 /// Individual bit fields
3241 /// [Bits 15:0] Bus (Reference) Frequency (in MHz).
3243 UINT32 BusFrequency
: 16;
3244 UINT32 Reserved
: 16;
3247 /// All bit fields as a 32-bit value
3250 } CPUID_PROCESSOR_FREQUENCY_ECX
;
3253 CPUID SoC Vendor Information
3255 @param EAX CPUID_SOC_VENDOR (0x17)
3256 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
3257 CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
3258 CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)
3259 CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)
3262 Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String
3263 is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC
3264 Vendor Brand String is constructed by concatenating in ascending order of
3265 EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
3268 #define CPUID_SOC_VENDOR 0x17
3271 CPUID SoC Vendor Information
3273 @param EAX CPUID_SOC_VENDOR (0x17)
3274 @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
3276 @retval EAX MaxSOCID_Index. Reports the maximum input value of supported
3277 sub-leaf in leaf 17H.
3278 @retval EBX Returns SoC Vendor information described by the type
3279 CPUID_SOC_VENDOR_MAIN_LEAF_EBX.
3280 @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC
3282 @retval EDX Stepping ID. A unique number within an SOC project that an SOC
3285 <b>Example usage</b>
3288 CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;
3293 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,
3294 &Eax, &Ebx.Uint32, &Ecx, &Edx
3298 #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00
3301 CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf
3302 #CPUID_SOC_VENDOR_MAIN_LEAF.
3306 /// Individual bit fields
3310 /// [Bits 15:0] SOC Vendor ID.
3312 UINT32 SocVendorId
: 16;
3314 /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry
3315 /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is
3316 /// assigned by Intel.
3318 UINT32 IsVendorScheme
: 1;
3319 UINT32 Reserved
: 15;
3322 /// All bit fields as a 32-bit value
3325 } CPUID_SOC_VENDOR_MAIN_LEAF_EBX
;
3328 CPUID SoC Vendor Information
3330 @param EAX CPUID_SOC_VENDOR (0x17)
3331 @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
3333 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3334 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3335 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3336 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3337 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3338 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3339 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3340 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3342 <b>Example usage</b>
3344 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3345 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3346 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3347 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3350 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,
3351 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3355 #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01
3358 CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,
3359 #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.
3363 /// 4 UTF-8 characters of Soc Vendor Brand String
3365 CHAR8 BrandString
[4];
3367 /// All fields as a 32-bit value
3370 } CPUID_SOC_VENDOR_BRAND_STRING_DATA
;
3373 CPUID SoC Vendor Information
3375 @param EAX CPUID_SOC_VENDOR (0x17)
3376 @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)
3378 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3379 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3380 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3381 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3382 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3383 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3384 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3385 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3387 <b>Example usage</b>
3389 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3390 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3391 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3392 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3395 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,
3396 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3400 #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02
3403 CPUID SoC Vendor Information
3405 @param EAX CPUID_SOC_VENDOR (0x17)
3406 @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)
3408 @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type
3409 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3410 @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type
3411 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3412 @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type
3413 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3414 @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type
3415 CPUID_SOC_VENDOR_BRAND_STRING_DATA.
3417 <b>Example usage</b>
3419 CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;
3420 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;
3421 CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;
3422 CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;
3425 CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,
3426 &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
3430 #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03
3433 CPUID Deterministic Address Translation Parameters
3436 Each sub-leaf enumerates a different address translation structure.
3437 If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
3438 index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A
3439 sub-leaf index is also invalid if EDX[4:0] returns 0.
3440 Valid sub-leaves do not need to be contiguous or in any particular order. A
3441 valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or
3442 than a valid sub-leaf of a higher or lower-level structure.
3443 * Some unified TLBs will allow a single TLB entry to satisfy data read/write
3444 and instruction fetches. Others will require separate entries (e.g., one
3445 loaded on data read/write and another loaded on an instruction fetch).
3446 Please see the Intel 64 and IA-32 Architectures Optimization Reference Manual
3447 for details of a particular product.
3448 ** Add one to the return value to get the result.
3450 @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)
3451 @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)
3452 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*)
3455 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18
3458 CPUID Deterministic Address Translation Parameters
3460 @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)
3461 @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)
3463 @retval EAX Reports the maximum input value of supported sub-leaf in leaf 18H.
3464 @retval EBX Returns Deterministic Address Translation Parameters described by
3465 the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX.
3466 @retval ECX Number of Sets.
3467 @retval EDX Returns Deterministic Address Translation Parameters described by
3468 the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.
3470 <b>Example usage</b>
3473 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx;
3475 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx;
3478 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,
3479 CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,
3480 &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32
3484 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00
3487 CPUID Deterministic Address Translation Parameters EBX for CPUID leafs.
3491 /// Individual bit fields
3495 /// [Bits 0] 4K page size entries supported by this structure.
3499 /// [Bits 1] 2MB page size entries supported by this structure.
3503 /// [Bits 2] 4MB page size entries supported by this structure.
3507 /// [Bits 3] 1 GB page size entries supported by this structure.
3511 /// [Bits 7:4] Reserved.
3513 UINT32 Reserved1
: 4;
3515 /// [Bits 10:8] Partitioning (0: Soft partitioning between the logical
3516 /// processors sharing this structure)
3518 UINT32 Partitioning
: 3;
3520 /// [Bits 15:11] Reserved.
3522 UINT32 Reserved2
: 5;
3524 /// [Bits 31:16] W = Ways of associativity.
3529 /// All bit fields as a 32-bit value
3532 } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX
;
3535 CPUID Deterministic Address Translation Parameters EDX for CPUID leafs.
3539 /// Individual bit fields
3543 /// [Bits 4:0] Translation cache type field.
3545 UINT32 TranslationCacheType
: 5;
3547 /// [Bits 7:5] Translation cache level (starts at 1).
3549 UINT32 TranslationCacheLevel
: 3;
3551 /// [Bits 8] Fully associative structure.
3553 UINT32 FullyAssociative
: 1;
3555 /// [Bits 13:9] Reserved.
3557 UINT32 Reserved1
: 5;
3559 /// [Bits 25:14] Maximum number of addressable IDs for logical
3560 /// processors sharing this translation cache.
3562 UINT32 MaximumNum
: 12;
3564 /// [Bits 31:26] Reserved.
3566 UINT32 Reserved2
: 6;
3569 /// All bit fields as a 32-bit value
3572 } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX
;
3575 /// @{ Define value for CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.TranslationCacheType
3577 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID 0x00
3578 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB 0x01
3579 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB 0x02
3580 #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB 0x03
3586 CPUID Hybrid Information Enumeration Leaf
3588 @param EAX CPUID_HYBRID_INFORMATION (0x1A)
3589 @param ECX CPUID_HYBRID_INFORMATION_MAIN_LEAF (0x00).
3591 @retval EAX Enumerates the native model ID and core type described
3592 by the type CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX
3593 @retval EBX Reserved.
3594 @retval ECX Reserved.
3595 @retval EDX Reserved.
3597 <b>Example usage</b>
3599 CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX Eax;
3602 CPUID_HYBRID_INFORMATION,
3603 CPUID_HYBRID_INFORMATION_MAIN_LEAF,
3604 &Eax, NULL, NULL, NULL
3609 #define CPUID_HYBRID_INFORMATION 0x1A
3612 /// CPUID Hybrid Information Enumeration main leaf
3614 #define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00
3617 CPUID Hybrid Information EAX for CPUID leaf #CPUID_HYBRID_INFORMATION,
3618 main leaf #CPUID_HYBRID_INFORMATION_MAIN_LEAF.
3622 /// Individual bit fields
3626 /// [Bit 23:0] Native model ID of the core.
3628 /// The core-type and native mode ID can be used to uniquely identify
3629 /// the microarchitecture of the core.This native model ID is not unique
3630 /// across core types, and not related to the model ID reported in CPUID
3631 /// leaf 01H, and does not identify the SOC.
3633 UINT32 NativeModelId
: 24;
3635 /// [Bit 31:24] Core type
3637 UINT32 CoreType
: 8;
3640 /// All bit fields as a 32-bit value
3643 } CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX
;
3646 /// @{ Define value for CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX.CoreType
3648 #define CPUID_CORE_TYPE_INTEL_ATOM 0x20
3649 #define CPUID_CORE_TYPE_INTEL_CORE 0x40
3655 CPUID V2 Extended Topology Enumeration Leaf
3658 CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking
3659 for the existence of Leaf 1FH and using this if available.
3660 Most of Leaf 1FH output depends on the initial value in ECX. The EDX output of leaf
3661 1FH is always valid and does not vary with input value in ECX. Output value in ECX[7:0]
3662 always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each
3663 subsequent higher sub-leaf index enumerates a higher-level topological entity in
3664 hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8];
3665 EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of
3666 0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8].
3668 Software should use this field (EAX[4:0]) to enumerate processor topology of the system.
3669 Software must not use EBX[15:0] to enumerate processor topology of the system. This value
3670 in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual
3671 number of logical processors available to BIOS/OS/Applications may be different from the
3672 value of EBX[15:0], depending on software and platform hardware configurations.
3674 @param EAX CPUID_V2_EXTENDED_TOPOLOGY (0x1F)
3675 @param ECX Level number
3678 #define CPUID_V2_EXTENDED_TOPOLOGY 0x1F
3681 /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
3682 /// The value of the "level type" field is not related to level numbers in
3683 /// any way, higher "level type" values do not mean higher levels.
3685 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03
3686 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04
3687 #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05
3693 CPUID Extended Function
3695 @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)
3697 @retval EAX Maximum Input Value for Extended Function CPUID Information.
3698 @retval EBX Reserved.
3699 @retval ECX Reserved.
3700 @retval EDX Reserved.
3702 <b>Example usage</b>
3706 AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
3709 #define CPUID_EXTENDED_FUNCTION 0x80000000
3712 CPUID Extended Processor Signature and Feature Bits
3714 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
3716 @retval EAX CPUID_EXTENDED_CPU_SIG.
3717 @retval EBX Reserved.
3718 @retval ECX Extended Processor Signature and Feature Bits information
3719 described by the type CPUID_EXTENDED_CPU_SIG_ECX.
3720 @retval EDX Extended Processor Signature and Feature Bits information
3721 described by the type CPUID_EXTENDED_CPU_SIG_EDX.
3723 <b>Example usage</b>
3726 CPUID_EXTENDED_CPU_SIG_ECX Ecx;
3727 CPUID_EXTENDED_CPU_SIG_EDX Edx;
3729 AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
3732 #define CPUID_EXTENDED_CPU_SIG 0x80000001
3735 CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf
3736 #CPUID_EXTENDED_CPU_SIG.
3740 /// Individual bit fields
3744 /// [Bit 0] LAHF/SAHF available in 64-bit mode.
3746 UINT32 LAHF_SAHF
: 1;
3747 UINT32 Reserved1
: 4;
3752 UINT32 Reserved2
: 2;
3754 /// [Bit 8] PREFETCHW.
3756 UINT32 PREFETCHW
: 1;
3757 UINT32 Reserved3
: 23;
3760 /// All bit fields as a 32-bit value
3763 } CPUID_EXTENDED_CPU_SIG_ECX
;
3766 CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf
3767 #CPUID_EXTENDED_CPU_SIG.
3771 /// Individual bit fields
3774 UINT32 Reserved1
: 11;
3776 /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.
3778 UINT32 SYSCALL_SYSRET
: 1;
3779 UINT32 Reserved2
: 8;
3781 /// [Bit 20] Execute Disable Bit available.
3784 UINT32 Reserved3
: 5;
3786 /// [Bit 26] 1-GByte pages are available if 1.
3790 /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.
3793 UINT32 Reserved4
: 1;
3795 /// [Bit 29] Intel(R) 64 Architecture available if 1.
3798 UINT32 Reserved5
: 2;
3801 /// All bit fields as a 32-bit value
3804 } CPUID_EXTENDED_CPU_SIG_EDX
;
3807 CPUID Processor Brand String
3809 @param EAX CPUID_BRAND_STRING1 (0x80000002)
3811 @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.
3812 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3813 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3814 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3816 <b>Example usage</b>
3818 CPUID_BRAND_STRING_DATA Eax;
3819 CPUID_BRAND_STRING_DATA Ebx;
3820 CPUID_BRAND_STRING_DATA Ecx;
3821 CPUID_BRAND_STRING_DATA Edx;
3823 AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3826 #define CPUID_BRAND_STRING1 0x80000002
3829 CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,
3830 #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.
3834 /// 4 ASCII characters of Processor Brand String
3836 CHAR8 BrandString
[4];
3838 /// All fields as a 32-bit value
3841 } CPUID_BRAND_STRING_DATA
;
3844 CPUID Processor Brand String
3846 @param EAX CPUID_BRAND_STRING2 (0x80000003)
3848 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3849 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3850 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3851 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3853 <b>Example usage</b>
3855 CPUID_BRAND_STRING_DATA Eax;
3856 CPUID_BRAND_STRING_DATA Ebx;
3857 CPUID_BRAND_STRING_DATA Ecx;
3858 CPUID_BRAND_STRING_DATA Edx;
3860 AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3863 #define CPUID_BRAND_STRING2 0x80000003
3866 CPUID Processor Brand String
3868 @param EAX CPUID_BRAND_STRING3 (0x80000004)
3870 @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3871 @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3872 @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3873 @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
3875 <b>Example usage</b>
3877 CPUID_BRAND_STRING_DATA Eax;
3878 CPUID_BRAND_STRING_DATA Ebx;
3879 CPUID_BRAND_STRING_DATA Ecx;
3880 CPUID_BRAND_STRING_DATA Edx;
3882 AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
3885 #define CPUID_BRAND_STRING3 0x80000004
3888 CPUID Extended Cache information
3890 @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)
3892 @retval EAX Reserved.
3893 @retval EBX Reserved.
3894 @retval ECX Extended cache information described by the type
3895 CPUID_EXTENDED_CACHE_INFO_ECX.
3896 @retval EDX Reserved.
3898 <b>Example usage</b>
3900 CPUID_EXTENDED_CACHE_INFO_ECX Ecx;
3902 AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
3905 #define CPUID_EXTENDED_CACHE_INFO 0x80000006
3908 CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.
3912 /// Individual bit fields
3916 /// [Bits 7:0] Cache line size in bytes.
3918 UINT32 CacheLineSize
: 8;
3919 UINT32 Reserved
: 4;
3921 /// [Bits 15:12] L2 Associativity field. Supported values are in the range
3922 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to
3923 /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL
3925 UINT32 L2Associativity
: 4;
3927 /// [Bits 31:16] Cache size in 1K units.
3929 UINT32 CacheSize
: 16;
3932 /// All bit fields as a 32-bit value
3935 } CPUID_EXTENDED_CACHE_INFO_ECX
;
3938 /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity
3940 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00
3941 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01
3942 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02
3943 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04
3944 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06
3945 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08
3946 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY 0x0A
3947 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY 0x0B
3948 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY 0x0C
3949 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY 0x0D
3950 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY 0x0E
3951 #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F
3957 CPUID Extended Time Stamp Counter information
3959 @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)
3961 @retval EAX Reserved.
3962 @retval EBX Reserved.
3963 @retval ECX Reserved.
3964 @retval EDX Extended time stamp counter (TSC) information described by the
3965 type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.
3967 <b>Example usage</b>
3969 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;
3971 AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
3974 #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007
3977 CPUID Extended Time Stamp Counter information EDX for CPUID leaf
3978 #CPUID_EXTENDED_TIME_STAMP_COUNTER.
3982 /// Individual bit fields
3985 UINT32 Reserved1
: 8;
3987 /// [Bit 8] Invariant TSC available if 1.
3989 UINT32 InvariantTsc
: 1;
3990 UINT32 Reserved2
: 23;
3993 /// All bit fields as a 32-bit value
3996 } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX
;
3999 CPUID Linear Physical Address Size
4001 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
4003 @retval EAX Linear/Physical Address Size described by the type
4004 CPUID_VIR_PHY_ADDRESS_SIZE_EAX.
4005 @retval EBX Reserved.
4006 @retval ECX Reserved.
4007 @retval EDX Reserved.
4009 <b>Example usage</b>
4011 CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;
4013 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
4016 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
4019 CPUID Linear Physical Address Size EAX for CPUID leaf
4020 #CPUID_VIR_PHY_ADDRESS_SIZE.
4024 /// Individual bit fields
4028 /// [Bits 7:0] Number of physical address bits.
4031 /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
4032 /// number supported should come from this field.
4034 UINT32 PhysicalAddressBits
: 8;
4036 /// [Bits 15:8] Number of linear address bits.
4038 UINT32 LinearAddressBits
: 8;
4039 UINT32 Reserved
: 16;
4042 /// All bit fields as a 32-bit value
4045 } CPUID_VIR_PHY_ADDRESS_SIZE_EAX
;
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