MdePkg/Include/Register/Intel/Msr/AtomMsr.h

   1 /** @file
   2   MSR Definitions for the Intel(R) Atom(TM) Processor Family.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __ATOM_MSR_H__
  19 #define __ATOM_MSR_H__
  20
  21 #include <Register/Intel/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Intel(R) Atom(TM) Processor Family?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x06 && \
  34    (                        \
  35     DisplayModel == 0x1C || \
  36     DisplayModel == 0x26 || \
  37     DisplayModel == 0x27 || \
  38     DisplayModel == 0x35 || \
  39     DisplayModel == 0x36    \
  40     )                       \
  41    )
  42
  43 /**
  44   Shared. Model Specific Platform ID (R).
  45
  46   @param  ECX  MSR_ATOM_PLATFORM_ID (0x00000017)
  47   @param  EAX  Lower 32-bits of MSR value.
  48                Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
  49   @param  EDX  Upper 32-bits of MSR value.
  50                Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
  51
  52   <b>Example usage</b>
  53   @code
  54   MSR_ATOM_PLATFORM_ID_REGISTER  Msr;
  55
  56   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
  57   @endcode
  58   @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
  59 **/
  60 #define MSR_ATOM_PLATFORM_ID  0x00000017
  61
  62 /**
  63   MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
  64 **/
  65 typedef union {
  66   ///
  67   /// Individual bit fields
  68   ///
  69   struct {
  70     UINT32    Reserved1             : 8;
  71     ///
  72     /// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
  73     ///
  74     UINT32    MaximumQualifiedRatio : 5;
  75     UINT32    Reserved2             : 19;
  76     UINT32    Reserved3             : 32;
  77   } Bits;
  78   ///
  79   /// All bit fields as a 32-bit value
  80   ///
  81   UINT32    Uint32;
  82   ///
  83   /// All bit fields as a 64-bit value
  84   ///
  85   UINT64    Uint64;
  86 } MSR_ATOM_PLATFORM_ID_REGISTER;
  87
  88 /**
  89   Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
  90   processor features; (R) indicates current processor configuration.
  91
  92   @param  ECX  MSR_ATOM_EBL_CR_POWERON (0x0000002A)
  93   @param  EAX  Lower 32-bits of MSR value.
  94                Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
  95   @param  EDX  Upper 32-bits of MSR value.
  96                Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
  97
  98   <b>Example usage</b>
  99   @code
 100   MSR_ATOM_EBL_CR_POWERON_REGISTER  Msr;
 101
 102   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
 103   AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
 104   @endcode
 105   @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 106 **/
 107 #define MSR_ATOM_EBL_CR_POWERON  0x0000002A
 108
 109 /**
 110   MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
 111 **/
 112 typedef union {
 113   ///
 114   /// Individual bit fields
 115   ///
 116   struct {
 117     UINT32    Reserved1                   : 1;
 118     ///
 119     /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
 120     /// Always 0.
 121     ///
 122     UINT32    DataErrorCheckingEnable     : 1;
 123     ///
 124     /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
 125     /// Always 0.
 126     ///
 127     UINT32    ResponseErrorCheckingEnable : 1;
 128     ///
 129     /// [Bit 3] AERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Always 0.
 130     ///
 131     UINT32    AERR_DriveEnable            : 1;
 132     ///
 133     /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
 134     /// Disabled Always 0.
 135     ///
 136     UINT32    BERR_Enable                 : 1;
 137     UINT32    Reserved2                   : 1;
 138     UINT32    Reserved3                   : 1;
 139     ///
 140     /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
 141     ///
 142     UINT32    BINIT_DriverEnable          : 1;
 143     UINT32    Reserved4                   : 1;
 144     ///
 145     /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
 146     ///
 147     UINT32    ExecuteBIST                 : 1;
 148     ///
 149     /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
 150     /// Always 0.
 151     ///
 152     UINT32    AERR_ObservationEnabled     : 1;
 153     UINT32    Reserved5                   : 1;
 154     ///
 155     /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
 156     /// Always 0.
 157     ///
 158     UINT32    BINIT_ObservationEnabled    : 1;
 159     UINT32    Reserved6                   : 1;
 160     ///
 161     /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
 162     ///
 163     UINT32    ResetVector                 : 1;
 164     UINT32    Reserved7                   : 1;
 165     ///
 166     /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
 167     ///
 168     UINT32    APICClusterID               : 2;
 169     UINT32    Reserved8                   : 2;
 170     ///
 171     /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
 172     ///
 173     UINT32    SymmetricArbitrationID      : 2;
 174     ///
 175     /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
 176     ///
 177     UINT32    IntegerBusFrequencyRatio    : 5;
 178     UINT32    Reserved9                   : 5;
 179     UINT32    Reserved10                  : 32;
 180   } Bits;
 181   ///
 182   /// All bit fields as a 32-bit value
 183   ///
 184   UINT32    Uint32;
 185   ///
 186   /// All bit fields as a 64-bit value
 187   ///
 188   UINT64    Uint64;
 189 } MSR_ATOM_EBL_CR_POWERON_REGISTER;
 190
 191 /**
 192   Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch
 193   record registers on the last branch record stack. The From_IP part of the
 194   stack contains pointers to the source instruction . See also: -  Last Branch
 195   Record Stack TOS at 1C9H -  Section 17.5.
 196
 197   @param  ECX  MSR_ATOM_LASTBRANCH_n_FROM_IP
 198   @param  EAX  Lower 32-bits of MSR value.
 199   @param  EDX  Upper 32-bits of MSR value.
 200
 201   <b>Example usage</b>
 202   @code
 203   UINT64  Msr;
 204
 205   Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
 206   AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
 207   @endcode
 208   @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
 209         MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
 210         MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
 211         MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
 212         MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
 213         MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
 214         MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
 215         MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
 216   @{
 217 **/
 218 #define MSR_ATOM_LASTBRANCH_0_FROM_IP  0x00000040
 219 #define MSR_ATOM_LASTBRANCH_1_FROM_IP  0x00000041
 220 #define MSR_ATOM_LASTBRANCH_2_FROM_IP  0x00000042
 221 #define MSR_ATOM_LASTBRANCH_3_FROM_IP  0x00000043
 222 #define MSR_ATOM_LASTBRANCH_4_FROM_IP  0x00000044
 223 #define MSR_ATOM_LASTBRANCH_5_FROM_IP  0x00000045
 224 #define MSR_ATOM_LASTBRANCH_6_FROM_IP  0x00000046
 225 #define MSR_ATOM_LASTBRANCH_7_FROM_IP  0x00000047
 226 /// @}
 227
 228 /**
 229   Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch
 230   record registers on the last branch record stack. The To_IP part of the
 231   stack contains pointers to the destination instruction.
 232
 233   @param  ECX  MSR_ATOM_LASTBRANCH_n_TO_IP
 234   @param  EAX  Lower 32-bits of MSR value.
 235   @param  EDX  Upper 32-bits of MSR value.
 236
 237   <b>Example usage</b>
 238   @code
 239   UINT64  Msr;
 240
 241   Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
 242   AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
 243   @endcode
 244   @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
 245         MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
 246         MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
 247         MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
 248         MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
 249         MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
 250         MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
 251         MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
 252   @{
 253 **/
 254 #define MSR_ATOM_LASTBRANCH_0_TO_IP  0x00000060
 255 #define MSR_ATOM_LASTBRANCH_1_TO_IP  0x00000061
 256 #define MSR_ATOM_LASTBRANCH_2_TO_IP  0x00000062
 257 #define MSR_ATOM_LASTBRANCH_3_TO_IP  0x00000063
 258 #define MSR_ATOM_LASTBRANCH_4_TO_IP  0x00000064
 259 #define MSR_ATOM_LASTBRANCH_5_TO_IP  0x00000065
 260 #define MSR_ATOM_LASTBRANCH_6_TO_IP  0x00000066
 261 #define MSR_ATOM_LASTBRANCH_7_TO_IP  0x00000067
 262 /// @}
 263
 264 /**
 265   Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
 266   bus clock speed for processors based on Intel Atom microarchitecture:.
 267
 268   @param  ECX  MSR_ATOM_FSB_FREQ (0x000000CD)
 269   @param  EAX  Lower 32-bits of MSR value.
 270                Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
 271   @param  EDX  Upper 32-bits of MSR value.
 272                Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
 273
 274   <b>Example usage</b>
 275   @code
 276   MSR_ATOM_FSB_FREQ_REGISTER  Msr;
 277
 278   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
 279   @endcode
 280   @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 281 **/
 282 #define MSR_ATOM_FSB_FREQ  0x000000CD
 283
 284 /**
 285   MSR information returned for MSR index #MSR_ATOM_FSB_FREQ
 286 **/
 287 typedef union {
 288   ///
 289   /// Individual bit fields
 290   ///
 291   struct {
 292     ///
 293     /// [Bits 2:0] - Scalable Bus Speed
 294     ///
 295     /// Atom Processor Family
 296     /// ---------------------
 297     ///   111B: 083 MHz (FSB 333)
 298     ///   101B: 100 MHz (FSB 400)
 299     ///   001B: 133 MHz (FSB 533)
 300     ///   011B: 167 MHz (FSB 667)
 301     ///
 302     /// 133.33 MHz should be utilized if performing calculation with
 303     /// System Bus Speed when encoding is 001B.
 304     /// 166.67 MHz should be utilized if performing calculation with
 305     /// System Bus Speed when
 306     /// encoding is 011B.
 307     ///
 308     UINT32    ScalableBusSpeed : 3;
 309     UINT32    Reserved1        : 29;
 310     UINT32    Reserved2        : 32;
 311   } Bits;
 312   ///
 313   /// All bit fields as a 32-bit value
 314   ///
 315   UINT32    Uint32;
 316   ///
 317   /// All bit fields as a 64-bit value
 318   ///
 319   UINT64    Uint64;
 320 } MSR_ATOM_FSB_FREQ_REGISTER;
 321
 322 /**
 323   Shared.
 324
 325   @param  ECX  MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
 326   @param  EAX  Lower 32-bits of MSR value.
 327                Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
 328   @param  EDX  Upper 32-bits of MSR value.
 329                Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
 330
 331   <b>Example usage</b>
 332   @code
 333   MSR_ATOM_BBL_CR_CTL3_REGISTER  Msr;
 334
 335   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
 336   AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
 337   @endcode
 338   @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 339 **/
 340 #define MSR_ATOM_BBL_CR_CTL3  0x0000011E
 341
 342 /**
 343   MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3
 344 **/
 345 typedef union {
 346   ///
 347   /// Individual bit fields
 348   ///
 349   struct {
 350     ///
 351     /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
 352     /// Indicates if the L2 is hardware-disabled.
 353     ///
 354     UINT32    L2HardwareEnabled : 1;
 355     UINT32    Reserved1         : 7;
 356     ///
 357     /// [Bit 8] L2 Enabled. (R/W)  1 = L2 cache has been initialized 0 =
 358     /// Disabled (default) Until this bit is set the processor will not
 359     /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
 360     ///
 361     UINT32    L2Enabled         : 1;
 362     UINT32    Reserved2         : 14;
 363     ///
 364     /// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.
 365     ///
 366     UINT32    L2NotPresent      : 1;
 367     UINT32    Reserved3         : 8;
 368     UINT32    Reserved4         : 32;
 369   } Bits;
 370   ///
 371   /// All bit fields as a 32-bit value
 372   ///
 373   UINT32    Uint32;
 374   ///
 375   /// All bit fields as a 64-bit value
 376   ///
 377   UINT64    Uint64;
 378 } MSR_ATOM_BBL_CR_CTL3_REGISTER;
 379
 380 /**
 381   Shared.
 382
 383   @param  ECX  MSR_ATOM_PERF_STATUS (0x00000198)
 384   @param  EAX  Lower 32-bits of MSR value.
 385                Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
 386   @param  EDX  Upper 32-bits of MSR value.
 387                Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
 388
 389   <b>Example usage</b>
 390   @code
 391   MSR_ATOM_PERF_STATUS_REGISTER  Msr;
 392
 393   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
 394   AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
 395   @endcode
 396   @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
 397 **/
 398 #define MSR_ATOM_PERF_STATUS  0x00000198
 399
 400 /**
 401   MSR information returned for MSR index #MSR_ATOM_PERF_STATUS
 402 **/
 403 typedef union {
 404   ///
 405   /// Individual bit fields
 406   ///
 407   struct {
 408     ///
 409     /// [Bits 15:0] Current Performance State Value.
 410     ///
 411     UINT32    CurrentPerformanceStateValue : 16;
 412     UINT32    Reserved1                    : 16;
 413     UINT32    Reserved2                    : 8;
 414     ///
 415     /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
 416     /// configured for the processor.
 417     ///
 418     UINT32    MaximumBusRatio              : 5;
 419     UINT32    Reserved3                    : 19;
 420   } Bits;
 421   ///
 422   /// All bit fields as a 64-bit value
 423   ///
 424   UINT64    Uint64;
 425 } MSR_ATOM_PERF_STATUS_REGISTER;
 426
 427 /**
 428   Shared.
 429
 430   @param  ECX  MSR_ATOM_THERM2_CTL (0x0000019D)
 431   @param  EAX  Lower 32-bits of MSR value.
 432                Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
 433   @param  EDX  Upper 32-bits of MSR value.
 434                Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
 435
 436   <b>Example usage</b>
 437   @code
 438   MSR_ATOM_THERM2_CTL_REGISTER  Msr;
 439
 440   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
 441   AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
 442   @endcode
 443   @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
 444 **/
 445 #define MSR_ATOM_THERM2_CTL  0x0000019D
 446
 447 /**
 448   MSR information returned for MSR index #MSR_ATOM_THERM2_CTL
 449 **/
 450 typedef union {
 451   ///
 452   /// Individual bit fields
 453   ///
 454   struct {
 455     UINT32    Reserved1 : 16;
 456     ///
 457     /// [Bit 16] TM_SELECT (R/W)  Mode of automatic thermal monitor: 1. =
 458     /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
 459     /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
 460     /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
 461     /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
 462     ///
 463     UINT32    TM_SELECT : 1;
 464     UINT32    Reserved2 : 15;
 465     UINT32    Reserved3 : 32;
 466   } Bits;
 467   ///
 468   /// All bit fields as a 32-bit value
 469   ///
 470   UINT32    Uint32;
 471   ///
 472   /// All bit fields as a 64-bit value
 473   ///
 474   UINT64    Uint64;
 475 } MSR_ATOM_THERM2_CTL_REGISTER;
 476
 477 /**
 478   Unique. Enable Misc. Processor Features (R/W)  Allows a variety of processor
 479   functions to be enabled and disabled.
 480
 481   @param  ECX  MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
 482   @param  EAX  Lower 32-bits of MSR value.
 483                Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
 484   @param  EDX  Upper 32-bits of MSR value.
 485                Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
 486
 487   <b>Example usage</b>
 488   @code
 489   MSR_ATOM_IA32_MISC_ENABLE_REGISTER  Msr;
 490
 491   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
 492   AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
 493   @endcode
 494   @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 495 **/
 496 #define MSR_ATOM_IA32_MISC_ENABLE  0x000001A0
 497
 498 /**
 499   MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE
 500 **/
 501 typedef union {
 502   ///
 503   /// Individual bit fields
 504   ///
 505   struct {
 506     ///
 507     /// [Bit 0] Fast-Strings Enable See Table 2-2.
 508     ///
 509     UINT32    FastStrings                    : 1;
 510     UINT32    Reserved1                      : 2;
 511     ///
 512     /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
 513     /// Table 2-2. Default value is 0.
 514     ///
 515     UINT32    AutomaticThermalControlCircuit : 1;
 516     UINT32    Reserved2                      : 3;
 517     ///
 518     /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
 519     ///
 520     UINT32    PerformanceMonitoring          : 1;
 521     UINT32    Reserved3                      : 1;
 522     UINT32    Reserved4                      : 1;
 523     ///
 524     /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
 525     /// the processor to indicate a pending break event within the processor 0
 526     /// = Indicates compatible FERR# signaling behavior This bit must be set
 527     /// to 1 to support XAPIC interrupt model usage.
 528     ///
 529     UINT32    FERR                           : 1;
 530     ///
 531     /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
 532     ///
 533     UINT32    BTS                            : 1;
 534     ///
 535     /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
 536     /// Table 2-2.
 537     ///
 538     UINT32    PEBS                           : 1;
 539     ///
 540     /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
 541     /// thermal sensor indicates that the die temperature is at the
 542     /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
 543     /// TM2 will reduce the bus to core ratio and voltage according to the
 544     /// value last written to MSR_THERM2_CTL bits 15:0.
 545     ///   When this bit is clear (0, default), the processor does not change
 546     ///   the VID signals or the bus to core ratio when the processor enters a
 547     ///   thermally managed state. The BIOS must enable this feature if the
 548     ///   TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
 549     ///   not set, this feature is not supported and BIOS must not alter the
 550     ///   contents of the TM2 bit location. The processor is operating out of
 551     ///   specification if both this bit and the TM1 bit are set to 0.
 552     ///
 553     UINT32    TM2       : 1;
 554     UINT32    Reserved5 : 2;
 555     ///
 556     /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
 557     /// Table 2-2.
 558     ///
 559     UINT32    EIST      : 1;
 560     UINT32    Reserved6 : 1;
 561     ///
 562     /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
 563     ///
 564     UINT32    MONITOR   : 1;
 565     UINT32    Reserved7 : 1;
 566     ///
 567     /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
 568     /// (R/WO) When set, this bit causes the following bits to become
 569     /// read-only: -  Enhanced Intel SpeedStep Technology Select Lock (this
 570     /// bit), -  Enhanced Intel SpeedStep Technology Enable bit. The bit must
 571     /// be set before an Enhanced Intel SpeedStep Technology transition is
 572     /// requested. This bit is cleared on reset.
 573     ///
 574     UINT32    EISTLock             : 1;
 575     UINT32    Reserved8            : 1;
 576     ///
 577     /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.
 578     ///
 579     UINT32    LimitCpuidMaxval     : 1;
 580     ///
 581     /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
 582     ///
 583     UINT32    xTPR_Message_Disable : 1;
 584     UINT32    Reserved9            : 8;
 585     UINT32    Reserved10           : 2;
 586     ///
 587     /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
 588     ///
 589     UINT32    XD                   : 1;
 590     UINT32    Reserved11           : 29;
 591   } Bits;
 592   ///
 593   /// All bit fields as a 64-bit value
 594   ///
 595   UINT64    Uint64;
 596 } MSR_ATOM_IA32_MISC_ENABLE_REGISTER;
 597
 598 /**
 599   Unique. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-2)
 600   that points to the MSR containing the most recent branch record. See
 601   MSR_LASTBRANCH_0_FROM_IP (at 40H).
 602
 603   @param  ECX  MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
 604   @param  EAX  Lower 32-bits of MSR value.
 605   @param  EDX  Upper 32-bits of MSR value.
 606
 607   <b>Example usage</b>
 608   @code
 609   UINT64  Msr;
 610
 611   Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
 612   AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
 613   @endcode
 614   @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 615 **/
 616 #define MSR_ATOM_LASTBRANCH_TOS  0x000001C9
 617
 618 /**
 619   Unique. Last Exception Record From Linear IP (R)  Contains a pointer to the
 620   last branch instruction that the processor executed prior to the last
 621   exception that was generated or the last interrupt that was handled.
 622
 623   @param  ECX  MSR_ATOM_LER_FROM_LIP (0x000001DD)
 624   @param  EAX  Lower 32-bits of MSR value.
 625   @param  EDX  Upper 32-bits of MSR value.
 626
 627   <b>Example usage</b>
 628   @code
 629   UINT64  Msr;
 630
 631   Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
 632   @endcode
 633   @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 634 **/
 635 #define MSR_ATOM_LER_FROM_LIP  0x000001DD
 636
 637 /**
 638   Unique. Last Exception Record To Linear IP (R)  This area contains a pointer
 639   to the target of the last branch instruction that the processor executed
 640   prior to the last exception that was generated or the last interrupt that
 641   was handled.
 642
 643   @param  ECX  MSR_ATOM_LER_TO_LIP (0x000001DE)
 644   @param  EAX  Lower 32-bits of MSR value.
 645   @param  EDX  Upper 32-bits of MSR value.
 646
 647   <b>Example usage</b>
 648   @code
 649   UINT64  Msr;
 650
 651   Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
 652   @endcode
 653   @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 654 **/
 655 #define MSR_ATOM_LER_TO_LIP  0x000001DE
 656
 657 /**
 658   Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
 659   (PEBS).".
 660
 661   @param  ECX  MSR_ATOM_PEBS_ENABLE (0x000003F1)
 662   @param  EAX  Lower 32-bits of MSR value.
 663                Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
 664   @param  EDX  Upper 32-bits of MSR value.
 665                Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
 666
 667   <b>Example usage</b>
 668   @code
 669   MSR_ATOM_PEBS_ENABLE_REGISTER  Msr;
 670
 671   Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
 672   AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
 673   @endcode
 674   @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
 675 **/
 676 #define MSR_ATOM_PEBS_ENABLE  0x000003F1
 677
 678 /**
 679   MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE
 680 **/
 681 typedef union {
 682   ///
 683   /// Individual bit fields
 684   ///
 685   struct {
 686     ///
 687     /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
 688     ///
 689     UINT32    Enable    : 1;
 690     UINT32    Reserved1 : 31;
 691     UINT32    Reserved2 : 32;
 692   } Bits;
 693   ///
 694   /// All bit fields as a 32-bit value
 695   ///
 696   UINT32    Uint32;
 697   ///
 698   /// All bit fields as a 64-bit value
 699   ///
 700   UINT64    Uint64;
 701 } MSR_ATOM_PEBS_ENABLE_REGISTER;
 702
 703 /**
 704   Package. Package C2 Residency Note: C-state values are processor specific
 705   C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
 706   C-States. Package. Package C2 Residency Counter. (R/O) Time that this
 707   package is in processor-specific C2 states since last reset. Counts at 1 Mhz
 708   frequency.
 709
 710   @param  ECX  MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
 711   @param  EAX  Lower 32-bits of MSR value.
 712   @param  EDX  Upper 32-bits of MSR value.
 713
 714   <b>Example usage</b>
 715   @code
 716   UINT64  Msr;
 717
 718   Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
 719   AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
 720   @endcode
 721   @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
 722 **/
 723 #define MSR_ATOM_PKG_C2_RESIDENCY  0x000003F8
 724
 725 /**
 726   Package. Package C4 Residency Note: C-state values are processor specific
 727   C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
 728   C-States. Package. Package C4 Residency Counter. (R/O) Time that this
 729   package is in processor-specific C4 states since last reset. Counts at 1 Mhz
 730   frequency.
 731
 732   @param  ECX  MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
 733   @param  EAX  Lower 32-bits of MSR value.
 734   @param  EDX  Upper 32-bits of MSR value.
 735
 736   <b>Example usage</b>
 737   @code
 738   UINT64  Msr;
 739
 740   Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
 741   AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
 742   @endcode
 743   @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.
 744 **/
 745 #define MSR_ATOM_PKG_C4_RESIDENCY  0x000003F9
 746
 747 /**
 748   Package. Package C6 Residency Note: C-state values are processor specific
 749   C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
 750   C-States. Package. Package C6 Residency Counter. (R/O) Time that this
 751   package is in processor-specific C6 states since last reset. Counts at 1 Mhz
 752   frequency.
 753
 754   @param  ECX  MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
 755   @param  EAX  Lower 32-bits of MSR value.
 756   @param  EDX  Upper 32-bits of MSR value.
 757
 758   <b>Example usage</b>
 759   @code
 760   UINT64  Msr;
 761
 762   Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
 763   AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
 764   @endcode
 765   @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
 766 **/
 767 #define MSR_ATOM_PKG_C6_RESIDENCY  0x000003FA
 768
 769 #endif