MdePkg/Include/Register/Intel/Msr/CoreMsr.h

   1 /** @file
   2   MSR Definitions for Intel Core Solo and Intel Core Duo Processors.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __CORE_MSR_H__
  19 #define __CORE_MSR_H__
  20
  21 #include <Register/Intel/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Intel Core Solo and Intel Core Duo Processors?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x06 && \
  34    ( \
  35     DisplayModel == 0x0E \
  36     ) \
  37    )
  38
  39 /**
  40   Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
  41
  42   @param  ECX  MSR_CORE_P5_MC_ADDR (0x00000000)
  43   @param  EAX  Lower 32-bits of MSR value.
  44   @param  EDX  Upper 32-bits of MSR value.
  45
  46   <b>Example usage</b>
  47   @code
  48   UINT64  Msr;
  49
  50   Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
  51   AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
  52   @endcode
  53   @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
  54 **/
  55 #define MSR_CORE_P5_MC_ADDR  0x00000000
  56
  57 /**
  58   Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
  59
  60   @param  ECX  MSR_CORE_P5_MC_TYPE (0x00000001)
  61   @param  EAX  Lower 32-bits of MSR value.
  62   @param  EDX  Upper 32-bits of MSR value.
  63
  64   <b>Example usage</b>
  65   @code
  66   UINT64  Msr;
  67
  68   Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
  69   AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
  70   @endcode
  71   @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
  72 **/
  73 #define MSR_CORE_P5_MC_TYPE  0x00000001
  74
  75 /**
  76   Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
  77   processor features; (R) indicates current processor configuration.
  78
  79   @param  ECX  MSR_CORE_EBL_CR_POWERON (0x0000002A)
  80   @param  EAX  Lower 32-bits of MSR value.
  81                Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
  82   @param  EDX  Upper 32-bits of MSR value.
  83                Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
  84
  85   <b>Example usage</b>
  86   @code
  87   MSR_CORE_EBL_CR_POWERON_REGISTER  Msr;
  88
  89   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
  90   AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
  91   @endcode
  92   @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
  93 **/
  94 #define MSR_CORE_EBL_CR_POWERON  0x0000002A
  95
  96 /**
  97   MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON
  98 **/
  99 typedef union {
 100   ///
 101   /// Individual bit fields
 102   ///
 103   struct {
 104     UINT32    Reserved1                   : 1;
 105     ///
 106     /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
 107     /// Note: Not all processor implements R/W.
 108     ///
 109     UINT32    DataErrorCheckingEnable     : 1;
 110     ///
 111     /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
 112     /// Note: Not all processor implements R/W.
 113     ///
 114     UINT32    ResponseErrorCheckingEnable : 1;
 115     ///
 116     /// [Bit 3] MCERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Note: Not
 117     /// all processor implements R/W.
 118     ///
 119     UINT32    MCERR_DriveEnable           : 1;
 120     ///
 121     /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
 122     /// Not all processor implements R/W.
 123     ///
 124     UINT32    AddressParityEnable         : 1;
 125     UINT32    Reserved2                   : 2;
 126     ///
 127     /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
 128     /// all processor implements R/W.
 129     ///
 130     UINT32    BINIT_DriverEnable          : 1;
 131     ///
 132     /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
 133     ///
 134     UINT32    OutputTriStateEnable        : 1;
 135     ///
 136     /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
 137     ///
 138     UINT32    ExecuteBIST                 : 1;
 139     ///
 140     /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
 141     ///
 142     UINT32    MCERR_ObservationEnabled    : 1;
 143     UINT32    Reserved3                   : 1;
 144     ///
 145     /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
 146     ///
 147     UINT32    BINIT_ObservationEnabled    : 1;
 148     UINT32    Reserved4                   : 1;
 149     ///
 150     /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
 151     ///
 152     UINT32    ResetVector                 : 1;
 153     UINT32    Reserved5                   : 1;
 154     ///
 155     /// [Bits 17:16] APIC Cluster ID (R/O).
 156     ///
 157     UINT32    APICClusterID               : 2;
 158     ///
 159     /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.
 160     ///
 161     UINT32    SystemBusFrequency          : 1;
 162     UINT32    Reserved6                   : 1;
 163     ///
 164     /// [Bits 21:20] Symmetric Arbitration ID (R/O).
 165     ///
 166     UINT32    SymmetricArbitrationID      : 2;
 167     ///
 168     /// [Bits 26:22] Clock Frequency Ratio (R/O).
 169     ///
 170     UINT32    ClockFrequencyRatio         : 5;
 171     UINT32    Reserved7                   : 5;
 172     UINT32    Reserved8                   : 32;
 173   } Bits;
 174   ///
 175   /// All bit fields as a 32-bit value
 176   ///
 177   UINT32    Uint32;
 178   ///
 179   /// All bit fields as a 64-bit value
 180   ///
 181   UINT64    Uint64;
 182 } MSR_CORE_EBL_CR_POWERON_REGISTER;
 183
 184 /**
 185   Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
 186   the last branch record stack: bits 31-0 hold the 'from' address and bits
 187   63-32 hold the 'to' address. See also: -  Last Branch Record Stack TOS at
 188   1C9H -  Section 17.15, "Last Branch, Interrupt, and Exception Recording
 189   (Pentium M Processors).".
 190
 191   @param  ECX  MSR_CORE_LASTBRANCH_n
 192   @param  EAX  Lower 32-bits of MSR value.
 193   @param  EDX  Upper 32-bits of MSR value.
 194
 195   <b>Example usage</b>
 196   @code
 197   UINT64  Msr;
 198
 199   Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
 200   AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);
 201   @endcode
 202   @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
 203         MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
 204         MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
 205         MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
 206         MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
 207         MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
 208         MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
 209         MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
 210   @{
 211 **/
 212 #define MSR_CORE_LASTBRANCH_0  0x00000040
 213 #define MSR_CORE_LASTBRANCH_1  0x00000041
 214 #define MSR_CORE_LASTBRANCH_2  0x00000042
 215 #define MSR_CORE_LASTBRANCH_3  0x00000043
 216 #define MSR_CORE_LASTBRANCH_4  0x00000044
 217 #define MSR_CORE_LASTBRANCH_5  0x00000045
 218 #define MSR_CORE_LASTBRANCH_6  0x00000046
 219 #define MSR_CORE_LASTBRANCH_7  0x00000047
 220 /// @}
 221
 222 /**
 223   Shared. Scalable Bus Speed (RO) This field indicates the scalable bus
 224   clock speed:.
 225
 226   @param  ECX  MSR_CORE_FSB_FREQ (0x000000CD)
 227   @param  EAX  Lower 32-bits of MSR value.
 228                Described by the type MSR_CORE_FSB_FREQ_REGISTER.
 229   @param  EDX  Upper 32-bits of MSR value.
 230                Described by the type MSR_CORE_FSB_FREQ_REGISTER.
 231
 232   <b>Example usage</b>
 233   @code
 234   MSR_CORE_FSB_FREQ_REGISTER  Msr;
 235
 236   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
 237   @endcode
 238   @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 239 **/
 240 #define MSR_CORE_FSB_FREQ  0x000000CD
 241
 242 /**
 243   MSR information returned for MSR index #MSR_CORE_FSB_FREQ
 244 **/
 245 typedef union {
 246   ///
 247   /// Individual bit fields
 248   ///
 249   struct {
 250     ///
 251     /// [Bits 2:0] - Scalable Bus Speed
 252     ///   101B: 100 MHz (FSB 400)
 253     ///   001B: 133 MHz (FSB 533)
 254     ///   011B: 167 MHz (FSB 667)
 255     ///
 256     /// 133.33 MHz should be utilized if performing calculation with System Bus
 257     /// Speed when encoding is 101B. 166.67 MHz should be utilized if
 258     /// performing calculation with System Bus Speed when encoding is 001B.
 259     ///
 260     UINT32    ScalableBusSpeed : 3;
 261     UINT32    Reserved1        : 29;
 262     UINT32    Reserved2        : 32;
 263   } Bits;
 264   ///
 265   /// All bit fields as a 32-bit value
 266   ///
 267   UINT32    Uint32;
 268   ///
 269   /// All bit fields as a 64-bit value
 270   ///
 271   UINT64    Uint64;
 272 } MSR_CORE_FSB_FREQ_REGISTER;
 273
 274 /**
 275   Shared.
 276
 277   @param  ECX  MSR_CORE_BBL_CR_CTL3 (0x0000011E)
 278   @param  EAX  Lower 32-bits of MSR value.
 279                Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
 280   @param  EDX  Upper 32-bits of MSR value.
 281                Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
 282
 283   <b>Example usage</b>
 284   @code
 285   MSR_CORE_BBL_CR_CTL3_REGISTER  Msr;
 286
 287   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);
 288   AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);
 289   @endcode
 290   @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 291 **/
 292 #define MSR_CORE_BBL_CR_CTL3  0x0000011E
 293
 294 /**
 295   MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3
 296 **/
 297 typedef union {
 298   ///
 299   /// Individual bit fields
 300   ///
 301   struct {
 302     ///
 303     /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
 304     /// Indicates if the L2 is hardware-disabled.
 305     ///
 306     UINT32    L2HardwareEnabled : 1;
 307     UINT32    Reserved1         : 7;
 308     ///
 309     /// [Bit 8] L2 Enabled (R/W)  1 = L2 cache has been initialized 0 =
 310     /// Disabled (default) Until this bit is set the processor will not
 311     /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
 312     ///
 313     UINT32    L2Enabled         : 1;
 314     UINT32    Reserved2         : 14;
 315     ///
 316     /// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.
 317     ///
 318     UINT32    L2NotPresent      : 1;
 319     UINT32    Reserved3         : 8;
 320     UINT32    Reserved4         : 32;
 321   } Bits;
 322   ///
 323   /// All bit fields as a 32-bit value
 324   ///
 325   UINT32    Uint32;
 326   ///
 327   /// All bit fields as a 64-bit value
 328   ///
 329   UINT64    Uint64;
 330 } MSR_CORE_BBL_CR_CTL3_REGISTER;
 331
 332 /**
 333   Unique.
 334
 335   @param  ECX  MSR_CORE_THERM2_CTL (0x0000019D)
 336   @param  EAX  Lower 32-bits of MSR value.
 337                Described by the type MSR_CORE_THERM2_CTL_REGISTER.
 338   @param  EDX  Upper 32-bits of MSR value.
 339                Described by the type MSR_CORE_THERM2_CTL_REGISTER.
 340
 341   <b>Example usage</b>
 342   @code
 343   MSR_CORE_THERM2_CTL_REGISTER  Msr;
 344
 345   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);
 346   AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);
 347   @endcode
 348   @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
 349 **/
 350 #define MSR_CORE_THERM2_CTL  0x0000019D
 351
 352 /**
 353   MSR information returned for MSR index #MSR_CORE_THERM2_CTL
 354 **/
 355 typedef union {
 356   ///
 357   /// Individual bit fields
 358   ///
 359   struct {
 360     UINT32    Reserved1 : 16;
 361     ///
 362     /// [Bit 16] TM_SELECT (R/W)  Mode of automatic thermal monitor: 1. =
 363     /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
 364     /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
 365     /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
 366     /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
 367     ///
 368     UINT32    TM_SELECT : 1;
 369     UINT32    Reserved2 : 15;
 370     UINT32    Reserved3 : 32;
 371   } Bits;
 372   ///
 373   /// All bit fields as a 32-bit value
 374   ///
 375   UINT32    Uint32;
 376   ///
 377   /// All bit fields as a 64-bit value
 378   ///
 379   UINT64    Uint64;
 380 } MSR_CORE_THERM2_CTL_REGISTER;
 381
 382 /**
 383   Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
 384   functions to be enabled and disabled.
 385
 386   @param  ECX  MSR_CORE_IA32_MISC_ENABLE (0x000001A0)
 387   @param  EAX  Lower 32-bits of MSR value.
 388                Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
 389   @param  EDX  Upper 32-bits of MSR value.
 390                Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
 391
 392   <b>Example usage</b>
 393   @code
 394   MSR_CORE_IA32_MISC_ENABLE_REGISTER  Msr;
 395
 396   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);
 397   AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);
 398   @endcode
 399   @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 400 **/
 401 #define MSR_CORE_IA32_MISC_ENABLE  0x000001A0
 402
 403 /**
 404   MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE
 405 **/
 406 typedef union {
 407   ///
 408   /// Individual bit fields
 409   ///
 410   struct {
 411     UINT32    Reserved1                      : 3;
 412     ///
 413     /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
 414     /// Table 2-2.
 415     ///
 416     UINT32    AutomaticThermalControlCircuit : 1;
 417     UINT32    Reserved2                      : 3;
 418     ///
 419     /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
 420     ///
 421     UINT32    PerformanceMonitoring          : 1;
 422     UINT32    Reserved3                      : 2;
 423     ///
 424     /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
 425     /// the processor to indicate a pending break event within the processor 0
 426     /// = Indicates compatible FERR# signaling behavior This bit must be set
 427     /// to 1 to support XAPIC interrupt model usage.
 428     ///
 429     UINT32    FERR                           : 1;
 430     ///
 431     /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
 432     ///
 433     UINT32    BTS                            : 1;
 434     UINT32    Reserved4                      : 1;
 435     ///
 436     /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
 437     /// thermal sensor indicates that the die temperature is at the
 438     /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
 439     /// TM2 will reduce the bus to core ratio and voltage according to the
 440     /// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear
 441     /// (0, default), the processor does not change the VID signals or the bus
 442     /// to core ratio when the processor enters a thermal managed state. If
 443     /// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID
 444     /// with EAX = 1, then this feature is not supported and BIOS must not
 445     /// alter the contents of this bit location. The processor is operating
 446     /// out of spec if both this bit and the TM1 bit are set to disabled
 447     /// states.
 448     ///
 449     UINT32    TM2              : 1;
 450     UINT32    Reserved5        : 2;
 451     ///
 452     /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
 453     /// Enhanced Intel SpeedStep Technology enabled.
 454     ///
 455     UINT32    EIST             : 1;
 456     UINT32    Reserved6        : 1;
 457     ///
 458     /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
 459     ///
 460     UINT32    MONITOR          : 1;
 461     UINT32    Reserved7        : 1;
 462     UINT32    Reserved8        : 2;
 463     ///
 464     /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this
 465     /// bit may cause behavior in software that depends on the availability of
 466     /// CPUID leaves greater than 2.
 467     ///
 468     UINT32    LimitCpuidMaxval : 1;
 469     UINT32    Reserved9        : 9;
 470     UINT32    Reserved10       : 2;
 471     ///
 472     /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.
 473     ///
 474     UINT32    XD               : 1;
 475     UINT32    Reserved11       : 29;
 476   } Bits;
 477   ///
 478   /// All bit fields as a 64-bit value
 479   ///
 480   UINT64    Uint64;
 481 } MSR_CORE_IA32_MISC_ENABLE_REGISTER;
 482
 483 /**
 484   Unique. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-3)
 485   that points to the MSR containing the most recent branch record. See
 486   MSR_LASTBRANCH_0_FROM_IP (at 40H).
 487
 488   @param  ECX  MSR_CORE_LASTBRANCH_TOS (0x000001C9)
 489   @param  EAX  Lower 32-bits of MSR value.
 490   @param  EDX  Upper 32-bits of MSR value.
 491
 492   <b>Example usage</b>
 493   @code
 494   UINT64  Msr;
 495
 496   Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);
 497   AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);
 498   @endcode
 499   @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
 500 **/
 501 #define MSR_CORE_LASTBRANCH_TOS  0x000001C9
 502
 503 /**
 504   Unique. Last Exception Record From Linear IP (R)  Contains a pointer to the
 505   last branch instruction that the processor executed prior to the last
 506   exception that was generated or the last interrupt that was handled.
 507
 508   @param  ECX  MSR_CORE_LER_FROM_LIP (0x000001DD)
 509   @param  EAX  Lower 32-bits of MSR value.
 510   @param  EDX  Upper 32-bits of MSR value.
 511
 512   <b>Example usage</b>
 513   @code
 514   UINT64  Msr;
 515
 516   Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);
 517   @endcode
 518   @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
 519 **/
 520 #define MSR_CORE_LER_FROM_LIP  0x000001DD
 521
 522 /**
 523   Unique. Last Exception Record To Linear IP (R)  This area contains a pointer
 524   to the target of the last branch instruction that the processor executed
 525   prior to the last exception that was generated or the last interrupt that
 526   was handled.
 527
 528   @param  ECX  MSR_CORE_LER_TO_LIP (0x000001DE)
 529   @param  EAX  Lower 32-bits of MSR value.
 530   @param  EDX  Upper 32-bits of MSR value.
 531
 532   <b>Example usage</b>
 533   @code
 534   UINT64  Msr;
 535
 536   Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);
 537   @endcode
 538   @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
 539 **/
 540 #define MSR_CORE_LER_TO_LIP  0x000001DE
 541
 542 /**
 543   Unique.
 544
 545   @param  ECX  MSR_CORE_MTRRPHYSBASEn
 546   @param  EAX  Lower 32-bits of MSR value.
 547   @param  EDX  Upper 32-bits of MSR value.
 548
 549   <b>Example usage</b>
 550   @code
 551   UINT64  Msr;
 552
 553   Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
 554   AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);
 555   @endcode
 556   @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
 557         MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
 558         MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
 559         MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
 560         MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
 561         MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
 562         MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
 563         MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
 564   @{
 565 **/
 566 #define MSR_CORE_MTRRPHYSBASE0  0x00000200
 567 #define MSR_CORE_MTRRPHYSBASE1  0x00000202
 568 #define MSR_CORE_MTRRPHYSBASE2  0x00000204
 569 #define MSR_CORE_MTRRPHYSBASE3  0x00000206
 570 #define MSR_CORE_MTRRPHYSBASE4  0x00000208
 571 #define MSR_CORE_MTRRPHYSBASE5  0x0000020A
 572 #define MSR_CORE_MTRRPHYSMASK6  0x0000020D
 573 #define MSR_CORE_MTRRPHYSMASK7  0x0000020F
 574 /// @}
 575
 576 /**
 577   Unique.
 578
 579   @param  ECX  MSR_CORE_MTRRPHYSMASKn (0x00000201)
 580   @param  EAX  Lower 32-bits of MSR value.
 581   @param  EDX  Upper 32-bits of MSR value.
 582
 583   <b>Example usage</b>
 584   @code
 585   UINT64  Msr;
 586
 587   Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
 588   AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);
 589   @endcode
 590   @note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
 591         MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
 592         MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
 593         MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
 594         MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
 595         MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
 596         MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
 597         MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
 598   @{
 599 **/
 600 #define MSR_CORE_MTRRPHYSMASK0  0x00000201
 601 #define MSR_CORE_MTRRPHYSMASK1  0x00000203
 602 #define MSR_CORE_MTRRPHYSMASK2  0x00000205
 603 #define MSR_CORE_MTRRPHYSMASK3  0x00000207
 604 #define MSR_CORE_MTRRPHYSMASK4  0x00000209
 605 #define MSR_CORE_MTRRPHYSMASK5  0x0000020B
 606 #define MSR_CORE_MTRRPHYSBASE6  0x0000020C
 607 #define MSR_CORE_MTRRPHYSBASE7  0x0000020E
 608 /// @}
 609
 610 /**
 611   Unique.
 612
 613   @param  ECX  MSR_CORE_MTRRFIX64K_00000 (0x00000250)
 614   @param  EAX  Lower 32-bits of MSR value.
 615   @param  EDX  Upper 32-bits of MSR value.
 616
 617   <b>Example usage</b>
 618   @code
 619   UINT64  Msr;
 620
 621   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);
 622   AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);
 623   @endcode
 624   @note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
 625 **/
 626 #define MSR_CORE_MTRRFIX64K_00000  0x00000250
 627
 628 /**
 629   Unique.
 630
 631   @param  ECX  MSR_CORE_MTRRFIX16K_80000 (0x00000258)
 632   @param  EAX  Lower 32-bits of MSR value.
 633   @param  EDX  Upper 32-bits of MSR value.
 634
 635   <b>Example usage</b>
 636   @code
 637   UINT64  Msr;
 638
 639   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);
 640   AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);
 641   @endcode
 642   @note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
 643 **/
 644 #define MSR_CORE_MTRRFIX16K_80000  0x00000258
 645
 646 /**
 647   Unique.
 648
 649   @param  ECX  MSR_CORE_MTRRFIX16K_A0000 (0x00000259)
 650   @param  EAX  Lower 32-bits of MSR value.
 651   @param  EDX  Upper 32-bits of MSR value.
 652
 653   <b>Example usage</b>
 654   @code
 655   UINT64  Msr;
 656
 657   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);
 658   AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);
 659   @endcode
 660   @note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
 661 **/
 662 #define MSR_CORE_MTRRFIX16K_A0000  0x00000259
 663
 664 /**
 665   Unique.
 666
 667   @param  ECX  MSR_CORE_MTRRFIX4K_C0000 (0x00000268)
 668   @param  EAX  Lower 32-bits of MSR value.
 669   @param  EDX  Upper 32-bits of MSR value.
 670
 671   <b>Example usage</b>
 672   @code
 673   UINT64  Msr;
 674
 675   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);
 676   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);
 677   @endcode
 678   @note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
 679 **/
 680 #define MSR_CORE_MTRRFIX4K_C0000  0x00000268
 681
 682 /**
 683   Unique.
 684
 685   @param  ECX  MSR_CORE_MTRRFIX4K_C8000 (0x00000269)
 686   @param  EAX  Lower 32-bits of MSR value.
 687   @param  EDX  Upper 32-bits of MSR value.
 688
 689   <b>Example usage</b>
 690   @code
 691   UINT64  Msr;
 692
 693   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);
 694   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);
 695   @endcode
 696   @note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
 697 **/
 698 #define MSR_CORE_MTRRFIX4K_C8000  0x00000269
 699
 700 /**
 701   Unique.
 702
 703   @param  ECX  MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)
 704   @param  EAX  Lower 32-bits of MSR value.
 705   @param  EDX  Upper 32-bits of MSR value.
 706
 707   <b>Example usage</b>
 708   @code
 709   UINT64  Msr;
 710
 711   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);
 712   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);
 713   @endcode
 714   @note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
 715 **/
 716 #define MSR_CORE_MTRRFIX4K_D0000  0x0000026A
 717
 718 /**
 719   Unique.
 720
 721   @param  ECX  MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)
 722   @param  EAX  Lower 32-bits of MSR value.
 723   @param  EDX  Upper 32-bits of MSR value.
 724
 725   <b>Example usage</b>
 726   @code
 727   UINT64  Msr;
 728
 729   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);
 730   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);
 731   @endcode
 732   @note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
 733 **/
 734 #define MSR_CORE_MTRRFIX4K_D8000  0x0000026B
 735
 736 /**
 737   Unique.
 738
 739   @param  ECX  MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)
 740   @param  EAX  Lower 32-bits of MSR value.
 741   @param  EDX  Upper 32-bits of MSR value.
 742
 743   <b>Example usage</b>
 744   @code
 745   UINT64  Msr;
 746
 747   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);
 748   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);
 749   @endcode
 750   @note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
 751 **/
 752 #define MSR_CORE_MTRRFIX4K_E0000  0x0000026C
 753
 754 /**
 755   Unique.
 756
 757   @param  ECX  MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)
 758   @param  EAX  Lower 32-bits of MSR value.
 759   @param  EDX  Upper 32-bits of MSR value.
 760
 761   <b>Example usage</b>
 762   @code
 763   UINT64  Msr;
 764
 765   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);
 766   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);
 767   @endcode
 768   @note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
 769 **/
 770 #define MSR_CORE_MTRRFIX4K_E8000  0x0000026D
 771
 772 /**
 773   Unique.
 774
 775   @param  ECX  MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)
 776   @param  EAX  Lower 32-bits of MSR value.
 777   @param  EDX  Upper 32-bits of MSR value.
 778
 779   <b>Example usage</b>
 780   @code
 781   UINT64  Msr;
 782
 783   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);
 784   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);
 785   @endcode
 786   @note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
 787 **/
 788 #define MSR_CORE_MTRRFIX4K_F0000  0x0000026E
 789
 790 /**
 791   Unique.
 792
 793   @param  ECX  MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)
 794   @param  EAX  Lower 32-bits of MSR value.
 795   @param  EDX  Upper 32-bits of MSR value.
 796
 797   <b>Example usage</b>
 798   @code
 799   UINT64  Msr;
 800
 801   Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);
 802   AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);
 803   @endcode
 804   @note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
 805 **/
 806 #define MSR_CORE_MTRRFIX4K_F8000  0x0000026F
 807
 808 /**
 809   Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
 810
 811   @param  ECX  MSR_CORE_MC4_CTL (0x0000040C)
 812   @param  EAX  Lower 32-bits of MSR value.
 813   @param  EDX  Upper 32-bits of MSR value.
 814
 815   <b>Example usage</b>
 816   @code
 817   UINT64  Msr;
 818
 819   Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);
 820   AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);
 821   @endcode
 822   @note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.
 823 **/
 824 #define MSR_CORE_MC4_CTL  0x0000040C
 825
 826 /**
 827   Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
 828
 829   @param  ECX  MSR_CORE_MC4_STATUS (0x0000040D)
 830   @param  EAX  Lower 32-bits of MSR value.
 831   @param  EDX  Upper 32-bits of MSR value.
 832
 833   <b>Example usage</b>
 834   @code
 835   UINT64  Msr;
 836
 837   Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);
 838   AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);
 839   @endcode
 840   @note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
 841 **/
 842 #define MSR_CORE_MC4_STATUS  0x0000040D
 843
 844 /**
 845   Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
 846   register is either not implemented or contains no address if the ADDRV flag
 847   in the MSR_MC4_STATUS register is clear. When not implemented in the
 848   processor, all reads and writes to this MSR will cause a general-protection
 849   exception.
 850
 851   @param  ECX  MSR_CORE_MC4_ADDR (0x0000040E)
 852   @param  EAX  Lower 32-bits of MSR value.
 853   @param  EDX  Upper 32-bits of MSR value.
 854
 855   <b>Example usage</b>
 856   @code
 857   UINT64  Msr;
 858
 859   Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);
 860   AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);
 861   @endcode
 862   @note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
 863 **/
 864 #define MSR_CORE_MC4_ADDR  0x0000040E
 865
 866 /**
 867   Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
 868   register is either not implemented or contains no address if the ADDRV flag
 869   in the MSR_MC3_STATUS register is clear. When not implemented in the
 870   processor, all reads and writes to this MSR will cause a general-protection
 871   exception.
 872
 873   @param  ECX  MSR_CORE_MC3_ADDR (0x00000412)
 874   @param  EAX  Lower 32-bits of MSR value.
 875   @param  EDX  Upper 32-bits of MSR value.
 876
 877   <b>Example usage</b>
 878   @code
 879   UINT64  Msr;
 880
 881   Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);
 882   AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);
 883   @endcode
 884   @note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
 885 **/
 886 #define MSR_CORE_MC3_ADDR  0x00000412
 887
 888 /**
 889   Unique.
 890
 891   @param  ECX  MSR_CORE_MC3_MISC (0x00000413)
 892   @param  EAX  Lower 32-bits of MSR value.
 893   @param  EDX  Upper 32-bits of MSR value.
 894
 895   <b>Example usage</b>
 896   @code
 897   UINT64  Msr;
 898
 899   Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);
 900   AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);
 901   @endcode
 902   @note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.
 903 **/
 904 #define MSR_CORE_MC3_MISC  0x00000413
 905
 906 /**
 907   Unique.
 908
 909   @param  ECX  MSR_CORE_MC5_CTL (0x00000414)
 910   @param  EAX  Lower 32-bits of MSR value.
 911   @param  EDX  Upper 32-bits of MSR value.
 912
 913   <b>Example usage</b>
 914   @code
 915   UINT64  Msr;
 916
 917   Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);
 918   AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);
 919   @endcode
 920   @note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.
 921 **/
 922 #define MSR_CORE_MC5_CTL  0x00000414
 923
 924 /**
 925   Unique.
 926
 927   @param  ECX  MSR_CORE_MC5_STATUS (0x00000415)
 928   @param  EAX  Lower 32-bits of MSR value.
 929   @param  EDX  Upper 32-bits of MSR value.
 930
 931   <b>Example usage</b>
 932   @code
 933   UINT64  Msr;
 934
 935   Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);
 936   AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);
 937   @endcode
 938   @note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
 939 **/
 940 #define MSR_CORE_MC5_STATUS  0x00000415
 941
 942 /**
 943   Unique.
 944
 945   @param  ECX  MSR_CORE_MC5_ADDR (0x00000416)
 946   @param  EAX  Lower 32-bits of MSR value.
 947   @param  EDX  Upper 32-bits of MSR value.
 948
 949   <b>Example usage</b>
 950   @code
 951   UINT64  Msr;
 952
 953   Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);
 954   AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);
 955   @endcode
 956   @note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
 957 **/
 958 #define MSR_CORE_MC5_ADDR  0x00000416
 959
 960 /**
 961   Unique.
 962
 963   @param  ECX  MSR_CORE_MC5_MISC (0x00000417)
 964   @param  EAX  Lower 32-bits of MSR value.
 965   @param  EDX  Upper 32-bits of MSR value.
 966
 967   <b>Example usage</b>
 968   @code
 969   UINT64  Msr;
 970
 971   Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);
 972   AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);
 973   @endcode
 974   @note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.
 975 **/
 976 #define MSR_CORE_MC5_MISC  0x00000417
 977
 978 /**
 979   Unique. See Table 2-2.
 980
 981   @param  ECX  MSR_CORE_IA32_EFER (0xC0000080)
 982   @param  EAX  Lower 32-bits of MSR value.
 983                Described by the type MSR_CORE_IA32_EFER_REGISTER.
 984   @param  EDX  Upper 32-bits of MSR value.
 985                Described by the type MSR_CORE_IA32_EFER_REGISTER.
 986
 987   <b>Example usage</b>
 988   @code
 989   MSR_CORE_IA32_EFER_REGISTER  Msr;
 990
 991   Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
 992   AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);
 993   @endcode
 994   @note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.
 995 **/
 996 #define MSR_CORE_IA32_EFER  0xC0000080
 997
 998 /**
 999   MSR information returned for MSR index #MSR_CORE_IA32_EFER
1000 **/
1001 typedef union {
1002   ///
1003   /// Individual bit fields
1004   ///
1005   struct {
1006     UINT32    Reserved1 : 11;
1007     ///
1008     /// [Bit 11] Execute Disable Bit Enable.
1009     ///
1010     UINT32    NXE       : 1;
1011     UINT32    Reserved2 : 20;
1012     UINT32    Reserved3 : 32;
1013   } Bits;
1014   ///
1015   /// All bit fields as a 32-bit value
1016   ///
1017   UINT32    Uint32;
1018   ///
1019   /// All bit fields as a 64-bit value
1020   ///
1021   UINT64    Uint64;
1022 } MSR_CORE_IA32_EFER_REGISTER;
1023
1024 #endif