MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h

   1 /** @file
   2   MSR Definitions for Intel Atom processors based on the Goldmont Plus microarchitecture.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __GOLDMONT_PLUS_MSR_H__
  19 #define __GOLDMONT_PLUS_MSR_H__
  20
  21 #include <Register/Intel/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Intel Atom processors based on the Goldmont plus microarchitecture?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x06 && \
  34    (                        \
  35     DisplayModel == 0x7A    \
  36     )                       \
  37    )
  38
  39 /**
  40   Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based
  41   Sampling (PEBS).".
  42
  43   @param  ECX  MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)
  44   @param  EAX  Lower 32-bits of MSR value.
  45                Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
  46   @param  EDX  Upper 32-bits of MSR value.
  47                Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
  48
  49   <b>Example usage</b>
  50   @code
  51   MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER  Msr;
  52
  53   Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);
  54   AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);
  55   @endcode
  56 **/
  57 #define MSR_GOLDMONT_PLUS_PEBS_ENABLE  0x000003F1
  58
  59 /**
  60   MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE
  61 **/
  62 typedef union {
  63   ///
  64   /// Individual bit fields
  65   ///
  66   struct {
  67     ///
  68     /// [Bit 0] Enable PEBS trigger and recording for the programmed event
  69     /// (precise or otherwise) on IA32_PMC0.
  70     ///
  71     UINT32    Fix_Me_1  : 1;
  72     ///
  73     /// [Bit 1] Enable PEBS trigger and recording for the programmed event
  74     /// (precise or otherwise) on IA32_PMC1.
  75     ///
  76     UINT32    Fix_Me_2  : 1;
  77     ///
  78     /// [Bit 2] Enable PEBS trigger and recording for the programmed event
  79     /// (precise or otherwise) on IA32_PMC2.
  80     ///
  81     UINT32    Fix_Me_3  : 1;
  82     ///
  83     /// [Bit 3] Enable PEBS trigger and recording for the programmed event
  84     /// (precise or otherwise) on IA32_PMC3.
  85     ///
  86     UINT32    Fix_Me_4  : 1;
  87     UINT32    Reserved1 : 28;
  88     ///
  89     /// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.
  90     ///
  91     UINT32    Fix_Me_5  : 1;
  92     ///
  93     /// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.
  94     ///
  95     UINT32    Fix_Me_6  : 1;
  96     ///
  97     /// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.
  98     ///
  99     UINT32    Fix_Me_7  : 1;
 100     UINT32    Reserved2 : 29;
 101   } Bits;
 102   ///
 103   /// All bit fields as a 64-bit value
 104   ///
 105   UINT64    Uint64;
 106 } MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;
 107
 108 /**
 109   Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up
 110   the first entry of the 32-entry LBR stack. The From_IP part of the stack
 111   contains pointers to the source instruction. See also: -  Last Branch Record
 112   Stack TOS at 1C9H. -  Section 17.7, "Last Branch, Call Stack, Interrupt, and
 113   .. Exception Recording for Processors based on Goldmont Plus
 114   Microarchitecture.".
 115
 116   @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)
 117   @param  EAX  Lower 32-bits of MSR value.
 118   @param  EDX  Upper 32-bits of MSR value.
 119
 120   <b>Example usage</b>
 121   @code
 122   UINT64  Msr;
 123
 124   Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);
 125   AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);
 126   @endcode
 127 **/
 128 #define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP   0x00000680
 129 #define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP   0x00000681
 130 #define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP   0x00000682
 131 #define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP   0x00000683
 132 #define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP   0x00000684
 133 #define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP   0x00000685
 134 #define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP   0x00000686
 135 #define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP   0x00000687
 136 #define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP   0x00000688
 137 #define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP   0x00000689
 138 #define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP  0x0000068A
 139 #define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP  0x0000068B
 140 #define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP  0x0000068C
 141 #define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP  0x0000068D
 142 #define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP  0x0000068E
 143 #define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP  0x0000068F
 144 #define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP  0x00000690
 145 #define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP  0x00000691
 146 #define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP  0x00000692
 147 #define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP  0x00000693
 148 #define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP  0x00000694
 149 #define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP  0x00000695
 150 #define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP  0x00000696
 151 #define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP  0x00000697
 152 #define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP  0x00000698
 153 #define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP  0x00000699
 154 #define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP  0x0000069A
 155 #define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP  0x0000069B
 156 #define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP  0x0000069C
 157 #define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP  0x0000069D
 158 #define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP  0x0000069E
 159 #define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP  0x0000069F
 160
 161 /**
 162   Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up
 163   the first entry of the 32-entry LBR stack. The To_IP part of the stack
 164   contains pointers to the Destination instruction. See also: - Section 17.7,
 165   "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors
 166   based on Goldmont Plus Microarchitecture.".
 167
 168   @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)
 169   @param  EAX  Lower 32-bits of MSR value.
 170   @param  EDX  Upper 32-bits of MSR value.
 171
 172   <b>Example usage</b>
 173   @code
 174   UINT64  Msr;
 175
 176   Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);
 177   AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);
 178   @endcode
 179 **/
 180 #define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP   0x000006C0
 181 #define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP   0x000006C1
 182 #define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP   0x000006C2
 183 #define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP   0x000006C3
 184 #define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP   0x000006C4
 185 #define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP   0x000006C5
 186 #define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP   0x000006C6
 187 #define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP   0x000006C7
 188 #define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP   0x000006C8
 189 #define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP   0x000006C9
 190 #define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP  0x000006CA
 191 #define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP  0x000006CB
 192 #define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP  0x000006CC
 193 #define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP  0x000006CD
 194 #define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP  0x000006CE
 195 #define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP  0x000006CF
 196 #define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP  0x000006D0
 197 #define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP  0x000006D1
 198 #define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP  0x000006D2
 199 #define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP  0x000006D3
 200 #define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP  0x000006D4
 201 #define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP  0x000006D5
 202 #define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP  0x000006D6
 203 #define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP  0x000006D7
 204 #define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP  0x000006D8
 205 #define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP  0x000006D9
 206 #define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP  0x000006DA
 207 #define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP  0x000006DB
 208 #define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP  0x000006DC
 209 #define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP  0x000006DD
 210 #define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP  0x000006DE
 211 #define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP  0x000006DF
 212
 213 /**
 214   Core. Last Branch Record N Additional Information (R/W) One of the three
 215   MSRs that make up the first entry of the 32-entry LBR stack. This part of
 216   the stack contains flag and elapsed cycle information. See also: -  Last
 217   Branch Record Stack TOS at 1C9H. -  Section 17.9.1, "LBR Stack.".
 218
 219   @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)
 220   @param  EAX  Lower 32-bits of MSR value.
 221   @param  EDX  Upper 32-bits of MSR value.
 222
 223   <b>Example usage</b>
 224   @code
 225   UINT64  Msr;
 226
 227   Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);
 228   AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);
 229   @endcode
 230 **/
 231 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0   0x00000DC0
 232 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1   0x00000DC1
 233 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2   0x00000DC2
 234 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3   0x00000DC3
 235 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4   0x00000DC4
 236 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5   0x00000DC5
 237 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6   0x00000DC6
 238 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7   0x00000DC7
 239 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8   0x00000DC8
 240 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9   0x00000DC9
 241 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10  0x00000DCA
 242 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11  0x00000DCB
 243 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12  0x00000DCC
 244 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13  0x00000DCD
 245 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14  0x00000DCE
 246 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15  0x00000DCF
 247 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16  0x00000DD0
 248 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17  0x00000DD1
 249 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18  0x00000DD2
 250 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19  0x00000DD3
 251 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20  0x00000DD4
 252 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21  0x00000DD5
 253 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22  0x00000DD6
 254 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23  0x00000DD7
 255 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24  0x00000DD8
 256 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25  0x00000DD9
 257 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26  0x00000DDA
 258 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27  0x00000DDB
 259 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28  0x00000DDC
 260 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29  0x00000DDD
 261 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30  0x00000DDE
 262 #define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31  0x00000DDF
 263
 264 #endif