MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h

   1 /** @file
   2   MSR Definitions for Intel processors based on the Haswell-E microarchitecture.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __HASWELL_E_MSR_H__
  19 #define __HASWELL_E_MSR_H__
  20
  21 #include <Register/Intel/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Intel processors based on the Haswell-E microarchitecture?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x06 && \
  34    (                        \
  35     DisplayModel == 0x3F    \
  36     )                       \
  37    )
  38
  39 /**
  40   Package. Configured State of Enabled Processor Core Count and Logical
  41   Processor Count (RO) -  After a Power-On RESET, enumerates factory
  42   configuration of the number of processor cores and logical processors in the
  43   physical package. -  Following the sequence of (i) BIOS modified a
  44   Configuration Mask which selects a subset of processor cores to be active
  45   post RESET and (ii) a RESET event after the modification, enumerates the
  46   current configuration of enabled processor core count and logical processor
  47   count in the physical package.
  48
  49   @param  ECX  MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)
  50   @param  EAX  Lower 32-bits of MSR value.
  51                Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
  52   @param  EDX  Upper 32-bits of MSR value.
  53                Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
  54
  55   <b>Example usage</b>
  56   @code
  57   MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER  Msr;
  58
  59   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);
  60   @endcode
  61   @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.
  62 **/
  63 #define MSR_HASWELL_E_CORE_THREAD_COUNT  0x00000035
  64
  65 /**
  66   MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT
  67 **/
  68 typedef union {
  69   ///
  70   /// Individual bit fields
  71   ///
  72   struct {
  73     ///
  74     /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are
  75     /// currently enabled (by either factory configuration or BIOS
  76     /// configuration) in the physical package.
  77     ///
  78     UINT32    Core_Count   : 16;
  79     ///
  80     /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that
  81     /// are currently enabled (by either factory configuration or BIOS
  82     /// configuration) in the physical package.
  83     ///
  84     UINT32    Thread_Count : 16;
  85     UINT32    Reserved     : 32;
  86   } Bits;
  87   ///
  88   /// All bit fields as a 32-bit value
  89   ///
  90   UINT32    Uint32;
  91   ///
  92   /// All bit fields as a 64-bit value
  93   ///
  94   UINT64    Uint64;
  95 } MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;
  96
  97 /**
  98   Thread. A Hardware Assigned ID for the Logical Processor (RO).
  99
 100   @param  ECX  MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)
 101   @param  EAX  Lower 32-bits of MSR value.
 102                Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
 103   @param  EDX  Upper 32-bits of MSR value.
 104                Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
 105
 106   <b>Example usage</b>
 107   @code
 108   MSR_HASWELL_E_THREAD_ID_INFO_REGISTER  Msr;
 109
 110   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);
 111   @endcode
 112   @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.
 113 **/
 114 #define MSR_HASWELL_E_THREAD_ID_INFO  0x00000053
 115
 116 /**
 117   MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO
 118 **/
 119 typedef union {
 120   ///
 121   /// Individual bit fields
 122   ///
 123   struct {
 124     ///
 125     /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific
 126     /// numerical. value physically assigned to each logical processor. This
 127     /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within
 128     /// a physical package.
 129     ///
 130     UINT32    Logical_Processor_ID : 8;
 131     UINT32    Reserved1            : 24;
 132     UINT32    Reserved2            : 32;
 133   } Bits;
 134   ///
 135   /// All bit fields as a 32-bit value
 136   ///
 137   UINT32    Uint32;
 138   ///
 139   /// All bit fields as a 64-bit value
 140   ///
 141   UINT64    Uint64;
 142 } MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;
 143
 144 /**
 145   Core. C-State Configuration Control (R/W) Note: C-state values are processor
 146   specific C-state code names, unrelated to MWAIT extension C-state parameters
 147   or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
 148
 149   @param  ECX  MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)
 150   @param  EAX  Lower 32-bits of MSR value.
 151                Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
 152   @param  EDX  Upper 32-bits of MSR value.
 153                Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
 154
 155   <b>Example usage</b>
 156   @code
 157   MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
 158
 159   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);
 160   AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
 161   @endcode
 162   @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 163 **/
 164 #define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL  0x000000E2
 165
 166 /**
 167   MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL
 168 **/
 169 typedef union {
 170   ///
 171   /// Individual bit fields
 172   ///
 173   struct {
 174     ///
 175     /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
 176     /// processor-specific C-state code name (consuming the least power) for
 177     /// the package. The default is set as factory-configured package C-state
 178     /// limit. The following C-state code name encodings are supported: 000b:
 179     /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
 180     /// 011b: C6 (retention) 111b: No Package C state limits. All C states
 181     /// supported by the processor are available.
 182     ///
 183     UINT32    Limit            : 3;
 184     UINT32    Reserved1        : 7;
 185     ///
 186     /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
 187     ///
 188     UINT32    IO_MWAIT         : 1;
 189     UINT32    Reserved2        : 4;
 190     ///
 191     /// [Bit 15] CFG Lock (R/WO).
 192     ///
 193     UINT32    CFGLock          : 1;
 194     UINT32    Reserved3        : 9;
 195     ///
 196     /// [Bit 25] C3 State Auto Demotion Enable (R/W).
 197     ///
 198     UINT32    C3AutoDemotion   : 1;
 199     ///
 200     /// [Bit 26] C1 State Auto Demotion Enable (R/W).
 201     ///
 202     UINT32    C1AutoDemotion   : 1;
 203     ///
 204     /// [Bit 27] Enable C3 Undemotion (R/W).
 205     ///
 206     UINT32    C3Undemotion     : 1;
 207     ///
 208     /// [Bit 28] Enable C1 Undemotion (R/W).
 209     ///
 210     UINT32    C1Undemotion     : 1;
 211     ///
 212     /// [Bit 29] Package C State Demotion Enable (R/W).
 213     ///
 214     UINT32    CStateDemotion   : 1;
 215     ///
 216     /// [Bit 30] Package C State UnDemotion Enable (R/W).
 217     ///
 218     UINT32    CStateUndemotion : 1;
 219     UINT32    Reserved4        : 1;
 220     UINT32    Reserved5        : 32;
 221   } Bits;
 222   ///
 223   /// All bit fields as a 32-bit value
 224   ///
 225   UINT32    Uint32;
 226   ///
 227   /// All bit fields as a 64-bit value
 228   ///
 229   UINT64    Uint64;
 230 } MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;
 231
 232 /**
 233   Thread. Global Machine Check Capability (R/O).
 234
 235   @param  ECX  MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)
 236   @param  EAX  Lower 32-bits of MSR value.
 237                Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
 238   @param  EDX  Upper 32-bits of MSR value.
 239                Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
 240
 241   <b>Example usage</b>
 242   @code
 243   MSR_HASWELL_E_IA32_MCG_CAP_REGISTER  Msr;
 244
 245   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);
 246   @endcode
 247   @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
 248 **/
 249 #define MSR_HASWELL_E_IA32_MCG_CAP  0x00000179
 250
 251 /**
 252   MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP
 253 **/
 254 typedef union {
 255   ///
 256   /// Individual bit fields
 257   ///
 258   struct {
 259     ///
 260     /// [Bits 7:0] Count.
 261     ///
 262     UINT32    Count       : 8;
 263     ///
 264     /// [Bit 8] MCG_CTL_P.
 265     ///
 266     UINT32    MCG_CTL_P   : 1;
 267     ///
 268     /// [Bit 9] MCG_EXT_P.
 269     ///
 270     UINT32    MCG_EXT_P   : 1;
 271     ///
 272     /// [Bit 10] MCP_CMCI_P.
 273     ///
 274     UINT32    MCP_CMCI_P  : 1;
 275     ///
 276     /// [Bit 11] MCG_TES_P.
 277     ///
 278     UINT32    MCG_TES_P   : 1;
 279     UINT32    Reserved1   : 4;
 280     ///
 281     /// [Bits 23:16] MCG_EXT_CNT.
 282     ///
 283     UINT32    MCG_EXT_CNT : 8;
 284     ///
 285     /// [Bit 24] MCG_SER_P.
 286     ///
 287     UINT32    MCG_SER_P   : 1;
 288     ///
 289     /// [Bit 25] MCG_EM_P.
 290     ///
 291     UINT32    MCG_EM_P    : 1;
 292     ///
 293     /// [Bit 26] MCG_ELOG_P.
 294     ///
 295     UINT32    MCG_ELOG_P  : 1;
 296     UINT32    Reserved2   : 5;
 297     UINT32    Reserved3   : 32;
 298   } Bits;
 299   ///
 300   /// All bit fields as a 32-bit value
 301   ///
 302   UINT32    Uint32;
 303   ///
 304   /// All bit fields as a 64-bit value
 305   ///
 306   UINT64    Uint64;
 307 } MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;
 308
 309 /**
 310   THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
 311   Enhancement. Accessible only while in SMM.
 312
 313   @param  ECX  MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)
 314   @param  EAX  Lower 32-bits of MSR value.
 315                Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
 316   @param  EDX  Upper 32-bits of MSR value.
 317                Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
 318
 319   <b>Example usage</b>
 320   @code
 321   MSR_HASWELL_E_SMM_MCA_CAP_REGISTER  Msr;
 322
 323   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);
 324   AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);
 325   @endcode
 326   @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
 327 **/
 328 #define MSR_HASWELL_E_SMM_MCA_CAP  0x0000017D
 329
 330 /**
 331   MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP
 332 **/
 333 typedef union {
 334   ///
 335   /// Individual bit fields
 336   ///
 337   struct {
 338     UINT32    Reserved1            : 32;
 339     UINT32    Reserved2            : 26;
 340     ///
 341     /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
 342     /// SMM code access restriction is supported and a host-space interface
 343     /// available to SMM handler.
 344     ///
 345     UINT32    SMM_Code_Access_Chk  : 1;
 346     ///
 347     /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
 348     /// SMM long flow indicator is supported and a host-space interface
 349     /// available to SMM handler.
 350     ///
 351     UINT32    Long_Flow_Indication : 1;
 352     UINT32    Reserved3            : 4;
 353   } Bits;
 354   ///
 355   /// All bit fields as a 64-bit value
 356   ///
 357   UINT64    Uint64;
 358 } MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;
 359
 360 /**
 361   Package. MC Bank Error Configuration (R/W).
 362
 363   @param  ECX  MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)
 364   @param  EAX  Lower 32-bits of MSR value.
 365                Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
 366   @param  EDX  Upper 32-bits of MSR value.
 367                Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
 368
 369   <b>Example usage</b>
 370   @code
 371   MSR_HASWELL_E_ERROR_CONTROL_REGISTER  Msr;
 372
 373   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);
 374   AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);
 375   @endcode
 376   @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
 377 **/
 378 #define MSR_HASWELL_E_ERROR_CONTROL  0x0000017F
 379
 380 /**
 381   MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL
 382 **/
 383 typedef union {
 384   ///
 385   /// Individual bit fields
 386   ///
 387   struct {
 388     UINT32    Reserved1         : 1;
 389     ///
 390     /// [Bit 1] MemError Log Enable (R/W)  When set, enables IMC status bank
 391     /// to log additional info in bits 36:32.
 392     ///
 393     UINT32    MemErrorLogEnable : 1;
 394     UINT32    Reserved2         : 30;
 395     UINT32    Reserved3         : 32;
 396   } Bits;
 397   ///
 398   /// All bit fields as a 32-bit value
 399   ///
 400   UINT32    Uint32;
 401   ///
 402   /// All bit fields as a 64-bit value
 403   ///
 404   UINT64    Uint64;
 405 } MSR_HASWELL_E_ERROR_CONTROL_REGISTER;
 406
 407 /**
 408   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 409   RW if MSR_PLATFORM_INFO.[28] = 1.
 410
 411   @param  ECX  MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)
 412   @param  EAX  Lower 32-bits of MSR value.
 413                Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
 414   @param  EDX  Upper 32-bits of MSR value.
 415                Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
 416
 417   <b>Example usage</b>
 418   @code
 419   MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER  Msr;
 420
 421   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);
 422   @endcode
 423   @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 424 **/
 425 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT  0x000001AD
 426
 427 /**
 428   MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT
 429 **/
 430 typedef union {
 431   ///
 432   /// Individual bit fields
 433   ///
 434   struct {
 435     ///
 436     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
 437     /// limit of 1 core active.
 438     ///
 439     UINT32    Maximum1C : 8;
 440     ///
 441     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
 442     /// limit of 2 core active.
 443     ///
 444     UINT32    Maximum2C : 8;
 445     ///
 446     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
 447     /// limit of 3 core active.
 448     ///
 449     UINT32    Maximum3C : 8;
 450     ///
 451     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
 452     /// limit of 4 core active.
 453     ///
 454     UINT32    Maximum4C : 8;
 455     ///
 456     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
 457     /// limit of 5 core active.
 458     ///
 459     UINT32    Maximum5C : 8;
 460     ///
 461     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
 462     /// limit of 6 core active.
 463     ///
 464     UINT32    Maximum6C : 8;
 465     ///
 466     /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
 467     /// limit of 7 core active.
 468     ///
 469     UINT32    Maximum7C : 8;
 470     ///
 471     /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
 472     /// limit of 8 core active.
 473     ///
 474     UINT32    Maximum8C : 8;
 475   } Bits;
 476   ///
 477   /// All bit fields as a 64-bit value
 478   ///
 479   UINT64    Uint64;
 480 } MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;
 481
 482 /**
 483   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 484   RW if MSR_PLATFORM_INFO.[28] = 1.
 485
 486   @param  ECX  MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)
 487   @param  EAX  Lower 32-bits of MSR value.
 488                Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
 489   @param  EDX  Upper 32-bits of MSR value.
 490                Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
 491
 492   <b>Example usage</b>
 493   @code
 494   MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER  Msr;
 495
 496   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);
 497   @endcode
 498   @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
 499 **/
 500 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT1  0x000001AE
 501
 502 /**
 503   MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1
 504 **/
 505 typedef union {
 506   ///
 507   /// Individual bit fields
 508   ///
 509   struct {
 510     ///
 511     /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
 512     /// limit of 9 core active.
 513     ///
 514     UINT32    Maximum9C  : 8;
 515     ///
 516     /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
 517     /// limit of 10 core active.
 518     ///
 519     UINT32    Maximum10C : 8;
 520     ///
 521     /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
 522     /// limit of 11 core active.
 523     ///
 524     UINT32    Maximum11C : 8;
 525     ///
 526     /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
 527     /// limit of 12 core active.
 528     ///
 529     UINT32    Maximum12C : 8;
 530     ///
 531     /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
 532     /// limit of 13 core active.
 533     ///
 534     UINT32    Maximum13C : 8;
 535     ///
 536     /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
 537     /// limit of 14 core active.
 538     ///
 539     UINT32    Maximum14C : 8;
 540     ///
 541     /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
 542     /// limit of 15 core active.
 543     ///
 544     UINT32    Maximum15C : 8;
 545     ///
 546     /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio
 547     /// limit of 16 core active.
 548     ///
 549     UINT32    Maximum16C : 8;
 550   } Bits;
 551   ///
 552   /// All bit fields as a 64-bit value
 553   ///
 554   UINT64    Uint64;
 555 } MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;
 556
 557 /**
 558   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 559   RW if MSR_PLATFORM_INFO.[28] = 1.
 560
 561   @param  ECX  MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)
 562   @param  EAX  Lower 32-bits of MSR value.
 563                Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
 564   @param  EDX  Upper 32-bits of MSR value.
 565                Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
 566
 567   <b>Example usage</b>
 568   @code
 569   MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER  Msr;
 570
 571   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);
 572   @endcode
 573   @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.
 574 **/
 575 #define MSR_HASWELL_E_TURBO_RATIO_LIMIT2  0x000001AF
 576
 577 /**
 578   MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2
 579 **/
 580 typedef union {
 581   ///
 582   /// Individual bit fields
 583   ///
 584   struct {
 585     ///
 586     /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio
 587     /// limit of 17 core active.
 588     ///
 589     UINT32    Maximum17C                            : 8;
 590     ///
 591     /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio
 592     /// limit of 18 core active.
 593     ///
 594     UINT32    Maximum18C                            : 8;
 595     UINT32    Reserved1                             : 16;
 596     UINT32    Reserved2                             : 31;
 597     ///
 598     /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
 599     /// the processor uses override configuration specified in
 600     /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and
 601     /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set
 602     /// configuration (Default).
 603     ///
 604     UINT32    TurboRatioLimitConfigurationSemaphore : 1;
 605   } Bits;
 606   ///
 607   /// All bit fields as a 64-bit value
 608   ///
 609   UINT64    Uint64;
 610 } MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;
 611
 612 /**
 613   Package. Unit Multipliers used in RAPL Interfaces (R/O).
 614
 615   @param  ECX  MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)
 616   @param  EAX  Lower 32-bits of MSR value.
 617                Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
 618   @param  EDX  Upper 32-bits of MSR value.
 619                Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
 620
 621   <b>Example usage</b>
 622   @code
 623   MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER  Msr;
 624
 625   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);
 626   @endcode
 627   @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
 628 **/
 629 #define MSR_HASWELL_E_RAPL_POWER_UNIT  0x00000606
 630
 631 /**
 632   MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT
 633 **/
 634 typedef union {
 635   ///
 636   /// Individual bit fields
 637   ///
 638   struct {
 639     ///
 640     /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
 641     ///
 642     UINT32    PowerUnits        : 4;
 643     UINT32    Reserved1         : 4;
 644     ///
 645     /// [Bits 12:8] Package. Energy Status Units Energy related information
 646     /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
 647     /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
 648     /// micro-joules).
 649     ///
 650     UINT32    EnergyStatusUnits : 5;
 651     UINT32    Reserved2         : 3;
 652     ///
 653     /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
 654     /// Interfaces.".
 655     ///
 656     UINT32    TimeUnits         : 4;
 657     UINT32    Reserved3         : 12;
 658     UINT32    Reserved4         : 32;
 659   } Bits;
 660   ///
 661   /// All bit fields as a 32-bit value
 662   ///
 663   UINT32    Uint32;
 664   ///
 665   /// All bit fields as a 64-bit value
 666   ///
 667   UINT64    Uint64;
 668 } MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;
 669
 670 /**
 671   Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
 672   Domain.".
 673
 674   @param  ECX  MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)
 675   @param  EAX  Lower 32-bits of MSR value.
 676   @param  EDX  Upper 32-bits of MSR value.
 677
 678   <b>Example usage</b>
 679   @code
 680   UINT64  Msr;
 681
 682   Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);
 683   AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);
 684   @endcode
 685   @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
 686 **/
 687 #define MSR_HASWELL_E_DRAM_POWER_LIMIT  0x00000618
 688
 689 /**
 690   Package. DRAM Energy Status (R/O)  Energy Consumed by DRAM devices.
 691
 692   @param  ECX  MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)
 693   @param  EAX  Lower 32-bits of MSR value.
 694                Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
 695   @param  EDX  Upper 32-bits of MSR value.
 696                Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
 697
 698   <b>Example usage</b>
 699   @code
 700   MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER  Msr;
 701
 702   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);
 703   @endcode
 704   @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
 705 **/
 706 #define MSR_HASWELL_E_DRAM_ENERGY_STATUS  0x00000619
 707
 708 /**
 709   MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS
 710 **/
 711 typedef union {
 712   ///
 713   /// Individual bit fields
 714   ///
 715   struct {
 716     ///
 717     /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
 718     /// to enable DRAM RAPL mode 0 (Direct VR).
 719     ///
 720     UINT32    Energy   : 32;
 721     UINT32    Reserved : 32;
 722   } Bits;
 723   ///
 724   /// All bit fields as a 32-bit value
 725   ///
 726   UINT32    Uint32;
 727   ///
 728   /// All bit fields as a 64-bit value
 729   ///
 730   UINT64    Uint64;
 731 } MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;
 732
 733 /**
 734   Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
 735   RAPL Domain.".
 736
 737   @param  ECX  MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)
 738   @param  EAX  Lower 32-bits of MSR value.
 739   @param  EDX  Upper 32-bits of MSR value.
 740
 741   <b>Example usage</b>
 742   @code
 743   UINT64  Msr;
 744
 745   Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);
 746   @endcode
 747   @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
 748 **/
 749 #define MSR_HASWELL_E_DRAM_PERF_STATUS  0x0000061B
 750
 751 /**
 752   Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
 753
 754   @param  ECX  MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)
 755   @param  EAX  Lower 32-bits of MSR value.
 756   @param  EDX  Upper 32-bits of MSR value.
 757
 758   <b>Example usage</b>
 759   @code
 760   UINT64  Msr;
 761
 762   Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);
 763   AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);
 764   @endcode
 765   @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
 766 **/
 767 #define MSR_HASWELL_E_DRAM_POWER_INFO  0x0000061C
 768
 769 /**
 770   Package. Configuration of PCIE PLL Relative to BCLK(R/W).
 771
 772   @param  ECX  MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)
 773   @param  EAX  Lower 32-bits of MSR value.
 774                Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
 775   @param  EDX  Upper 32-bits of MSR value.
 776                Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
 777
 778   <b>Example usage</b>
 779   @code
 780   MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER  Msr;
 781
 782   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);
 783   AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);
 784   @endcode
 785   @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.
 786 **/
 787 #define MSR_HASWELL_E_PCIE_PLL_RATIO  0x0000061E
 788
 789 /**
 790   MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO
 791 **/
 792 typedef union {
 793   ///
 794   /// Individual bit fields
 795   ///
 796   struct {
 797     ///
 798     /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz
 799     /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use
 800     /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz
 801     /// operation.
 802     ///
 803     UINT32    PCIERatio  : 2;
 804     ///
 805     /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of
 806     /// PCIE Ratio.
 807     ///
 808     UINT32    LPLLSelect : 1;
 809     ///
 810     /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out
 811     /// before re-locking Gen2/Gen3 PLLs.
 812     ///
 813     UINT32    LONGRESET  : 1;
 814     UINT32    Reserved1  : 28;
 815     UINT32    Reserved2  : 32;
 816   } Bits;
 817   ///
 818   /// All bit fields as a 32-bit value
 819   ///
 820   UINT32    Uint32;
 821   ///
 822   /// All bit fields as a 64-bit value
 823   ///
 824   UINT64    Uint64;
 825 } MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;
 826
 827 /**
 828   Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
 829   fields represent the widest possible range of uncore frequencies. Writing to
 830   these fields allows software to control the minimum and the maximum
 831   frequency that hardware will select.
 832
 833   @param  ECX  MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)
 834   @param  EAX  Lower 32-bits of MSR value.
 835                Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
 836   @param  EDX  Upper 32-bits of MSR value.
 837                Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
 838
 839   <b>Example usage</b>
 840   @code
 841   MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
 842
 843   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);
 844   AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
 845   @endcode
 846 **/
 847 #define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT  0x00000620
 848
 849 /**
 850   MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT
 851 **/
 852 typedef union {
 853   ///
 854   /// Individual bit fields
 855   ///
 856   struct {
 857     ///
 858     /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
 859     /// LLC/Ring.
 860     ///
 861     UINT32    MAX_RATIO : 7;
 862     UINT32    Reserved1 : 1;
 863     ///
 864     /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
 865     /// possible ratio of the LLC/Ring.
 866     ///
 867     UINT32    MIN_RATIO : 7;
 868     UINT32    Reserved2 : 17;
 869     UINT32    Reserved3 : 32;
 870   } Bits;
 871   ///
 872   /// All bit fields as a 32-bit value
 873   ///
 874   UINT32    Uint32;
 875   ///
 876   /// All bit fields as a 64-bit value
 877   ///
 878   UINT64    Uint64;
 879 } MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;
 880
 881 /**
 882   Package. Reserved (R/O) Reads return 0.
 883
 884   @param  ECX  MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)
 885   @param  EAX  Lower 32-bits of MSR value.
 886   @param  EDX  Upper 32-bits of MSR value.
 887
 888   <b>Example usage</b>
 889   @code
 890   UINT64  Msr;
 891
 892   Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);
 893   @endcode
 894   @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
 895 **/
 896 #define MSR_HASWELL_E_PP0_ENERGY_STATUS  0x00000639
 897
 898 /**
 899   Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
 900   refers to processor core frequency).
 901
 902   @param  ECX  MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)
 903   @param  EAX  Lower 32-bits of MSR value.
 904                Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
 905   @param  EDX  Upper 32-bits of MSR value.
 906                Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
 907
 908   <b>Example usage</b>
 909   @code
 910   MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
 911
 912   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);
 913   AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
 914   @endcode
 915   @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
 916 **/
 917 #define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS  0x00000690
 918
 919 /**
 920   MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS
 921 **/
 922 typedef union {
 923   ///
 924   /// Individual bit fields
 925   ///
 926   struct {
 927     ///
 928     /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
 929     /// reduced below the operating system request due to assertion of
 930     /// external PROCHOT.
 931     ///
 932     UINT32    PROCHOT_Status                                   : 1;
 933     ///
 934     /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
 935     /// operating system request due to a thermal event.
 936     ///
 937     UINT32    ThermalStatus                                    : 1;
 938     ///
 939     /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
 940     /// reduced below the operating system request due to PBM limit.
 941     ///
 942     UINT32    PowerBudgetManagementStatus                      : 1;
 943     ///
 944     /// [Bit 3] Platform Configuration Services Status (R0) When set,
 945     /// frequency is reduced below the operating system request due to PCS
 946     /// limit.
 947     ///
 948     UINT32    PlatformConfigurationServicesStatus              : 1;
 949     UINT32    Reserved1                                        : 1;
 950     ///
 951     /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
 952     /// When set, frequency is reduced below the operating system request
 953     /// because the processor has detected that utilization is low.
 954     ///
 955     UINT32    AutonomousUtilizationBasedFrequencyControlStatus : 1;
 956     ///
 957     /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
 958     /// below the operating system request due to a thermal alert from the
 959     /// Voltage Regulator.
 960     ///
 961     UINT32    VRThermAlertStatus                               : 1;
 962     UINT32    Reserved2                                        : 1;
 963     ///
 964     /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
 965     /// reduced below the operating system request due to electrical design
 966     /// point constraints (e.g. maximum electrical current consumption).
 967     ///
 968     UINT32    ElectricalDesignPointStatus                      : 1;
 969     UINT32    Reserved3                                        : 1;
 970     ///
 971     /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
 972     /// below the operating system request due to Multi-Core Turbo limits.
 973     ///
 974     UINT32    MultiCoreTurboStatus                             : 1;
 975     UINT32    Reserved4                                        : 2;
 976     ///
 977     /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
 978     /// below max non-turbo P1.
 979     ///
 980     UINT32    FrequencyP1Status                                : 1;
 981     ///
 982     /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
 983     /// set, frequency is reduced below max n-core turbo frequency.
 984     ///
 985     UINT32    TurboFrequencyLimitingStatus                     : 1;
 986     ///
 987     /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
 988     /// reduced below the operating system request.
 989     ///
 990     UINT32    FrequencyLimitingStatus                          : 1;
 991     ///
 992     /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
 993     /// has asserted since the log bit was last cleared. This log bit will
 994     /// remain set until cleared by software writing 0.
 995     ///
 996     UINT32    PROCHOT_Log                                      : 1;
 997     ///
 998     /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
 999     /// has asserted since the log bit was last cleared. This log bit will
1000     /// remain set until cleared by software writing 0.
1001     ///
1002     UINT32    ThermalLog                                       : 1;
1003     ///
1004     /// [Bit 18] Power Budget Management Log  When set, indicates that the PBM
1005     /// Status bit has asserted since the log bit was last cleared. This log
1006     /// bit will remain set until cleared by software writing 0.
1007     ///
1008     UINT32    PowerBudgetManagementLog                         : 1;
1009     ///
1010     /// [Bit 19] Platform Configuration Services Log  When set, indicates that
1011     /// the PCS Status bit has asserted since the log bit was last cleared.
1012     /// This log bit will remain set until cleared by software writing 0.
1013     ///
1014     UINT32    PlatformConfigurationServicesLog                 : 1;
1015     UINT32    Reserved5                                        : 1;
1016     ///
1017     /// [Bit 21] Autonomous Utilization-Based Frequency Control Log  When set,
1018     /// indicates that the AUBFC Status bit has asserted since the log bit was
1019     /// last cleared. This log bit will remain set until cleared by software
1020     /// writing 0.
1021     ///
1022     UINT32    AutonomousUtilizationBasedFrequencyControlLog    : 1;
1023     ///
1024     /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
1025     /// Alert Status bit has asserted since the log bit was last cleared. This
1026     /// log bit will remain set until cleared by software writing 0.
1027     ///
1028     UINT32    VRThermAlertLog                                  : 1;
1029     UINT32    Reserved6                                        : 1;
1030     ///
1031     /// [Bit 24] Electrical Design Point Log  When set, indicates that the EDP
1032     /// Status bit has asserted since the log bit was last cleared. This log
1033     /// bit will remain set until cleared by software writing 0.
1034     ///
1035     UINT32    ElectricalDesignPointLog                         : 1;
1036     UINT32    Reserved7                                        : 1;
1037     ///
1038     /// [Bit 26] Multi-Core Turbo Log  When set, indicates that the Multi-Core
1039     /// Turbo Status bit has asserted since the log bit was last cleared. This
1040     /// log bit will remain set until cleared by software writing 0.
1041     ///
1042     UINT32    MultiCoreTurboLog                                : 1;
1043     UINT32    Reserved8                                        : 2;
1044     ///
1045     /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
1046     /// Frequency P1 Status bit has asserted since the log bit was last
1047     /// cleared. This log bit will remain set until cleared by software
1048     /// writing 0.
1049     ///
1050     UINT32    CoreFrequencyP1Log                               : 1;
1051     ///
1052     /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
1053     /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
1054     /// has asserted since the log bit was last cleared. This log bit will
1055     /// remain set until cleared by software writing 0.
1056     ///
1057     UINT32    TurboFrequencyLimitingLog                        : 1;
1058     ///
1059     /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
1060     /// Frequency Limiting Status bit has asserted since the log bit was last
1061     /// cleared. This log bit will remain set until cleared by software
1062     /// writing 0.
1063     ///
1064     UINT32    CoreFrequencyLimitingLog                         : 1;
1065     UINT32    Reserved9                                        : 32;
1066   } Bits;
1067   ///
1068   /// All bit fields as a 32-bit value
1069   ///
1070   UINT32    Uint32;
1071   ///
1072   /// All bit fields as a 64-bit value
1073   ///
1074   UINT64    Uint64;
1075 } MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;
1076
1077 /**
1078   THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,
1079   ECX=0):EBX.RDT-M[bit 12] = 1.
1080
1081   @param  ECX  MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)
1082   @param  EAX  Lower 32-bits of MSR value.
1083                Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
1084   @param  EDX  Upper 32-bits of MSR value.
1085                Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
1086
1087   <b>Example usage</b>
1088   @code
1089   MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER  Msr;
1090
1091   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);
1092   AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);
1093   @endcode
1094   @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
1095 **/
1096 #define MSR_HASWELL_E_IA32_QM_EVTSEL  0x00000C8D
1097
1098 /**
1099   MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL
1100 **/
1101 typedef union {
1102   ///
1103   /// Individual bit fields
1104   ///
1105   struct {
1106     ///
1107     /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3
1108     /// occupancy monitoring all other encoding reserved..
1109     ///
1110     UINT32    EventID   : 8;
1111     UINT32    Reserved1 : 24;
1112     ///
1113     /// [Bits 41:32] RMID (RW).
1114     ///
1115     UINT32    RMID      : 10;
1116     UINT32    Reserved2 : 22;
1117   } Bits;
1118   ///
1119   /// All bit fields as a 64-bit value
1120   ///
1121   UINT64    Uint64;
1122 } MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;
1123
1124 /**
1125   THREAD. Resource Association Register (R/W)..
1126
1127   @param  ECX  MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)
1128   @param  EAX  Lower 32-bits of MSR value.
1129                Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
1130   @param  EDX  Upper 32-bits of MSR value.
1131                Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
1132
1133   <b>Example usage</b>
1134   @code
1135   MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER  Msr;
1136
1137   Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);
1138   AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);
1139   @endcode
1140   @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
1141 **/
1142 #define MSR_HASWELL_E_IA32_PQR_ASSOC  0x00000C8F
1143
1144 /**
1145   MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC
1146 **/
1147 typedef union {
1148   ///
1149   /// Individual bit fields
1150   ///
1151   struct {
1152     ///
1153     /// [Bits 9:0] RMID.
1154     ///
1155     UINT32    RMID      : 10;
1156     UINT32    Reserved1 : 22;
1157     UINT32    Reserved2 : 32;
1158   } Bits;
1159   ///
1160   /// All bit fields as a 32-bit value
1161   ///
1162   UINT32    Uint32;
1163   ///
1164   /// All bit fields as a 64-bit value
1165   ///
1166   UINT64    Uint64;
1167 } MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;
1168
1169 /**
1170   Package. Uncore perfmon per-socket global control.
1171
1172   @param  ECX  MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)
1173   @param  EAX  Lower 32-bits of MSR value.
1174   @param  EDX  Upper 32-bits of MSR value.
1175
1176   <b>Example usage</b>
1177   @code
1178   UINT64  Msr;
1179
1180   Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);
1181   AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);
1182   @endcode
1183   @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
1184 **/
1185 #define MSR_HASWELL_E_PMON_GLOBAL_CTL  0x00000700
1186
1187 /**
1188   Package. Uncore perfmon per-socket global status.
1189
1190   @param  ECX  MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)
1191   @param  EAX  Lower 32-bits of MSR value.
1192   @param  EDX  Upper 32-bits of MSR value.
1193
1194   <b>Example usage</b>
1195   @code
1196   UINT64  Msr;
1197
1198   Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);
1199   AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);
1200   @endcode
1201   @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
1202 **/
1203 #define MSR_HASWELL_E_PMON_GLOBAL_STATUS  0x00000701
1204
1205 /**
1206   Package. Uncore perfmon per-socket global configuration.
1207
1208   @param  ECX  MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)
1209   @param  EAX  Lower 32-bits of MSR value.
1210   @param  EDX  Upper 32-bits of MSR value.
1211
1212   <b>Example usage</b>
1213   @code
1214   UINT64  Msr;
1215
1216   Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);
1217   AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);
1218   @endcode
1219   @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
1220 **/
1221 #define MSR_HASWELL_E_PMON_GLOBAL_CONFIG  0x00000702
1222
1223 /**
1224   Package. Uncore U-box UCLK fixed counter control.
1225
1226   @param  ECX  MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)
1227   @param  EAX  Lower 32-bits of MSR value.
1228   @param  EDX  Upper 32-bits of MSR value.
1229
1230   <b>Example usage</b>
1231   @code
1232   UINT64  Msr;
1233
1234   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);
1235   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);
1236   @endcode
1237   @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
1238 **/
1239 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL  0x00000703
1240
1241 /**
1242   Package. Uncore U-box UCLK fixed counter.
1243
1244   @param  ECX  MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)
1245   @param  EAX  Lower 32-bits of MSR value.
1246   @param  EDX  Upper 32-bits of MSR value.
1247
1248   <b>Example usage</b>
1249   @code
1250   UINT64  Msr;
1251
1252   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);
1253   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);
1254   @endcode
1255   @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
1256 **/
1257 #define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR  0x00000704
1258
1259 /**
1260   Package. Uncore U-box perfmon event select for U-box counter 0.
1261
1262   @param  ECX  MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)
1263   @param  EAX  Lower 32-bits of MSR value.
1264   @param  EDX  Upper 32-bits of MSR value.
1265
1266   <b>Example usage</b>
1267   @code
1268   UINT64  Msr;
1269
1270   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);
1271   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);
1272   @endcode
1273   @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
1274 **/
1275 #define MSR_HASWELL_E_U_PMON_EVNTSEL0  0x00000705
1276
1277 /**
1278   Package. Uncore U-box perfmon event select for U-box counter 1.
1279
1280   @param  ECX  MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)
1281   @param  EAX  Lower 32-bits of MSR value.
1282   @param  EDX  Upper 32-bits of MSR value.
1283
1284   <b>Example usage</b>
1285   @code
1286   UINT64  Msr;
1287
1288   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);
1289   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);
1290   @endcode
1291   @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
1292 **/
1293 #define MSR_HASWELL_E_U_PMON_EVNTSEL1  0x00000706
1294
1295 /**
1296   Package. Uncore U-box perfmon U-box wide status.
1297
1298   @param  ECX  MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)
1299   @param  EAX  Lower 32-bits of MSR value.
1300   @param  EDX  Upper 32-bits of MSR value.
1301
1302   <b>Example usage</b>
1303   @code
1304   UINT64  Msr;
1305
1306   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);
1307   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);
1308   @endcode
1309   @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
1310 **/
1311 #define MSR_HASWELL_E_U_PMON_BOX_STATUS  0x00000708
1312
1313 /**
1314   Package. Uncore U-box perfmon counter 0.
1315
1316   @param  ECX  MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)
1317   @param  EAX  Lower 32-bits of MSR value.
1318   @param  EDX  Upper 32-bits of MSR value.
1319
1320   <b>Example usage</b>
1321   @code
1322   UINT64  Msr;
1323
1324   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);
1325   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);
1326   @endcode
1327   @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
1328 **/
1329 #define MSR_HASWELL_E_U_PMON_CTR0  0x00000709
1330
1331 /**
1332   Package. Uncore U-box perfmon counter 1.
1333
1334   @param  ECX  MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)
1335   @param  EAX  Lower 32-bits of MSR value.
1336   @param  EDX  Upper 32-bits of MSR value.
1337
1338   <b>Example usage</b>
1339   @code
1340   UINT64  Msr;
1341
1342   Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);
1343   AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);
1344   @endcode
1345   @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
1346 **/
1347 #define MSR_HASWELL_E_U_PMON_CTR1  0x0000070A
1348
1349 /**
1350   Package. Uncore PCU perfmon for PCU-box-wide control.
1351
1352   @param  ECX  MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)
1353   @param  EAX  Lower 32-bits of MSR value.
1354   @param  EDX  Upper 32-bits of MSR value.
1355
1356   <b>Example usage</b>
1357   @code
1358   UINT64  Msr;
1359
1360   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);
1361   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);
1362   @endcode
1363   @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
1364 **/
1365 #define MSR_HASWELL_E_PCU_PMON_BOX_CTL  0x00000710
1366
1367 /**
1368   Package. Uncore PCU perfmon event select for PCU counter 0.
1369
1370   @param  ECX  MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)
1371   @param  EAX  Lower 32-bits of MSR value.
1372   @param  EDX  Upper 32-bits of MSR value.
1373
1374   <b>Example usage</b>
1375   @code
1376   UINT64  Msr;
1377
1378   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);
1379   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);
1380   @endcode
1381   @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
1382 **/
1383 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL0  0x00000711
1384
1385 /**
1386   Package. Uncore PCU perfmon event select for PCU counter 1.
1387
1388   @param  ECX  MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)
1389   @param  EAX  Lower 32-bits of MSR value.
1390   @param  EDX  Upper 32-bits of MSR value.
1391
1392   <b>Example usage</b>
1393   @code
1394   UINT64  Msr;
1395
1396   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);
1397   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);
1398   @endcode
1399   @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
1400 **/
1401 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL1  0x00000712
1402
1403 /**
1404   Package. Uncore PCU perfmon event select for PCU counter 2.
1405
1406   @param  ECX  MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)
1407   @param  EAX  Lower 32-bits of MSR value.
1408   @param  EDX  Upper 32-bits of MSR value.
1409
1410   <b>Example usage</b>
1411   @code
1412   UINT64  Msr;
1413
1414   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);
1415   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);
1416   @endcode
1417   @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
1418 **/
1419 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL2  0x00000713
1420
1421 /**
1422   Package. Uncore PCU perfmon event select for PCU counter 3.
1423
1424   @param  ECX  MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)
1425   @param  EAX  Lower 32-bits of MSR value.
1426   @param  EDX  Upper 32-bits of MSR value.
1427
1428   <b>Example usage</b>
1429   @code
1430   UINT64  Msr;
1431
1432   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);
1433   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);
1434   @endcode
1435   @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
1436 **/
1437 #define MSR_HASWELL_E_PCU_PMON_EVNTSEL3  0x00000714
1438
1439 /**
1440   Package. Uncore PCU perfmon box-wide filter.
1441
1442   @param  ECX  MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)
1443   @param  EAX  Lower 32-bits of MSR value.
1444   @param  EDX  Upper 32-bits of MSR value.
1445
1446   <b>Example usage</b>
1447   @code
1448   UINT64  Msr;
1449
1450   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);
1451   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);
1452   @endcode
1453   @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
1454 **/
1455 #define MSR_HASWELL_E_PCU_PMON_BOX_FILTER  0x00000715
1456
1457 /**
1458   Package. Uncore PCU perfmon box wide status.
1459
1460   @param  ECX  MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)
1461   @param  EAX  Lower 32-bits of MSR value.
1462   @param  EDX  Upper 32-bits of MSR value.
1463
1464   <b>Example usage</b>
1465   @code
1466   UINT64  Msr;
1467
1468   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);
1469   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);
1470   @endcode
1471   @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
1472 **/
1473 #define MSR_HASWELL_E_PCU_PMON_BOX_STATUS  0x00000716
1474
1475 /**
1476   Package. Uncore PCU perfmon counter 0.
1477
1478   @param  ECX  MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)
1479   @param  EAX  Lower 32-bits of MSR value.
1480   @param  EDX  Upper 32-bits of MSR value.
1481
1482   <b>Example usage</b>
1483   @code
1484   UINT64  Msr;
1485
1486   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);
1487   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);
1488   @endcode
1489   @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
1490 **/
1491 #define MSR_HASWELL_E_PCU_PMON_CTR0  0x00000717
1492
1493 /**
1494   Package. Uncore PCU perfmon counter 1.
1495
1496   @param  ECX  MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)
1497   @param  EAX  Lower 32-bits of MSR value.
1498   @param  EDX  Upper 32-bits of MSR value.
1499
1500   <b>Example usage</b>
1501   @code
1502   UINT64  Msr;
1503
1504   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);
1505   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);
1506   @endcode
1507   @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
1508 **/
1509 #define MSR_HASWELL_E_PCU_PMON_CTR1  0x00000718
1510
1511 /**
1512   Package. Uncore PCU perfmon counter 2.
1513
1514   @param  ECX  MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)
1515   @param  EAX  Lower 32-bits of MSR value.
1516   @param  EDX  Upper 32-bits of MSR value.
1517
1518   <b>Example usage</b>
1519   @code
1520   UINT64  Msr;
1521
1522   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);
1523   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);
1524   @endcode
1525   @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
1526 **/
1527 #define MSR_HASWELL_E_PCU_PMON_CTR2  0x00000719
1528
1529 /**
1530   Package. Uncore PCU perfmon counter 3.
1531
1532   @param  ECX  MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)
1533   @param  EAX  Lower 32-bits of MSR value.
1534   @param  EDX  Upper 32-bits of MSR value.
1535
1536   <b>Example usage</b>
1537   @code
1538   UINT64  Msr;
1539
1540   Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);
1541   AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);
1542   @endcode
1543   @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
1544 **/
1545 #define MSR_HASWELL_E_PCU_PMON_CTR3  0x0000071A
1546
1547 /**
1548   Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.
1549
1550   @param  ECX  MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)
1551   @param  EAX  Lower 32-bits of MSR value.
1552   @param  EDX  Upper 32-bits of MSR value.
1553
1554   <b>Example usage</b>
1555   @code
1556   UINT64  Msr;
1557
1558   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);
1559   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);
1560   @endcode
1561   @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.
1562 **/
1563 #define MSR_HASWELL_E_S0_PMON_BOX_CTL  0x00000720
1564
1565 /**
1566   Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.
1567
1568   @param  ECX  MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)
1569   @param  EAX  Lower 32-bits of MSR value.
1570   @param  EDX  Upper 32-bits of MSR value.
1571
1572   <b>Example usage</b>
1573   @code
1574   UINT64  Msr;
1575
1576   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);
1577   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);
1578   @endcode
1579   @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.
1580 **/
1581 #define MSR_HASWELL_E_S0_PMON_EVNTSEL0  0x00000721
1582
1583 /**
1584   Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.
1585
1586   @param  ECX  MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)
1587   @param  EAX  Lower 32-bits of MSR value.
1588   @param  EDX  Upper 32-bits of MSR value.
1589
1590   <b>Example usage</b>
1591   @code
1592   UINT64  Msr;
1593
1594   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);
1595   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);
1596   @endcode
1597   @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.
1598 **/
1599 #define MSR_HASWELL_E_S0_PMON_EVNTSEL1  0x00000722
1600
1601 /**
1602   Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.
1603
1604   @param  ECX  MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)
1605   @param  EAX  Lower 32-bits of MSR value.
1606   @param  EDX  Upper 32-bits of MSR value.
1607
1608   <b>Example usage</b>
1609   @code
1610   UINT64  Msr;
1611
1612   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);
1613   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);
1614   @endcode
1615   @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.
1616 **/
1617 #define MSR_HASWELL_E_S0_PMON_EVNTSEL2  0x00000723
1618
1619 /**
1620   Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.
1621
1622   @param  ECX  MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)
1623   @param  EAX  Lower 32-bits of MSR value.
1624   @param  EDX  Upper 32-bits of MSR value.
1625
1626   <b>Example usage</b>
1627   @code
1628   UINT64  Msr;
1629
1630   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);
1631   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);
1632   @endcode
1633   @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.
1634 **/
1635 #define MSR_HASWELL_E_S0_PMON_EVNTSEL3  0x00000724
1636
1637 /**
1638   Package. Uncore SBo 0 perfmon box-wide filter.
1639
1640   @param  ECX  MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)
1641   @param  EAX  Lower 32-bits of MSR value.
1642   @param  EDX  Upper 32-bits of MSR value.
1643
1644   <b>Example usage</b>
1645   @code
1646   UINT64  Msr;
1647
1648   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);
1649   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);
1650   @endcode
1651   @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.
1652 **/
1653 #define MSR_HASWELL_E_S0_PMON_BOX_FILTER  0x00000725
1654
1655 /**
1656   Package. Uncore SBo 0 perfmon counter 0.
1657
1658   @param  ECX  MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)
1659   @param  EAX  Lower 32-bits of MSR value.
1660   @param  EDX  Upper 32-bits of MSR value.
1661
1662   <b>Example usage</b>
1663   @code
1664   UINT64  Msr;
1665
1666   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);
1667   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);
1668   @endcode
1669   @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
1670 **/
1671 #define MSR_HASWELL_E_S0_PMON_CTR0  0x00000726
1672
1673 /**
1674   Package. Uncore SBo 0 perfmon counter 1.
1675
1676   @param  ECX  MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)
1677   @param  EAX  Lower 32-bits of MSR value.
1678   @param  EDX  Upper 32-bits of MSR value.
1679
1680   <b>Example usage</b>
1681   @code
1682   UINT64  Msr;
1683
1684   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);
1685   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);
1686   @endcode
1687   @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
1688 **/
1689 #define MSR_HASWELL_E_S0_PMON_CTR1  0x00000727
1690
1691 /**
1692   Package. Uncore SBo 0 perfmon counter 2.
1693
1694   @param  ECX  MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)
1695   @param  EAX  Lower 32-bits of MSR value.
1696   @param  EDX  Upper 32-bits of MSR value.
1697
1698   <b>Example usage</b>
1699   @code
1700   UINT64  Msr;
1701
1702   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);
1703   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);
1704   @endcode
1705   @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
1706 **/
1707 #define MSR_HASWELL_E_S0_PMON_CTR2  0x00000728
1708
1709 /**
1710   Package. Uncore SBo 0 perfmon counter 3.
1711
1712   @param  ECX  MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)
1713   @param  EAX  Lower 32-bits of MSR value.
1714   @param  EDX  Upper 32-bits of MSR value.
1715
1716   <b>Example usage</b>
1717   @code
1718   UINT64  Msr;
1719
1720   Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);
1721   AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);
1722   @endcode
1723   @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
1724 **/
1725 #define MSR_HASWELL_E_S0_PMON_CTR3  0x00000729
1726
1727 /**
1728   Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.
1729
1730   @param  ECX  MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)
1731   @param  EAX  Lower 32-bits of MSR value.
1732   @param  EDX  Upper 32-bits of MSR value.
1733
1734   <b>Example usage</b>
1735   @code
1736   UINT64  Msr;
1737
1738   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);
1739   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);
1740   @endcode
1741   @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.
1742 **/
1743 #define MSR_HASWELL_E_S1_PMON_BOX_CTL  0x0000072A
1744
1745 /**
1746   Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.
1747
1748   @param  ECX  MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)
1749   @param  EAX  Lower 32-bits of MSR value.
1750   @param  EDX  Upper 32-bits of MSR value.
1751
1752   <b>Example usage</b>
1753   @code
1754   UINT64  Msr;
1755
1756   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);
1757   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);
1758   @endcode
1759   @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.
1760 **/
1761 #define MSR_HASWELL_E_S1_PMON_EVNTSEL0  0x0000072B
1762
1763 /**
1764   Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.
1765
1766   @param  ECX  MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)
1767   @param  EAX  Lower 32-bits of MSR value.
1768   @param  EDX  Upper 32-bits of MSR value.
1769
1770   <b>Example usage</b>
1771   @code
1772   UINT64  Msr;
1773
1774   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);
1775   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);
1776   @endcode
1777   @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.
1778 **/
1779 #define MSR_HASWELL_E_S1_PMON_EVNTSEL1  0x0000072C
1780
1781 /**
1782   Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.
1783
1784   @param  ECX  MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)
1785   @param  EAX  Lower 32-bits of MSR value.
1786   @param  EDX  Upper 32-bits of MSR value.
1787
1788   <b>Example usage</b>
1789   @code
1790   UINT64  Msr;
1791
1792   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);
1793   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);
1794   @endcode
1795   @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.
1796 **/
1797 #define MSR_HASWELL_E_S1_PMON_EVNTSEL2  0x0000072D
1798
1799 /**
1800   Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.
1801
1802   @param  ECX  MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)
1803   @param  EAX  Lower 32-bits of MSR value.
1804   @param  EDX  Upper 32-bits of MSR value.
1805
1806   <b>Example usage</b>
1807   @code
1808   UINT64  Msr;
1809
1810   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);
1811   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);
1812   @endcode
1813   @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.
1814 **/
1815 #define MSR_HASWELL_E_S1_PMON_EVNTSEL3  0x0000072E
1816
1817 /**
1818   Package. Uncore SBo 1 perfmon box-wide filter.
1819
1820   @param  ECX  MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)
1821   @param  EAX  Lower 32-bits of MSR value.
1822   @param  EDX  Upper 32-bits of MSR value.
1823
1824   <b>Example usage</b>
1825   @code
1826   UINT64  Msr;
1827
1828   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);
1829   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);
1830   @endcode
1831   @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.
1832 **/
1833 #define MSR_HASWELL_E_S1_PMON_BOX_FILTER  0x0000072F
1834
1835 /**
1836   Package. Uncore SBo 1 perfmon counter 0.
1837
1838   @param  ECX  MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)
1839   @param  EAX  Lower 32-bits of MSR value.
1840   @param  EDX  Upper 32-bits of MSR value.
1841
1842   <b>Example usage</b>
1843   @code
1844   UINT64  Msr;
1845
1846   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);
1847   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);
1848   @endcode
1849   @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
1850 **/
1851 #define MSR_HASWELL_E_S1_PMON_CTR0  0x00000730
1852
1853 /**
1854   Package. Uncore SBo 1 perfmon counter 1.
1855
1856   @param  ECX  MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)
1857   @param  EAX  Lower 32-bits of MSR value.
1858   @param  EDX  Upper 32-bits of MSR value.
1859
1860   <b>Example usage</b>
1861   @code
1862   UINT64  Msr;
1863
1864   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);
1865   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);
1866   @endcode
1867   @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
1868 **/
1869 #define MSR_HASWELL_E_S1_PMON_CTR1  0x00000731
1870
1871 /**
1872   Package. Uncore SBo 1 perfmon counter 2.
1873
1874   @param  ECX  MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)
1875   @param  EAX  Lower 32-bits of MSR value.
1876   @param  EDX  Upper 32-bits of MSR value.
1877
1878   <b>Example usage</b>
1879   @code
1880   UINT64  Msr;
1881
1882   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);
1883   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);
1884   @endcode
1885   @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
1886 **/
1887 #define MSR_HASWELL_E_S1_PMON_CTR2  0x00000732
1888
1889 /**
1890   Package. Uncore SBo 1 perfmon counter 3.
1891
1892   @param  ECX  MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)
1893   @param  EAX  Lower 32-bits of MSR value.
1894   @param  EDX  Upper 32-bits of MSR value.
1895
1896   <b>Example usage</b>
1897   @code
1898   UINT64  Msr;
1899
1900   Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);
1901   AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);
1902   @endcode
1903   @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
1904 **/
1905 #define MSR_HASWELL_E_S1_PMON_CTR3  0x00000733
1906
1907 /**
1908   Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.
1909
1910   @param  ECX  MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)
1911   @param  EAX  Lower 32-bits of MSR value.
1912   @param  EDX  Upper 32-bits of MSR value.
1913
1914   <b>Example usage</b>
1915   @code
1916   UINT64  Msr;
1917
1918   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);
1919   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);
1920   @endcode
1921   @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.
1922 **/
1923 #define MSR_HASWELL_E_S2_PMON_BOX_CTL  0x00000734
1924
1925 /**
1926   Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.
1927
1928   @param  ECX  MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)
1929   @param  EAX  Lower 32-bits of MSR value.
1930   @param  EDX  Upper 32-bits of MSR value.
1931
1932   <b>Example usage</b>
1933   @code
1934   UINT64  Msr;
1935
1936   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);
1937   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);
1938   @endcode
1939   @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.
1940 **/
1941 #define MSR_HASWELL_E_S2_PMON_EVNTSEL0  0x00000735
1942
1943 /**
1944   Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.
1945
1946   @param  ECX  MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)
1947   @param  EAX  Lower 32-bits of MSR value.
1948   @param  EDX  Upper 32-bits of MSR value.
1949
1950   <b>Example usage</b>
1951   @code
1952   UINT64  Msr;
1953
1954   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);
1955   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);
1956   @endcode
1957   @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.
1958 **/
1959 #define MSR_HASWELL_E_S2_PMON_EVNTSEL1  0x00000736
1960
1961 /**
1962   Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.
1963
1964   @param  ECX  MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)
1965   @param  EAX  Lower 32-bits of MSR value.
1966   @param  EDX  Upper 32-bits of MSR value.
1967
1968   <b>Example usage</b>
1969   @code
1970   UINT64  Msr;
1971
1972   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);
1973   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);
1974   @endcode
1975   @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.
1976 **/
1977 #define MSR_HASWELL_E_S2_PMON_EVNTSEL2  0x00000737
1978
1979 /**
1980   Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.
1981
1982   @param  ECX  MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)
1983   @param  EAX  Lower 32-bits of MSR value.
1984   @param  EDX  Upper 32-bits of MSR value.
1985
1986   <b>Example usage</b>
1987   @code
1988   UINT64  Msr;
1989
1990   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);
1991   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);
1992   @endcode
1993   @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.
1994 **/
1995 #define MSR_HASWELL_E_S2_PMON_EVNTSEL3  0x00000738
1996
1997 /**
1998   Package. Uncore SBo 2 perfmon box-wide filter.
1999
2000   @param  ECX  MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)
2001   @param  EAX  Lower 32-bits of MSR value.
2002   @param  EDX  Upper 32-bits of MSR value.
2003
2004   <b>Example usage</b>
2005   @code
2006   UINT64  Msr;
2007
2008   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);
2009   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);
2010   @endcode
2011   @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.
2012 **/
2013 #define MSR_HASWELL_E_S2_PMON_BOX_FILTER  0x00000739
2014
2015 /**
2016   Package. Uncore SBo 2 perfmon counter 0.
2017
2018   @param  ECX  MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)
2019   @param  EAX  Lower 32-bits of MSR value.
2020   @param  EDX  Upper 32-bits of MSR value.
2021
2022   <b>Example usage</b>
2023   @code
2024   UINT64  Msr;
2025
2026   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);
2027   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);
2028   @endcode
2029   @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.
2030 **/
2031 #define MSR_HASWELL_E_S2_PMON_CTR0  0x0000073A
2032
2033 /**
2034   Package. Uncore SBo 2 perfmon counter 1.
2035
2036   @param  ECX  MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)
2037   @param  EAX  Lower 32-bits of MSR value.
2038   @param  EDX  Upper 32-bits of MSR value.
2039
2040   <b>Example usage</b>
2041   @code
2042   UINT64  Msr;
2043
2044   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);
2045   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);
2046   @endcode
2047   @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.
2048 **/
2049 #define MSR_HASWELL_E_S2_PMON_CTR1  0x0000073B
2050
2051 /**
2052   Package. Uncore SBo 2 perfmon counter 2.
2053
2054   @param  ECX  MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)
2055   @param  EAX  Lower 32-bits of MSR value.
2056   @param  EDX  Upper 32-bits of MSR value.
2057
2058   <b>Example usage</b>
2059   @code
2060   UINT64  Msr;
2061
2062   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);
2063   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);
2064   @endcode
2065   @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.
2066 **/
2067 #define MSR_HASWELL_E_S2_PMON_CTR2  0x0000073C
2068
2069 /**
2070   Package. Uncore SBo 2 perfmon counter 3.
2071
2072   @param  ECX  MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)
2073   @param  EAX  Lower 32-bits of MSR value.
2074   @param  EDX  Upper 32-bits of MSR value.
2075
2076   <b>Example usage</b>
2077   @code
2078   UINT64  Msr;
2079
2080   Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);
2081   AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);
2082   @endcode
2083   @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.
2084 **/
2085 #define MSR_HASWELL_E_S2_PMON_CTR3  0x0000073D
2086
2087 /**
2088   Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.
2089
2090   @param  ECX  MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)
2091   @param  EAX  Lower 32-bits of MSR value.
2092   @param  EDX  Upper 32-bits of MSR value.
2093
2094   <b>Example usage</b>
2095   @code
2096   UINT64  Msr;
2097
2098   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);
2099   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);
2100   @endcode
2101   @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.
2102 **/
2103 #define MSR_HASWELL_E_S3_PMON_BOX_CTL  0x0000073E
2104
2105 /**
2106   Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.
2107
2108   @param  ECX  MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)
2109   @param  EAX  Lower 32-bits of MSR value.
2110   @param  EDX  Upper 32-bits of MSR value.
2111
2112   <b>Example usage</b>
2113   @code
2114   UINT64  Msr;
2115
2116   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);
2117   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);
2118   @endcode
2119   @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.
2120 **/
2121 #define MSR_HASWELL_E_S3_PMON_EVNTSEL0  0x0000073F
2122
2123 /**
2124   Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.
2125
2126   @param  ECX  MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)
2127   @param  EAX  Lower 32-bits of MSR value.
2128   @param  EDX  Upper 32-bits of MSR value.
2129
2130   <b>Example usage</b>
2131   @code
2132   UINT64  Msr;
2133
2134   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);
2135   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);
2136   @endcode
2137   @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.
2138 **/
2139 #define MSR_HASWELL_E_S3_PMON_EVNTSEL1  0x00000740
2140
2141 /**
2142   Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.
2143
2144   @param  ECX  MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)
2145   @param  EAX  Lower 32-bits of MSR value.
2146   @param  EDX  Upper 32-bits of MSR value.
2147
2148   <b>Example usage</b>
2149   @code
2150   UINT64  Msr;
2151
2152   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);
2153   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);
2154   @endcode
2155   @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.
2156 **/
2157 #define MSR_HASWELL_E_S3_PMON_EVNTSEL2  0x00000741
2158
2159 /**
2160   Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.
2161
2162   @param  ECX  MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)
2163   @param  EAX  Lower 32-bits of MSR value.
2164   @param  EDX  Upper 32-bits of MSR value.
2165
2166   <b>Example usage</b>
2167   @code
2168   UINT64  Msr;
2169
2170   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);
2171   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);
2172   @endcode
2173   @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.
2174 **/
2175 #define MSR_HASWELL_E_S3_PMON_EVNTSEL3  0x00000742
2176
2177 /**
2178   Package. Uncore SBo 3 perfmon box-wide filter.
2179
2180   @param  ECX  MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)
2181   @param  EAX  Lower 32-bits of MSR value.
2182   @param  EDX  Upper 32-bits of MSR value.
2183
2184   <b>Example usage</b>
2185   @code
2186   UINT64  Msr;
2187
2188   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);
2189   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);
2190   @endcode
2191   @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.
2192 **/
2193 #define MSR_HASWELL_E_S3_PMON_BOX_FILTER  0x00000743
2194
2195 /**
2196   Package. Uncore SBo 3 perfmon counter 0.
2197
2198   @param  ECX  MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)
2199   @param  EAX  Lower 32-bits of MSR value.
2200   @param  EDX  Upper 32-bits of MSR value.
2201
2202   <b>Example usage</b>
2203   @code
2204   UINT64  Msr;
2205
2206   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);
2207   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);
2208   @endcode
2209   @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.
2210 **/
2211 #define MSR_HASWELL_E_S3_PMON_CTR0  0x00000744
2212
2213 /**
2214   Package. Uncore SBo 3 perfmon counter 1.
2215
2216   @param  ECX  MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)
2217   @param  EAX  Lower 32-bits of MSR value.
2218   @param  EDX  Upper 32-bits of MSR value.
2219
2220   <b>Example usage</b>
2221   @code
2222   UINT64  Msr;
2223
2224   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);
2225   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);
2226   @endcode
2227   @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.
2228 **/
2229 #define MSR_HASWELL_E_S3_PMON_CTR1  0x00000745
2230
2231 /**
2232   Package. Uncore SBo 3 perfmon counter 2.
2233
2234   @param  ECX  MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)
2235   @param  EAX  Lower 32-bits of MSR value.
2236   @param  EDX  Upper 32-bits of MSR value.
2237
2238   <b>Example usage</b>
2239   @code
2240   UINT64  Msr;
2241
2242   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);
2243   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);
2244   @endcode
2245   @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.
2246 **/
2247 #define MSR_HASWELL_E_S3_PMON_CTR2  0x00000746
2248
2249 /**
2250   Package. Uncore SBo 3 perfmon counter 3.
2251
2252   @param  ECX  MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)
2253   @param  EAX  Lower 32-bits of MSR value.
2254   @param  EDX  Upper 32-bits of MSR value.
2255
2256   <b>Example usage</b>
2257   @code
2258   UINT64  Msr;
2259
2260   Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);
2261   AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);
2262   @endcode
2263   @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.
2264 **/
2265 #define MSR_HASWELL_E_S3_PMON_CTR3  0x00000747
2266
2267 /**
2268   Package. Uncore C-box 0 perfmon for box-wide control.
2269
2270   @param  ECX  MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)
2271   @param  EAX  Lower 32-bits of MSR value.
2272   @param  EDX  Upper 32-bits of MSR value.
2273
2274   <b>Example usage</b>
2275   @code
2276   UINT64  Msr;
2277
2278   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);
2279   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);
2280   @endcode
2281   @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
2282 **/
2283 #define MSR_HASWELL_E_C0_PMON_BOX_CTL  0x00000E00
2284
2285 /**
2286   Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
2287
2288   @param  ECX  MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)
2289   @param  EAX  Lower 32-bits of MSR value.
2290   @param  EDX  Upper 32-bits of MSR value.
2291
2292   <b>Example usage</b>
2293   @code
2294   UINT64  Msr;
2295
2296   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);
2297   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);
2298   @endcode
2299   @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
2300 **/
2301 #define MSR_HASWELL_E_C0_PMON_EVNTSEL0  0x00000E01
2302
2303 /**
2304   Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
2305
2306   @param  ECX  MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)
2307   @param  EAX  Lower 32-bits of MSR value.
2308   @param  EDX  Upper 32-bits of MSR value.
2309
2310   <b>Example usage</b>
2311   @code
2312   UINT64  Msr;
2313
2314   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);
2315   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);
2316   @endcode
2317   @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
2318 **/
2319 #define MSR_HASWELL_E_C0_PMON_EVNTSEL1  0x00000E02
2320
2321 /**
2322   Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
2323
2324   @param  ECX  MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)
2325   @param  EAX  Lower 32-bits of MSR value.
2326   @param  EDX  Upper 32-bits of MSR value.
2327
2328   <b>Example usage</b>
2329   @code
2330   UINT64  Msr;
2331
2332   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);
2333   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);
2334   @endcode
2335   @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
2336 **/
2337 #define MSR_HASWELL_E_C0_PMON_EVNTSEL2  0x00000E03
2338
2339 /**
2340   Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
2341
2342   @param  ECX  MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)
2343   @param  EAX  Lower 32-bits of MSR value.
2344   @param  EDX  Upper 32-bits of MSR value.
2345
2346   <b>Example usage</b>
2347   @code
2348   UINT64  Msr;
2349
2350   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);
2351   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);
2352   @endcode
2353   @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
2354 **/
2355 #define MSR_HASWELL_E_C0_PMON_EVNTSEL3  0x00000E04
2356
2357 /**
2358   Package. Uncore C-box 0 perfmon box wide filter 0.
2359
2360   @param  ECX  MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)
2361   @param  EAX  Lower 32-bits of MSR value.
2362   @param  EDX  Upper 32-bits of MSR value.
2363
2364   <b>Example usage</b>
2365   @code
2366   UINT64  Msr;
2367
2368   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);
2369   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);
2370   @endcode
2371   @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.
2372 **/
2373 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER0  0x00000E05
2374
2375 /**
2376   Package. Uncore C-box 0 perfmon box wide filter 1.
2377
2378   @param  ECX  MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)
2379   @param  EAX  Lower 32-bits of MSR value.
2380   @param  EDX  Upper 32-bits of MSR value.
2381
2382   <b>Example usage</b>
2383   @code
2384   UINT64  Msr;
2385
2386   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);
2387   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);
2388   @endcode
2389   @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
2390 **/
2391 #define MSR_HASWELL_E_C0_PMON_BOX_FILTER1  0x00000E06
2392
2393 /**
2394   Package. Uncore C-box 0 perfmon box wide status.
2395
2396   @param  ECX  MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)
2397   @param  EAX  Lower 32-bits of MSR value.
2398   @param  EDX  Upper 32-bits of MSR value.
2399
2400   <b>Example usage</b>
2401   @code
2402   UINT64  Msr;
2403
2404   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);
2405   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);
2406   @endcode
2407   @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
2408 **/
2409 #define MSR_HASWELL_E_C0_PMON_BOX_STATUS  0x00000E07
2410
2411 /**
2412   Package. Uncore C-box 0 perfmon counter 0.
2413
2414   @param  ECX  MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)
2415   @param  EAX  Lower 32-bits of MSR value.
2416   @param  EDX  Upper 32-bits of MSR value.
2417
2418   <b>Example usage</b>
2419   @code
2420   UINT64  Msr;
2421
2422   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);
2423   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);
2424   @endcode
2425   @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
2426 **/
2427 #define MSR_HASWELL_E_C0_PMON_CTR0  0x00000E08
2428
2429 /**
2430   Package. Uncore C-box 0 perfmon counter 1.
2431
2432   @param  ECX  MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)
2433   @param  EAX  Lower 32-bits of MSR value.
2434   @param  EDX  Upper 32-bits of MSR value.
2435
2436   <b>Example usage</b>
2437   @code
2438   UINT64  Msr;
2439
2440   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);
2441   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);
2442   @endcode
2443   @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
2444 **/
2445 #define MSR_HASWELL_E_C0_PMON_CTR1  0x00000E09
2446
2447 /**
2448   Package. Uncore C-box 0 perfmon counter 2.
2449
2450   @param  ECX  MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)
2451   @param  EAX  Lower 32-bits of MSR value.
2452   @param  EDX  Upper 32-bits of MSR value.
2453
2454   <b>Example usage</b>
2455   @code
2456   UINT64  Msr;
2457
2458   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);
2459   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);
2460   @endcode
2461   @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
2462 **/
2463 #define MSR_HASWELL_E_C0_PMON_CTR2  0x00000E0A
2464
2465 /**
2466   Package. Uncore C-box 0 perfmon counter 3.
2467
2468   @param  ECX  MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)
2469   @param  EAX  Lower 32-bits of MSR value.
2470   @param  EDX  Upper 32-bits of MSR value.
2471
2472   <b>Example usage</b>
2473   @code
2474   UINT64  Msr;
2475
2476   Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);
2477   AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);
2478   @endcode
2479   @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
2480 **/
2481 #define MSR_HASWELL_E_C0_PMON_CTR3  0x00000E0B
2482
2483 /**
2484   Package. Uncore C-box 1 perfmon for box-wide control.
2485
2486   @param  ECX  MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)
2487   @param  EAX  Lower 32-bits of MSR value.
2488   @param  EDX  Upper 32-bits of MSR value.
2489
2490   <b>Example usage</b>
2491   @code
2492   UINT64  Msr;
2493
2494   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);
2495   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);
2496   @endcode
2497   @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
2498 **/
2499 #define MSR_HASWELL_E_C1_PMON_BOX_CTL  0x00000E10
2500
2501 /**
2502   Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
2503
2504   @param  ECX  MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)
2505   @param  EAX  Lower 32-bits of MSR value.
2506   @param  EDX  Upper 32-bits of MSR value.
2507
2508   <b>Example usage</b>
2509   @code
2510   UINT64  Msr;
2511
2512   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);
2513   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);
2514   @endcode
2515   @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
2516 **/
2517 #define MSR_HASWELL_E_C1_PMON_EVNTSEL0  0x00000E11
2518
2519 /**
2520   Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
2521
2522   @param  ECX  MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)
2523   @param  EAX  Lower 32-bits of MSR value.
2524   @param  EDX  Upper 32-bits of MSR value.
2525
2526   <b>Example usage</b>
2527   @code
2528   UINT64  Msr;
2529
2530   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);
2531   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);
2532   @endcode
2533   @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
2534 **/
2535 #define MSR_HASWELL_E_C1_PMON_EVNTSEL1  0x00000E12
2536
2537 /**
2538   Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
2539
2540   @param  ECX  MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)
2541   @param  EAX  Lower 32-bits of MSR value.
2542   @param  EDX  Upper 32-bits of MSR value.
2543
2544   <b>Example usage</b>
2545   @code
2546   UINT64  Msr;
2547
2548   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);
2549   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);
2550   @endcode
2551   @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
2552 **/
2553 #define MSR_HASWELL_E_C1_PMON_EVNTSEL2  0x00000E13
2554
2555 /**
2556   Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
2557
2558   @param  ECX  MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)
2559   @param  EAX  Lower 32-bits of MSR value.
2560   @param  EDX  Upper 32-bits of MSR value.
2561
2562   <b>Example usage</b>
2563   @code
2564   UINT64  Msr;
2565
2566   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);
2567   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);
2568   @endcode
2569   @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
2570 **/
2571 #define MSR_HASWELL_E_C1_PMON_EVNTSEL3  0x00000E14
2572
2573 /**
2574   Package. Uncore C-box 1 perfmon box wide filter 0.
2575
2576   @param  ECX  MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)
2577   @param  EAX  Lower 32-bits of MSR value.
2578   @param  EDX  Upper 32-bits of MSR value.
2579
2580   <b>Example usage</b>
2581   @code
2582   UINT64  Msr;
2583
2584   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);
2585   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);
2586   @endcode
2587   @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.
2588 **/
2589 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER0  0x00000E15
2590
2591 /**
2592   Package. Uncore C-box 1 perfmon box wide filter1.
2593
2594   @param  ECX  MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)
2595   @param  EAX  Lower 32-bits of MSR value.
2596   @param  EDX  Upper 32-bits of MSR value.
2597
2598   <b>Example usage</b>
2599   @code
2600   UINT64  Msr;
2601
2602   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);
2603   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);
2604   @endcode
2605   @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
2606 **/
2607 #define MSR_HASWELL_E_C1_PMON_BOX_FILTER1  0x00000E16
2608
2609 /**
2610   Package. Uncore C-box 1 perfmon box wide status.
2611
2612   @param  ECX  MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)
2613   @param  EAX  Lower 32-bits of MSR value.
2614   @param  EDX  Upper 32-bits of MSR value.
2615
2616   <b>Example usage</b>
2617   @code
2618   UINT64  Msr;
2619
2620   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);
2621   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);
2622   @endcode
2623   @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
2624 **/
2625 #define MSR_HASWELL_E_C1_PMON_BOX_STATUS  0x00000E17
2626
2627 /**
2628   Package. Uncore C-box 1 perfmon counter 0.
2629
2630   @param  ECX  MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)
2631   @param  EAX  Lower 32-bits of MSR value.
2632   @param  EDX  Upper 32-bits of MSR value.
2633
2634   <b>Example usage</b>
2635   @code
2636   UINT64  Msr;
2637
2638   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);
2639   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);
2640   @endcode
2641   @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
2642 **/
2643 #define MSR_HASWELL_E_C1_PMON_CTR0  0x00000E18
2644
2645 /**
2646   Package. Uncore C-box 1 perfmon counter 1.
2647
2648   @param  ECX  MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)
2649   @param  EAX  Lower 32-bits of MSR value.
2650   @param  EDX  Upper 32-bits of MSR value.
2651
2652   <b>Example usage</b>
2653   @code
2654   UINT64  Msr;
2655
2656   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);
2657   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);
2658   @endcode
2659   @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
2660 **/
2661 #define MSR_HASWELL_E_C1_PMON_CTR1  0x00000E19
2662
2663 /**
2664   Package. Uncore C-box 1 perfmon counter 2.
2665
2666   @param  ECX  MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)
2667   @param  EAX  Lower 32-bits of MSR value.
2668   @param  EDX  Upper 32-bits of MSR value.
2669
2670   <b>Example usage</b>
2671   @code
2672   UINT64  Msr;
2673
2674   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);
2675   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);
2676   @endcode
2677   @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
2678 **/
2679 #define MSR_HASWELL_E_C1_PMON_CTR2  0x00000E1A
2680
2681 /**
2682   Package. Uncore C-box 1 perfmon counter 3.
2683
2684   @param  ECX  MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)
2685   @param  EAX  Lower 32-bits of MSR value.
2686   @param  EDX  Upper 32-bits of MSR value.
2687
2688   <b>Example usage</b>
2689   @code
2690   UINT64  Msr;
2691
2692   Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);
2693   AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);
2694   @endcode
2695   @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
2696 **/
2697 #define MSR_HASWELL_E_C1_PMON_CTR3  0x00000E1B
2698
2699 /**
2700   Package. Uncore C-box 2 perfmon for box-wide control.
2701
2702   @param  ECX  MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)
2703   @param  EAX  Lower 32-bits of MSR value.
2704   @param  EDX  Upper 32-bits of MSR value.
2705
2706   <b>Example usage</b>
2707   @code
2708   UINT64  Msr;
2709
2710   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);
2711   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);
2712   @endcode
2713   @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
2714 **/
2715 #define MSR_HASWELL_E_C2_PMON_BOX_CTL  0x00000E20
2716
2717 /**
2718   Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
2719
2720   @param  ECX  MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)
2721   @param  EAX  Lower 32-bits of MSR value.
2722   @param  EDX  Upper 32-bits of MSR value.
2723
2724   <b>Example usage</b>
2725   @code
2726   UINT64  Msr;
2727
2728   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);
2729   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);
2730   @endcode
2731   @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
2732 **/
2733 #define MSR_HASWELL_E_C2_PMON_EVNTSEL0  0x00000E21
2734
2735 /**
2736   Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
2737
2738   @param  ECX  MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)
2739   @param  EAX  Lower 32-bits of MSR value.
2740   @param  EDX  Upper 32-bits of MSR value.
2741
2742   <b>Example usage</b>
2743   @code
2744   UINT64  Msr;
2745
2746   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);
2747   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);
2748   @endcode
2749   @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
2750 **/
2751 #define MSR_HASWELL_E_C2_PMON_EVNTSEL1  0x00000E22
2752
2753 /**
2754   Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
2755
2756   @param  ECX  MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)
2757   @param  EAX  Lower 32-bits of MSR value.
2758   @param  EDX  Upper 32-bits of MSR value.
2759
2760   <b>Example usage</b>
2761   @code
2762   UINT64  Msr;
2763
2764   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);
2765   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);
2766   @endcode
2767   @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
2768 **/
2769 #define MSR_HASWELL_E_C2_PMON_EVNTSEL2  0x00000E23
2770
2771 /**
2772   Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
2773
2774   @param  ECX  MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)
2775   @param  EAX  Lower 32-bits of MSR value.
2776   @param  EDX  Upper 32-bits of MSR value.
2777
2778   <b>Example usage</b>
2779   @code
2780   UINT64  Msr;
2781
2782   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);
2783   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);
2784   @endcode
2785   @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
2786 **/
2787 #define MSR_HASWELL_E_C2_PMON_EVNTSEL3  0x00000E24
2788
2789 /**
2790   Package. Uncore C-box 2 perfmon box wide filter 0.
2791
2792   @param  ECX  MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)
2793   @param  EAX  Lower 32-bits of MSR value.
2794   @param  EDX  Upper 32-bits of MSR value.
2795
2796   <b>Example usage</b>
2797   @code
2798   UINT64  Msr;
2799
2800   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);
2801   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);
2802   @endcode
2803   @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.
2804 **/
2805 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER0  0x00000E25
2806
2807 /**
2808   Package. Uncore C-box 2 perfmon box wide filter1.
2809
2810   @param  ECX  MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)
2811   @param  EAX  Lower 32-bits of MSR value.
2812   @param  EDX  Upper 32-bits of MSR value.
2813
2814   <b>Example usage</b>
2815   @code
2816   UINT64  Msr;
2817
2818   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);
2819   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);
2820   @endcode
2821   @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
2822 **/
2823 #define MSR_HASWELL_E_C2_PMON_BOX_FILTER1  0x00000E26
2824
2825 /**
2826   Package. Uncore C-box 2 perfmon box wide status.
2827
2828   @param  ECX  MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)
2829   @param  EAX  Lower 32-bits of MSR value.
2830   @param  EDX  Upper 32-bits of MSR value.
2831
2832   <b>Example usage</b>
2833   @code
2834   UINT64  Msr;
2835
2836   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);
2837   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);
2838   @endcode
2839   @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
2840 **/
2841 #define MSR_HASWELL_E_C2_PMON_BOX_STATUS  0x00000E27
2842
2843 /**
2844   Package. Uncore C-box 2 perfmon counter 0.
2845
2846   @param  ECX  MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)
2847   @param  EAX  Lower 32-bits of MSR value.
2848   @param  EDX  Upper 32-bits of MSR value.
2849
2850   <b>Example usage</b>
2851   @code
2852   UINT64  Msr;
2853
2854   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);
2855   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);
2856   @endcode
2857   @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
2858 **/
2859 #define MSR_HASWELL_E_C2_PMON_CTR0  0x00000E28
2860
2861 /**
2862   Package. Uncore C-box 2 perfmon counter 1.
2863
2864   @param  ECX  MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)
2865   @param  EAX  Lower 32-bits of MSR value.
2866   @param  EDX  Upper 32-bits of MSR value.
2867
2868   <b>Example usage</b>
2869   @code
2870   UINT64  Msr;
2871
2872   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);
2873   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);
2874   @endcode
2875   @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
2876 **/
2877 #define MSR_HASWELL_E_C2_PMON_CTR1  0x00000E29
2878
2879 /**
2880   Package. Uncore C-box 2 perfmon counter 2.
2881
2882   @param  ECX  MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)
2883   @param  EAX  Lower 32-bits of MSR value.
2884   @param  EDX  Upper 32-bits of MSR value.
2885
2886   <b>Example usage</b>
2887   @code
2888   UINT64  Msr;
2889
2890   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);
2891   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);
2892   @endcode
2893   @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
2894 **/
2895 #define MSR_HASWELL_E_C2_PMON_CTR2  0x00000E2A
2896
2897 /**
2898   Package. Uncore C-box 2 perfmon counter 3.
2899
2900   @param  ECX  MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)
2901   @param  EAX  Lower 32-bits of MSR value.
2902   @param  EDX  Upper 32-bits of MSR value.
2903
2904   <b>Example usage</b>
2905   @code
2906   UINT64  Msr;
2907
2908   Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);
2909   AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);
2910   @endcode
2911   @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
2912 **/
2913 #define MSR_HASWELL_E_C2_PMON_CTR3  0x00000E2B
2914
2915 /**
2916   Package. Uncore C-box 3 perfmon for box-wide control.
2917
2918   @param  ECX  MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)
2919   @param  EAX  Lower 32-bits of MSR value.
2920   @param  EDX  Upper 32-bits of MSR value.
2921
2922   <b>Example usage</b>
2923   @code
2924   UINT64  Msr;
2925
2926   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);
2927   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);
2928   @endcode
2929   @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
2930 **/
2931 #define MSR_HASWELL_E_C3_PMON_BOX_CTL  0x00000E30
2932
2933 /**
2934   Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
2935
2936   @param  ECX  MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)
2937   @param  EAX  Lower 32-bits of MSR value.
2938   @param  EDX  Upper 32-bits of MSR value.
2939
2940   <b>Example usage</b>
2941   @code
2942   UINT64  Msr;
2943
2944   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);
2945   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);
2946   @endcode
2947   @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
2948 **/
2949 #define MSR_HASWELL_E_C3_PMON_EVNTSEL0  0x00000E31
2950
2951 /**
2952   Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
2953
2954   @param  ECX  MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)
2955   @param  EAX  Lower 32-bits of MSR value.
2956   @param  EDX  Upper 32-bits of MSR value.
2957
2958   <b>Example usage</b>
2959   @code
2960   UINT64  Msr;
2961
2962   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);
2963   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);
2964   @endcode
2965   @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
2966 **/
2967 #define MSR_HASWELL_E_C3_PMON_EVNTSEL1  0x00000E32
2968
2969 /**
2970   Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
2971
2972   @param  ECX  MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)
2973   @param  EAX  Lower 32-bits of MSR value.
2974   @param  EDX  Upper 32-bits of MSR value.
2975
2976   <b>Example usage</b>
2977   @code
2978   UINT64  Msr;
2979
2980   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);
2981   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);
2982   @endcode
2983   @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
2984 **/
2985 #define MSR_HASWELL_E_C3_PMON_EVNTSEL2  0x00000E33
2986
2987 /**
2988   Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
2989
2990   @param  ECX  MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)
2991   @param  EAX  Lower 32-bits of MSR value.
2992   @param  EDX  Upper 32-bits of MSR value.
2993
2994   <b>Example usage</b>
2995   @code
2996   UINT64  Msr;
2997
2998   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);
2999   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);
3000   @endcode
3001   @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
3002 **/
3003 #define MSR_HASWELL_E_C3_PMON_EVNTSEL3  0x00000E34
3004
3005 /**
3006   Package. Uncore C-box 3 perfmon box wide filter 0.
3007
3008   @param  ECX  MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)
3009   @param  EAX  Lower 32-bits of MSR value.
3010   @param  EDX  Upper 32-bits of MSR value.
3011
3012   <b>Example usage</b>
3013   @code
3014   UINT64  Msr;
3015
3016   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);
3017   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);
3018   @endcode
3019   @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.
3020 **/
3021 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER0  0x00000E35
3022
3023 /**
3024   Package. Uncore C-box 3 perfmon box wide filter1.
3025
3026   @param  ECX  MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)
3027   @param  EAX  Lower 32-bits of MSR value.
3028   @param  EDX  Upper 32-bits of MSR value.
3029
3030   <b>Example usage</b>
3031   @code
3032   UINT64  Msr;
3033
3034   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);
3035   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);
3036   @endcode
3037   @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
3038 **/
3039 #define MSR_HASWELL_E_C3_PMON_BOX_FILTER1  0x00000E36
3040
3041 /**
3042   Package. Uncore C-box 3 perfmon box wide status.
3043
3044   @param  ECX  MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)
3045   @param  EAX  Lower 32-bits of MSR value.
3046   @param  EDX  Upper 32-bits of MSR value.
3047
3048   <b>Example usage</b>
3049   @code
3050   UINT64  Msr;
3051
3052   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);
3053   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);
3054   @endcode
3055   @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
3056 **/
3057 #define MSR_HASWELL_E_C3_PMON_BOX_STATUS  0x00000E37
3058
3059 /**
3060   Package. Uncore C-box 3 perfmon counter 0.
3061
3062   @param  ECX  MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)
3063   @param  EAX  Lower 32-bits of MSR value.
3064   @param  EDX  Upper 32-bits of MSR value.
3065
3066   <b>Example usage</b>
3067   @code
3068   UINT64  Msr;
3069
3070   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);
3071   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);
3072   @endcode
3073   @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
3074 **/
3075 #define MSR_HASWELL_E_C3_PMON_CTR0  0x00000E38
3076
3077 /**
3078   Package. Uncore C-box 3 perfmon counter 1.
3079
3080   @param  ECX  MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)
3081   @param  EAX  Lower 32-bits of MSR value.
3082   @param  EDX  Upper 32-bits of MSR value.
3083
3084   <b>Example usage</b>
3085   @code
3086   UINT64  Msr;
3087
3088   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);
3089   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);
3090   @endcode
3091   @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
3092 **/
3093 #define MSR_HASWELL_E_C3_PMON_CTR1  0x00000E39
3094
3095 /**
3096   Package. Uncore C-box 3 perfmon counter 2.
3097
3098   @param  ECX  MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)
3099   @param  EAX  Lower 32-bits of MSR value.
3100   @param  EDX  Upper 32-bits of MSR value.
3101
3102   <b>Example usage</b>
3103   @code
3104   UINT64  Msr;
3105
3106   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);
3107   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);
3108   @endcode
3109   @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
3110 **/
3111 #define MSR_HASWELL_E_C3_PMON_CTR2  0x00000E3A
3112
3113 /**
3114   Package. Uncore C-box 3 perfmon counter 3.
3115
3116   @param  ECX  MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)
3117   @param  EAX  Lower 32-bits of MSR value.
3118   @param  EDX  Upper 32-bits of MSR value.
3119
3120   <b>Example usage</b>
3121   @code
3122   UINT64  Msr;
3123
3124   Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);
3125   AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);
3126   @endcode
3127   @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
3128 **/
3129 #define MSR_HASWELL_E_C3_PMON_CTR3  0x00000E3B
3130
3131 /**
3132   Package. Uncore C-box 4 perfmon for box-wide control.
3133
3134   @param  ECX  MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)
3135   @param  EAX  Lower 32-bits of MSR value.
3136   @param  EDX  Upper 32-bits of MSR value.
3137
3138   <b>Example usage</b>
3139   @code
3140   UINT64  Msr;
3141
3142   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);
3143   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);
3144   @endcode
3145   @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
3146 **/
3147 #define MSR_HASWELL_E_C4_PMON_BOX_CTL  0x00000E40
3148
3149 /**
3150   Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
3151
3152   @param  ECX  MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)
3153   @param  EAX  Lower 32-bits of MSR value.
3154   @param  EDX  Upper 32-bits of MSR value.
3155
3156   <b>Example usage</b>
3157   @code
3158   UINT64  Msr;
3159
3160   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);
3161   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);
3162   @endcode
3163   @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
3164 **/
3165 #define MSR_HASWELL_E_C4_PMON_EVNTSEL0  0x00000E41
3166
3167 /**
3168   Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
3169
3170   @param  ECX  MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)
3171   @param  EAX  Lower 32-bits of MSR value.
3172   @param  EDX  Upper 32-bits of MSR value.
3173
3174   <b>Example usage</b>
3175   @code
3176   UINT64  Msr;
3177
3178   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);
3179   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);
3180   @endcode
3181   @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
3182 **/
3183 #define MSR_HASWELL_E_C4_PMON_EVNTSEL1  0x00000E42
3184
3185 /**
3186   Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
3187
3188   @param  ECX  MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)
3189   @param  EAX  Lower 32-bits of MSR value.
3190   @param  EDX  Upper 32-bits of MSR value.
3191
3192   <b>Example usage</b>
3193   @code
3194   UINT64  Msr;
3195
3196   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);
3197   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);
3198   @endcode
3199   @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
3200 **/
3201 #define MSR_HASWELL_E_C4_PMON_EVNTSEL2  0x00000E43
3202
3203 /**
3204   Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
3205
3206   @param  ECX  MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)
3207   @param  EAX  Lower 32-bits of MSR value.
3208   @param  EDX  Upper 32-bits of MSR value.
3209
3210   <b>Example usage</b>
3211   @code
3212   UINT64  Msr;
3213
3214   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);
3215   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);
3216   @endcode
3217   @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
3218 **/
3219 #define MSR_HASWELL_E_C4_PMON_EVNTSEL3  0x00000E44
3220
3221 /**
3222   Package. Uncore C-box 4 perfmon box wide filter 0.
3223
3224   @param  ECX  MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)
3225   @param  EAX  Lower 32-bits of MSR value.
3226   @param  EDX  Upper 32-bits of MSR value.
3227
3228   <b>Example usage</b>
3229   @code
3230   UINT64  Msr;
3231
3232   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);
3233   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);
3234   @endcode
3235   @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.
3236 **/
3237 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER0  0x00000E45
3238
3239 /**
3240   Package. Uncore C-box 4 perfmon box wide filter1.
3241
3242   @param  ECX  MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)
3243   @param  EAX  Lower 32-bits of MSR value.
3244   @param  EDX  Upper 32-bits of MSR value.
3245
3246   <b>Example usage</b>
3247   @code
3248   UINT64  Msr;
3249
3250   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);
3251   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);
3252   @endcode
3253   @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
3254 **/
3255 #define MSR_HASWELL_E_C4_PMON_BOX_FILTER1  0x00000E46
3256
3257 /**
3258   Package. Uncore C-box 4 perfmon box wide status.
3259
3260   @param  ECX  MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)
3261   @param  EAX  Lower 32-bits of MSR value.
3262   @param  EDX  Upper 32-bits of MSR value.
3263
3264   <b>Example usage</b>
3265   @code
3266   UINT64  Msr;
3267
3268   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);
3269   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);
3270   @endcode
3271   @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
3272 **/
3273 #define MSR_HASWELL_E_C4_PMON_BOX_STATUS  0x00000E47
3274
3275 /**
3276   Package. Uncore C-box 4 perfmon counter 0.
3277
3278   @param  ECX  MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)
3279   @param  EAX  Lower 32-bits of MSR value.
3280   @param  EDX  Upper 32-bits of MSR value.
3281
3282   <b>Example usage</b>
3283   @code
3284   UINT64  Msr;
3285
3286   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);
3287   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);
3288   @endcode
3289   @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
3290 **/
3291 #define MSR_HASWELL_E_C4_PMON_CTR0  0x00000E48
3292
3293 /**
3294   Package. Uncore C-box 4 perfmon counter 1.
3295
3296   @param  ECX  MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)
3297   @param  EAX  Lower 32-bits of MSR value.
3298   @param  EDX  Upper 32-bits of MSR value.
3299
3300   <b>Example usage</b>
3301   @code
3302   UINT64  Msr;
3303
3304   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);
3305   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);
3306   @endcode
3307   @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
3308 **/
3309 #define MSR_HASWELL_E_C4_PMON_CTR1  0x00000E49
3310
3311 /**
3312   Package. Uncore C-box 4 perfmon counter 2.
3313
3314   @param  ECX  MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)
3315   @param  EAX  Lower 32-bits of MSR value.
3316   @param  EDX  Upper 32-bits of MSR value.
3317
3318   <b>Example usage</b>
3319   @code
3320   UINT64  Msr;
3321
3322   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);
3323   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);
3324   @endcode
3325   @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
3326 **/
3327 #define MSR_HASWELL_E_C4_PMON_CTR2  0x00000E4A
3328
3329 /**
3330   Package. Uncore C-box 4 perfmon counter 3.
3331
3332   @param  ECX  MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)
3333   @param  EAX  Lower 32-bits of MSR value.
3334   @param  EDX  Upper 32-bits of MSR value.
3335
3336   <b>Example usage</b>
3337   @code
3338   UINT64  Msr;
3339
3340   Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);
3341   AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);
3342   @endcode
3343   @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
3344 **/
3345 #define MSR_HASWELL_E_C4_PMON_CTR3  0x00000E4B
3346
3347 /**
3348   Package. Uncore C-box 5 perfmon for box-wide control.
3349
3350   @param  ECX  MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)
3351   @param  EAX  Lower 32-bits of MSR value.
3352   @param  EDX  Upper 32-bits of MSR value.
3353
3354   <b>Example usage</b>
3355   @code
3356   UINT64  Msr;
3357
3358   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);
3359   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);
3360   @endcode
3361   @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
3362 **/
3363 #define MSR_HASWELL_E_C5_PMON_BOX_CTL  0x00000E50
3364
3365 /**
3366   Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
3367
3368   @param  ECX  MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)
3369   @param  EAX  Lower 32-bits of MSR value.
3370   @param  EDX  Upper 32-bits of MSR value.
3371
3372   <b>Example usage</b>
3373   @code
3374   UINT64  Msr;
3375
3376   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);
3377   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);
3378   @endcode
3379   @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
3380 **/
3381 #define MSR_HASWELL_E_C5_PMON_EVNTSEL0  0x00000E51
3382
3383 /**
3384   Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
3385
3386   @param  ECX  MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)
3387   @param  EAX  Lower 32-bits of MSR value.
3388   @param  EDX  Upper 32-bits of MSR value.
3389
3390   <b>Example usage</b>
3391   @code
3392   UINT64  Msr;
3393
3394   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);
3395   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);
3396   @endcode
3397   @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
3398 **/
3399 #define MSR_HASWELL_E_C5_PMON_EVNTSEL1  0x00000E52
3400
3401 /**
3402   Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
3403
3404   @param  ECX  MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)
3405   @param  EAX  Lower 32-bits of MSR value.
3406   @param  EDX  Upper 32-bits of MSR value.
3407
3408   <b>Example usage</b>
3409   @code
3410   UINT64  Msr;
3411
3412   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);
3413   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);
3414   @endcode
3415   @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
3416 **/
3417 #define MSR_HASWELL_E_C5_PMON_EVNTSEL2  0x00000E53
3418
3419 /**
3420   Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
3421
3422   @param  ECX  MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)
3423   @param  EAX  Lower 32-bits of MSR value.
3424   @param  EDX  Upper 32-bits of MSR value.
3425
3426   <b>Example usage</b>
3427   @code
3428   UINT64  Msr;
3429
3430   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);
3431   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);
3432   @endcode
3433   @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
3434 **/
3435 #define MSR_HASWELL_E_C5_PMON_EVNTSEL3  0x00000E54
3436
3437 /**
3438   Package. Uncore C-box 5 perfmon box wide filter 0.
3439
3440   @param  ECX  MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)
3441   @param  EAX  Lower 32-bits of MSR value.
3442   @param  EDX  Upper 32-bits of MSR value.
3443
3444   <b>Example usage</b>
3445   @code
3446   UINT64  Msr;
3447
3448   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);
3449   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);
3450   @endcode
3451   @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.
3452 **/
3453 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER0  0x00000E55
3454
3455 /**
3456   Package. Uncore C-box 5 perfmon box wide filter1.
3457
3458   @param  ECX  MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)
3459   @param  EAX  Lower 32-bits of MSR value.
3460   @param  EDX  Upper 32-bits of MSR value.
3461
3462   <b>Example usage</b>
3463   @code
3464   UINT64  Msr;
3465
3466   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);
3467   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);
3468   @endcode
3469   @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
3470 **/
3471 #define MSR_HASWELL_E_C5_PMON_BOX_FILTER1  0x00000E56
3472
3473 /**
3474   Package. Uncore C-box 5 perfmon box wide status.
3475
3476   @param  ECX  MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)
3477   @param  EAX  Lower 32-bits of MSR value.
3478   @param  EDX  Upper 32-bits of MSR value.
3479
3480   <b>Example usage</b>
3481   @code
3482   UINT64  Msr;
3483
3484   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);
3485   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);
3486   @endcode
3487   @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
3488 **/
3489 #define MSR_HASWELL_E_C5_PMON_BOX_STATUS  0x00000E57
3490
3491 /**
3492   Package. Uncore C-box 5 perfmon counter 0.
3493
3494   @param  ECX  MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)
3495   @param  EAX  Lower 32-bits of MSR value.
3496   @param  EDX  Upper 32-bits of MSR value.
3497
3498   <b>Example usage</b>
3499   @code
3500   UINT64  Msr;
3501
3502   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);
3503   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);
3504   @endcode
3505   @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
3506 **/
3507 #define MSR_HASWELL_E_C5_PMON_CTR0  0x00000E58
3508
3509 /**
3510   Package. Uncore C-box 5 perfmon counter 1.
3511
3512   @param  ECX  MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)
3513   @param  EAX  Lower 32-bits of MSR value.
3514   @param  EDX  Upper 32-bits of MSR value.
3515
3516   <b>Example usage</b>
3517   @code
3518   UINT64  Msr;
3519
3520   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);
3521   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);
3522   @endcode
3523   @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
3524 **/
3525 #define MSR_HASWELL_E_C5_PMON_CTR1  0x00000E59
3526
3527 /**
3528   Package. Uncore C-box 5 perfmon counter 2.
3529
3530   @param  ECX  MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)
3531   @param  EAX  Lower 32-bits of MSR value.
3532   @param  EDX  Upper 32-bits of MSR value.
3533
3534   <b>Example usage</b>
3535   @code
3536   UINT64  Msr;
3537
3538   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);
3539   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);
3540   @endcode
3541   @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
3542 **/
3543 #define MSR_HASWELL_E_C5_PMON_CTR2  0x00000E5A
3544
3545 /**
3546   Package. Uncore C-box 5 perfmon counter 3.
3547
3548   @param  ECX  MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)
3549   @param  EAX  Lower 32-bits of MSR value.
3550   @param  EDX  Upper 32-bits of MSR value.
3551
3552   <b>Example usage</b>
3553   @code
3554   UINT64  Msr;
3555
3556   Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);
3557   AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);
3558   @endcode
3559   @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
3560 **/
3561 #define MSR_HASWELL_E_C5_PMON_CTR3  0x00000E5B
3562
3563 /**
3564   Package. Uncore C-box 6 perfmon for box-wide control.
3565
3566   @param  ECX  MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)
3567   @param  EAX  Lower 32-bits of MSR value.
3568   @param  EDX  Upper 32-bits of MSR value.
3569
3570   <b>Example usage</b>
3571   @code
3572   UINT64  Msr;
3573
3574   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);
3575   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);
3576   @endcode
3577   @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
3578 **/
3579 #define MSR_HASWELL_E_C6_PMON_BOX_CTL  0x00000E60
3580
3581 /**
3582   Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
3583
3584   @param  ECX  MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)
3585   @param  EAX  Lower 32-bits of MSR value.
3586   @param  EDX  Upper 32-bits of MSR value.
3587
3588   <b>Example usage</b>
3589   @code
3590   UINT64  Msr;
3591
3592   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);
3593   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);
3594   @endcode
3595   @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
3596 **/
3597 #define MSR_HASWELL_E_C6_PMON_EVNTSEL0  0x00000E61
3598
3599 /**
3600   Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
3601
3602   @param  ECX  MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)
3603   @param  EAX  Lower 32-bits of MSR value.
3604   @param  EDX  Upper 32-bits of MSR value.
3605
3606   <b>Example usage</b>
3607   @code
3608   UINT64  Msr;
3609
3610   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);
3611   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);
3612   @endcode
3613   @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
3614 **/
3615 #define MSR_HASWELL_E_C6_PMON_EVNTSEL1  0x00000E62
3616
3617 /**
3618   Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
3619
3620   @param  ECX  MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)
3621   @param  EAX  Lower 32-bits of MSR value.
3622   @param  EDX  Upper 32-bits of MSR value.
3623
3624   <b>Example usage</b>
3625   @code
3626   UINT64  Msr;
3627
3628   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);
3629   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);
3630   @endcode
3631   @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
3632 **/
3633 #define MSR_HASWELL_E_C6_PMON_EVNTSEL2  0x00000E63
3634
3635 /**
3636   Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
3637
3638   @param  ECX  MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)
3639   @param  EAX  Lower 32-bits of MSR value.
3640   @param  EDX  Upper 32-bits of MSR value.
3641
3642   <b>Example usage</b>
3643   @code
3644   UINT64  Msr;
3645
3646   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);
3647   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);
3648   @endcode
3649   @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
3650 **/
3651 #define MSR_HASWELL_E_C6_PMON_EVNTSEL3  0x00000E64
3652
3653 /**
3654   Package. Uncore C-box 6 perfmon box wide filter 0.
3655
3656   @param  ECX  MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)
3657   @param  EAX  Lower 32-bits of MSR value.
3658   @param  EDX  Upper 32-bits of MSR value.
3659
3660   <b>Example usage</b>
3661   @code
3662   UINT64  Msr;
3663
3664   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);
3665   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);
3666   @endcode
3667   @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.
3668 **/
3669 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER0  0x00000E65
3670
3671 /**
3672   Package. Uncore C-box 6 perfmon box wide filter1.
3673
3674   @param  ECX  MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)
3675   @param  EAX  Lower 32-bits of MSR value.
3676   @param  EDX  Upper 32-bits of MSR value.
3677
3678   <b>Example usage</b>
3679   @code
3680   UINT64  Msr;
3681
3682   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);
3683   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);
3684   @endcode
3685   @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
3686 **/
3687 #define MSR_HASWELL_E_C6_PMON_BOX_FILTER1  0x00000E66
3688
3689 /**
3690   Package. Uncore C-box 6 perfmon box wide status.
3691
3692   @param  ECX  MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)
3693   @param  EAX  Lower 32-bits of MSR value.
3694   @param  EDX  Upper 32-bits of MSR value.
3695
3696   <b>Example usage</b>
3697   @code
3698   UINT64  Msr;
3699
3700   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);
3701   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);
3702   @endcode
3703   @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
3704 **/
3705 #define MSR_HASWELL_E_C6_PMON_BOX_STATUS  0x00000E67
3706
3707 /**
3708   Package. Uncore C-box 6 perfmon counter 0.
3709
3710   @param  ECX  MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)
3711   @param  EAX  Lower 32-bits of MSR value.
3712   @param  EDX  Upper 32-bits of MSR value.
3713
3714   <b>Example usage</b>
3715   @code
3716   UINT64  Msr;
3717
3718   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);
3719   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);
3720   @endcode
3721   @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
3722 **/
3723 #define MSR_HASWELL_E_C6_PMON_CTR0  0x00000E68
3724
3725 /**
3726   Package. Uncore C-box 6 perfmon counter 1.
3727
3728   @param  ECX  MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)
3729   @param  EAX  Lower 32-bits of MSR value.
3730   @param  EDX  Upper 32-bits of MSR value.
3731
3732   <b>Example usage</b>
3733   @code
3734   UINT64  Msr;
3735
3736   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);
3737   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);
3738   @endcode
3739   @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
3740 **/
3741 #define MSR_HASWELL_E_C6_PMON_CTR1  0x00000E69
3742
3743 /**
3744   Package. Uncore C-box 6 perfmon counter 2.
3745
3746   @param  ECX  MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)
3747   @param  EAX  Lower 32-bits of MSR value.
3748   @param  EDX  Upper 32-bits of MSR value.
3749
3750   <b>Example usage</b>
3751   @code
3752   UINT64  Msr;
3753
3754   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);
3755   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);
3756   @endcode
3757   @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
3758 **/
3759 #define MSR_HASWELL_E_C6_PMON_CTR2  0x00000E6A
3760
3761 /**
3762   Package. Uncore C-box 6 perfmon counter 3.
3763
3764   @param  ECX  MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)
3765   @param  EAX  Lower 32-bits of MSR value.
3766   @param  EDX  Upper 32-bits of MSR value.
3767
3768   <b>Example usage</b>
3769   @code
3770   UINT64  Msr;
3771
3772   Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);
3773   AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);
3774   @endcode
3775   @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
3776 **/
3777 #define MSR_HASWELL_E_C6_PMON_CTR3  0x00000E6B
3778
3779 /**
3780   Package. Uncore C-box 7 perfmon for box-wide control.
3781
3782   @param  ECX  MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)
3783   @param  EAX  Lower 32-bits of MSR value.
3784   @param  EDX  Upper 32-bits of MSR value.
3785
3786   <b>Example usage</b>
3787   @code
3788   UINT64  Msr;
3789
3790   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);
3791   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);
3792   @endcode
3793   @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
3794 **/
3795 #define MSR_HASWELL_E_C7_PMON_BOX_CTL  0x00000E70
3796
3797 /**
3798   Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
3799
3800   @param  ECX  MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)
3801   @param  EAX  Lower 32-bits of MSR value.
3802   @param  EDX  Upper 32-bits of MSR value.
3803
3804   <b>Example usage</b>
3805   @code
3806   UINT64  Msr;
3807
3808   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);
3809   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);
3810   @endcode
3811   @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
3812 **/
3813 #define MSR_HASWELL_E_C7_PMON_EVNTSEL0  0x00000E71
3814
3815 /**
3816   Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
3817
3818   @param  ECX  MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)
3819   @param  EAX  Lower 32-bits of MSR value.
3820   @param  EDX  Upper 32-bits of MSR value.
3821
3822   <b>Example usage</b>
3823   @code
3824   UINT64  Msr;
3825
3826   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);
3827   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);
3828   @endcode
3829   @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
3830 **/
3831 #define MSR_HASWELL_E_C7_PMON_EVNTSEL1  0x00000E72
3832
3833 /**
3834   Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
3835
3836   @param  ECX  MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)
3837   @param  EAX  Lower 32-bits of MSR value.
3838   @param  EDX  Upper 32-bits of MSR value.
3839
3840   <b>Example usage</b>
3841   @code
3842   UINT64  Msr;
3843
3844   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);
3845   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);
3846   @endcode
3847   @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
3848 **/
3849 #define MSR_HASWELL_E_C7_PMON_EVNTSEL2  0x00000E73
3850
3851 /**
3852   Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
3853
3854   @param  ECX  MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)
3855   @param  EAX  Lower 32-bits of MSR value.
3856   @param  EDX  Upper 32-bits of MSR value.
3857
3858   <b>Example usage</b>
3859   @code
3860   UINT64  Msr;
3861
3862   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);
3863   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);
3864   @endcode
3865   @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
3866 **/
3867 #define MSR_HASWELL_E_C7_PMON_EVNTSEL3  0x00000E74
3868
3869 /**
3870   Package. Uncore C-box 7 perfmon box wide filter 0.
3871
3872   @param  ECX  MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)
3873   @param  EAX  Lower 32-bits of MSR value.
3874   @param  EDX  Upper 32-bits of MSR value.
3875
3876   <b>Example usage</b>
3877   @code
3878   UINT64  Msr;
3879
3880   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);
3881   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);
3882   @endcode
3883   @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.
3884 **/
3885 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER0  0x00000E75
3886
3887 /**
3888   Package. Uncore C-box 7 perfmon box wide filter1.
3889
3890   @param  ECX  MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)
3891   @param  EAX  Lower 32-bits of MSR value.
3892   @param  EDX  Upper 32-bits of MSR value.
3893
3894   <b>Example usage</b>
3895   @code
3896   UINT64  Msr;
3897
3898   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);
3899   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);
3900   @endcode
3901   @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
3902 **/
3903 #define MSR_HASWELL_E_C7_PMON_BOX_FILTER1  0x00000E76
3904
3905 /**
3906   Package. Uncore C-box 7 perfmon box wide status.
3907
3908   @param  ECX  MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)
3909   @param  EAX  Lower 32-bits of MSR value.
3910   @param  EDX  Upper 32-bits of MSR value.
3911
3912   <b>Example usage</b>
3913   @code
3914   UINT64  Msr;
3915
3916   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);
3917   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);
3918   @endcode
3919   @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
3920 **/
3921 #define MSR_HASWELL_E_C7_PMON_BOX_STATUS  0x00000E77
3922
3923 /**
3924   Package. Uncore C-box 7 perfmon counter 0.
3925
3926   @param  ECX  MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)
3927   @param  EAX  Lower 32-bits of MSR value.
3928   @param  EDX  Upper 32-bits of MSR value.
3929
3930   <b>Example usage</b>
3931   @code
3932   UINT64  Msr;
3933
3934   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);
3935   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);
3936   @endcode
3937   @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
3938 **/
3939 #define MSR_HASWELL_E_C7_PMON_CTR0  0x00000E78
3940
3941 /**
3942   Package. Uncore C-box 7 perfmon counter 1.
3943
3944   @param  ECX  MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)
3945   @param  EAX  Lower 32-bits of MSR value.
3946   @param  EDX  Upper 32-bits of MSR value.
3947
3948   <b>Example usage</b>
3949   @code
3950   UINT64  Msr;
3951
3952   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);
3953   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);
3954   @endcode
3955   @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
3956 **/
3957 #define MSR_HASWELL_E_C7_PMON_CTR1  0x00000E79
3958
3959 /**
3960   Package. Uncore C-box 7 perfmon counter 2.
3961
3962   @param  ECX  MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)
3963   @param  EAX  Lower 32-bits of MSR value.
3964   @param  EDX  Upper 32-bits of MSR value.
3965
3966   <b>Example usage</b>
3967   @code
3968   UINT64  Msr;
3969
3970   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);
3971   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);
3972   @endcode
3973   @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
3974 **/
3975 #define MSR_HASWELL_E_C7_PMON_CTR2  0x00000E7A
3976
3977 /**
3978   Package. Uncore C-box 7 perfmon counter 3.
3979
3980   @param  ECX  MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)
3981   @param  EAX  Lower 32-bits of MSR value.
3982   @param  EDX  Upper 32-bits of MSR value.
3983
3984   <b>Example usage</b>
3985   @code
3986   UINT64  Msr;
3987
3988   Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);
3989   AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);
3990   @endcode
3991   @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
3992 **/
3993 #define MSR_HASWELL_E_C7_PMON_CTR3  0x00000E7B
3994
3995 /**
3996   Package. Uncore C-box 8 perfmon local box wide control.
3997
3998   @param  ECX  MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)
3999   @param  EAX  Lower 32-bits of MSR value.
4000   @param  EDX  Upper 32-bits of MSR value.
4001
4002   <b>Example usage</b>
4003   @code
4004   UINT64  Msr;
4005
4006   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);
4007   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);
4008   @endcode
4009   @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
4010 **/
4011 #define MSR_HASWELL_E_C8_PMON_BOX_CTL  0x00000E80
4012
4013 /**
4014   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
4015
4016   @param  ECX  MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)
4017   @param  EAX  Lower 32-bits of MSR value.
4018   @param  EDX  Upper 32-bits of MSR value.
4019
4020   <b>Example usage</b>
4021   @code
4022   UINT64  Msr;
4023
4024   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);
4025   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);
4026   @endcode
4027   @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
4028 **/
4029 #define MSR_HASWELL_E_C8_PMON_EVNTSEL0  0x00000E81
4030
4031 /**
4032   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
4033
4034   @param  ECX  MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)
4035   @param  EAX  Lower 32-bits of MSR value.
4036   @param  EDX  Upper 32-bits of MSR value.
4037
4038   <b>Example usage</b>
4039   @code
4040   UINT64  Msr;
4041
4042   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);
4043   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);
4044   @endcode
4045   @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
4046 **/
4047 #define MSR_HASWELL_E_C8_PMON_EVNTSEL1  0x00000E82
4048
4049 /**
4050   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
4051
4052   @param  ECX  MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)
4053   @param  EAX  Lower 32-bits of MSR value.
4054   @param  EDX  Upper 32-bits of MSR value.
4055
4056   <b>Example usage</b>
4057   @code
4058   UINT64  Msr;
4059
4060   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);
4061   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);
4062   @endcode
4063   @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
4064 **/
4065 #define MSR_HASWELL_E_C8_PMON_EVNTSEL2  0x00000E83
4066
4067 /**
4068   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
4069
4070   @param  ECX  MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)
4071   @param  EAX  Lower 32-bits of MSR value.
4072   @param  EDX  Upper 32-bits of MSR value.
4073
4074   <b>Example usage</b>
4075   @code
4076   UINT64  Msr;
4077
4078   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);
4079   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);
4080   @endcode
4081   @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
4082 **/
4083 #define MSR_HASWELL_E_C8_PMON_EVNTSEL3  0x00000E84
4084
4085 /**
4086   Package. Uncore C-box 8 perfmon box wide filter0.
4087
4088   @param  ECX  MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)
4089   @param  EAX  Lower 32-bits of MSR value.
4090   @param  EDX  Upper 32-bits of MSR value.
4091
4092   <b>Example usage</b>
4093   @code
4094   UINT64  Msr;
4095
4096   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);
4097   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);
4098   @endcode
4099   @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.
4100 **/
4101 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER0  0x00000E85
4102
4103 /**
4104   Package. Uncore C-box 8 perfmon box wide filter1.
4105
4106   @param  ECX  MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)
4107   @param  EAX  Lower 32-bits of MSR value.
4108   @param  EDX  Upper 32-bits of MSR value.
4109
4110   <b>Example usage</b>
4111   @code
4112   UINT64  Msr;
4113
4114   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);
4115   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);
4116   @endcode
4117   @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
4118 **/
4119 #define MSR_HASWELL_E_C8_PMON_BOX_FILTER1  0x00000E86
4120
4121 /**
4122   Package. Uncore C-box 8 perfmon box wide status.
4123
4124   @param  ECX  MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)
4125   @param  EAX  Lower 32-bits of MSR value.
4126   @param  EDX  Upper 32-bits of MSR value.
4127
4128   <b>Example usage</b>
4129   @code
4130   UINT64  Msr;
4131
4132   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);
4133   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);
4134   @endcode
4135   @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
4136 **/
4137 #define MSR_HASWELL_E_C8_PMON_BOX_STATUS  0x00000E87
4138
4139 /**
4140   Package. Uncore C-box 8 perfmon counter 0.
4141
4142   @param  ECX  MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)
4143   @param  EAX  Lower 32-bits of MSR value.
4144   @param  EDX  Upper 32-bits of MSR value.
4145
4146   <b>Example usage</b>
4147   @code
4148   UINT64  Msr;
4149
4150   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);
4151   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);
4152   @endcode
4153   @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
4154 **/
4155 #define MSR_HASWELL_E_C8_PMON_CTR0  0x00000E88
4156
4157 /**
4158   Package. Uncore C-box 8 perfmon counter 1.
4159
4160   @param  ECX  MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)
4161   @param  EAX  Lower 32-bits of MSR value.
4162   @param  EDX  Upper 32-bits of MSR value.
4163
4164   <b>Example usage</b>
4165   @code
4166   UINT64  Msr;
4167
4168   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);
4169   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);
4170   @endcode
4171   @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
4172 **/
4173 #define MSR_HASWELL_E_C8_PMON_CTR1  0x00000E89
4174
4175 /**
4176   Package. Uncore C-box 8 perfmon counter 2.
4177
4178   @param  ECX  MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)
4179   @param  EAX  Lower 32-bits of MSR value.
4180   @param  EDX  Upper 32-bits of MSR value.
4181
4182   <b>Example usage</b>
4183   @code
4184   UINT64  Msr;
4185
4186   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);
4187   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);
4188   @endcode
4189   @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
4190 **/
4191 #define MSR_HASWELL_E_C8_PMON_CTR2  0x00000E8A
4192
4193 /**
4194   Package. Uncore C-box 8 perfmon counter 3.
4195
4196   @param  ECX  MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)
4197   @param  EAX  Lower 32-bits of MSR value.
4198   @param  EDX  Upper 32-bits of MSR value.
4199
4200   <b>Example usage</b>
4201   @code
4202   UINT64  Msr;
4203
4204   Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);
4205   AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);
4206   @endcode
4207   @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
4208 **/
4209 #define MSR_HASWELL_E_C8_PMON_CTR3  0x00000E8B
4210
4211 /**
4212   Package. Uncore C-box 9 perfmon local box wide control.
4213
4214   @param  ECX  MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)
4215   @param  EAX  Lower 32-bits of MSR value.
4216   @param  EDX  Upper 32-bits of MSR value.
4217
4218   <b>Example usage</b>
4219   @code
4220   UINT64  Msr;
4221
4222   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);
4223   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);
4224   @endcode
4225   @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
4226 **/
4227 #define MSR_HASWELL_E_C9_PMON_BOX_CTL  0x00000E90
4228
4229 /**
4230   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
4231
4232   @param  ECX  MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)
4233   @param  EAX  Lower 32-bits of MSR value.
4234   @param  EDX  Upper 32-bits of MSR value.
4235
4236   <b>Example usage</b>
4237   @code
4238   UINT64  Msr;
4239
4240   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);
4241   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);
4242   @endcode
4243   @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
4244 **/
4245 #define MSR_HASWELL_E_C9_PMON_EVNTSEL0  0x00000E91
4246
4247 /**
4248   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
4249
4250   @param  ECX  MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)
4251   @param  EAX  Lower 32-bits of MSR value.
4252   @param  EDX  Upper 32-bits of MSR value.
4253
4254   <b>Example usage</b>
4255   @code
4256   UINT64  Msr;
4257
4258   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);
4259   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);
4260   @endcode
4261   @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
4262 **/
4263 #define MSR_HASWELL_E_C9_PMON_EVNTSEL1  0x00000E92
4264
4265 /**
4266   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
4267
4268   @param  ECX  MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)
4269   @param  EAX  Lower 32-bits of MSR value.
4270   @param  EDX  Upper 32-bits of MSR value.
4271
4272   <b>Example usage</b>
4273   @code
4274   UINT64  Msr;
4275
4276   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);
4277   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);
4278   @endcode
4279   @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
4280 **/
4281 #define MSR_HASWELL_E_C9_PMON_EVNTSEL2  0x00000E93
4282
4283 /**
4284   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
4285
4286   @param  ECX  MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)
4287   @param  EAX  Lower 32-bits of MSR value.
4288   @param  EDX  Upper 32-bits of MSR value.
4289
4290   <b>Example usage</b>
4291   @code
4292   UINT64  Msr;
4293
4294   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);
4295   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);
4296   @endcode
4297   @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
4298 **/
4299 #define MSR_HASWELL_E_C9_PMON_EVNTSEL3  0x00000E94
4300
4301 /**
4302   Package. Uncore C-box 9 perfmon box wide filter0.
4303
4304   @param  ECX  MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)
4305   @param  EAX  Lower 32-bits of MSR value.
4306   @param  EDX  Upper 32-bits of MSR value.
4307
4308   <b>Example usage</b>
4309   @code
4310   UINT64  Msr;
4311
4312   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);
4313   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);
4314   @endcode
4315   @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.
4316 **/
4317 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER0  0x00000E95
4318
4319 /**
4320   Package. Uncore C-box 9 perfmon box wide filter1.
4321
4322   @param  ECX  MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)
4323   @param  EAX  Lower 32-bits of MSR value.
4324   @param  EDX  Upper 32-bits of MSR value.
4325
4326   <b>Example usage</b>
4327   @code
4328   UINT64  Msr;
4329
4330   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);
4331   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);
4332   @endcode
4333   @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
4334 **/
4335 #define MSR_HASWELL_E_C9_PMON_BOX_FILTER1  0x00000E96
4336
4337 /**
4338   Package. Uncore C-box 9 perfmon box wide status.
4339
4340   @param  ECX  MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)
4341   @param  EAX  Lower 32-bits of MSR value.
4342   @param  EDX  Upper 32-bits of MSR value.
4343
4344   <b>Example usage</b>
4345   @code
4346   UINT64  Msr;
4347
4348   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);
4349   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);
4350   @endcode
4351   @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
4352 **/
4353 #define MSR_HASWELL_E_C9_PMON_BOX_STATUS  0x00000E97
4354
4355 /**
4356   Package. Uncore C-box 9 perfmon counter 0.
4357
4358   @param  ECX  MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)
4359   @param  EAX  Lower 32-bits of MSR value.
4360   @param  EDX  Upper 32-bits of MSR value.
4361
4362   <b>Example usage</b>
4363   @code
4364   UINT64  Msr;
4365
4366   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);
4367   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);
4368   @endcode
4369   @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
4370 **/
4371 #define MSR_HASWELL_E_C9_PMON_CTR0  0x00000E98
4372
4373 /**
4374   Package. Uncore C-box 9 perfmon counter 1.
4375
4376   @param  ECX  MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)
4377   @param  EAX  Lower 32-bits of MSR value.
4378   @param  EDX  Upper 32-bits of MSR value.
4379
4380   <b>Example usage</b>
4381   @code
4382   UINT64  Msr;
4383
4384   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);
4385   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);
4386   @endcode
4387   @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
4388 **/
4389 #define MSR_HASWELL_E_C9_PMON_CTR1  0x00000E99
4390
4391 /**
4392   Package. Uncore C-box 9 perfmon counter 2.
4393
4394   @param  ECX  MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)
4395   @param  EAX  Lower 32-bits of MSR value.
4396   @param  EDX  Upper 32-bits of MSR value.
4397
4398   <b>Example usage</b>
4399   @code
4400   UINT64  Msr;
4401
4402   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);
4403   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);
4404   @endcode
4405   @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
4406 **/
4407 #define MSR_HASWELL_E_C9_PMON_CTR2  0x00000E9A
4408
4409 /**
4410   Package. Uncore C-box 9 perfmon counter 3.
4411
4412   @param  ECX  MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)
4413   @param  EAX  Lower 32-bits of MSR value.
4414   @param  EDX  Upper 32-bits of MSR value.
4415
4416   <b>Example usage</b>
4417   @code
4418   UINT64  Msr;
4419
4420   Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);
4421   AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);
4422   @endcode
4423   @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
4424 **/
4425 #define MSR_HASWELL_E_C9_PMON_CTR3  0x00000E9B
4426
4427 /**
4428   Package. Uncore C-box 10 perfmon local box wide control.
4429
4430   @param  ECX  MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)
4431   @param  EAX  Lower 32-bits of MSR value.
4432   @param  EDX  Upper 32-bits of MSR value.
4433
4434   <b>Example usage</b>
4435   @code
4436   UINT64  Msr;
4437
4438   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);
4439   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);
4440   @endcode
4441   @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
4442 **/
4443 #define MSR_HASWELL_E_C10_PMON_BOX_CTL  0x00000EA0
4444
4445 /**
4446   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
4447
4448   @param  ECX  MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)
4449   @param  EAX  Lower 32-bits of MSR value.
4450   @param  EDX  Upper 32-bits of MSR value.
4451
4452   <b>Example usage</b>
4453   @code
4454   UINT64  Msr;
4455
4456   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);
4457   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);
4458   @endcode
4459   @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
4460 **/
4461 #define MSR_HASWELL_E_C10_PMON_EVNTSEL0  0x00000EA1
4462
4463 /**
4464   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
4465
4466   @param  ECX  MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)
4467   @param  EAX  Lower 32-bits of MSR value.
4468   @param  EDX  Upper 32-bits of MSR value.
4469
4470   <b>Example usage</b>
4471   @code
4472   UINT64  Msr;
4473
4474   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);
4475   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);
4476   @endcode
4477   @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
4478 **/
4479 #define MSR_HASWELL_E_C10_PMON_EVNTSEL1  0x00000EA2
4480
4481 /**
4482   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
4483
4484   @param  ECX  MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)
4485   @param  EAX  Lower 32-bits of MSR value.
4486   @param  EDX  Upper 32-bits of MSR value.
4487
4488   <b>Example usage</b>
4489   @code
4490   UINT64  Msr;
4491
4492   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);
4493   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);
4494   @endcode
4495   @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
4496 **/
4497 #define MSR_HASWELL_E_C10_PMON_EVNTSEL2  0x00000EA3
4498
4499 /**
4500   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
4501
4502   @param  ECX  MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)
4503   @param  EAX  Lower 32-bits of MSR value.
4504   @param  EDX  Upper 32-bits of MSR value.
4505
4506   <b>Example usage</b>
4507   @code
4508   UINT64  Msr;
4509
4510   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);
4511   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);
4512   @endcode
4513   @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
4514 **/
4515 #define MSR_HASWELL_E_C10_PMON_EVNTSEL3  0x00000EA4
4516
4517 /**
4518   Package. Uncore C-box 10 perfmon box wide filter0.
4519
4520   @param  ECX  MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)
4521   @param  EAX  Lower 32-bits of MSR value.
4522   @param  EDX  Upper 32-bits of MSR value.
4523
4524   <b>Example usage</b>
4525   @code
4526   UINT64  Msr;
4527
4528   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);
4529   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);
4530   @endcode
4531   @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.
4532 **/
4533 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER0  0x00000EA5
4534
4535 /**
4536   Package. Uncore C-box 10 perfmon box wide filter1.
4537
4538   @param  ECX  MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)
4539   @param  EAX  Lower 32-bits of MSR value.
4540   @param  EDX  Upper 32-bits of MSR value.
4541
4542   <b>Example usage</b>
4543   @code
4544   UINT64  Msr;
4545
4546   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);
4547   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);
4548   @endcode
4549   @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
4550 **/
4551 #define MSR_HASWELL_E_C10_PMON_BOX_FILTER1  0x00000EA6
4552
4553 /**
4554   Package. Uncore C-box 10 perfmon box wide status.
4555
4556   @param  ECX  MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)
4557   @param  EAX  Lower 32-bits of MSR value.
4558   @param  EDX  Upper 32-bits of MSR value.
4559
4560   <b>Example usage</b>
4561   @code
4562   UINT64  Msr;
4563
4564   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);
4565   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);
4566   @endcode
4567   @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.
4568 **/
4569 #define MSR_HASWELL_E_C10_PMON_BOX_STATUS  0x00000EA7
4570
4571 /**
4572   Package. Uncore C-box 10 perfmon counter 0.
4573
4574   @param  ECX  MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)
4575   @param  EAX  Lower 32-bits of MSR value.
4576   @param  EDX  Upper 32-bits of MSR value.
4577
4578   <b>Example usage</b>
4579   @code
4580   UINT64  Msr;
4581
4582   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);
4583   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);
4584   @endcode
4585   @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
4586 **/
4587 #define MSR_HASWELL_E_C10_PMON_CTR0  0x00000EA8
4588
4589 /**
4590   Package. Uncore C-box 10 perfmon counter 1.
4591
4592   @param  ECX  MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)
4593   @param  EAX  Lower 32-bits of MSR value.
4594   @param  EDX  Upper 32-bits of MSR value.
4595
4596   <b>Example usage</b>
4597   @code
4598   UINT64  Msr;
4599
4600   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);
4601   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);
4602   @endcode
4603   @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
4604 **/
4605 #define MSR_HASWELL_E_C10_PMON_CTR1  0x00000EA9
4606
4607 /**
4608   Package. Uncore C-box 10 perfmon counter 2.
4609
4610   @param  ECX  MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)
4611   @param  EAX  Lower 32-bits of MSR value.
4612   @param  EDX  Upper 32-bits of MSR value.
4613
4614   <b>Example usage</b>
4615   @code
4616   UINT64  Msr;
4617
4618   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);
4619   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);
4620   @endcode
4621   @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
4622 **/
4623 #define MSR_HASWELL_E_C10_PMON_CTR2  0x00000EAA
4624
4625 /**
4626   Package. Uncore C-box 10 perfmon counter 3.
4627
4628   @param  ECX  MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)
4629   @param  EAX  Lower 32-bits of MSR value.
4630   @param  EDX  Upper 32-bits of MSR value.
4631
4632   <b>Example usage</b>
4633   @code
4634   UINT64  Msr;
4635
4636   Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);
4637   AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);
4638   @endcode
4639   @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
4640 **/
4641 #define MSR_HASWELL_E_C10_PMON_CTR3  0x00000EAB
4642
4643 /**
4644   Package. Uncore C-box 11 perfmon local box wide control.
4645
4646   @param  ECX  MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)
4647   @param  EAX  Lower 32-bits of MSR value.
4648   @param  EDX  Upper 32-bits of MSR value.
4649
4650   <b>Example usage</b>
4651   @code
4652   UINT64  Msr;
4653
4654   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);
4655   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);
4656   @endcode
4657   @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
4658 **/
4659 #define MSR_HASWELL_E_C11_PMON_BOX_CTL  0x00000EB0
4660
4661 /**
4662   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
4663
4664   @param  ECX  MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)
4665   @param  EAX  Lower 32-bits of MSR value.
4666   @param  EDX  Upper 32-bits of MSR value.
4667
4668   <b>Example usage</b>
4669   @code
4670   UINT64  Msr;
4671
4672   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);
4673   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);
4674   @endcode
4675   @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
4676 **/
4677 #define MSR_HASWELL_E_C11_PMON_EVNTSEL0  0x00000EB1
4678
4679 /**
4680   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
4681
4682   @param  ECX  MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)
4683   @param  EAX  Lower 32-bits of MSR value.
4684   @param  EDX  Upper 32-bits of MSR value.
4685
4686   <b>Example usage</b>
4687   @code
4688   UINT64  Msr;
4689
4690   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);
4691   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);
4692   @endcode
4693   @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
4694 **/
4695 #define MSR_HASWELL_E_C11_PMON_EVNTSEL1  0x00000EB2
4696
4697 /**
4698   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
4699
4700   @param  ECX  MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)
4701   @param  EAX  Lower 32-bits of MSR value.
4702   @param  EDX  Upper 32-bits of MSR value.
4703
4704   <b>Example usage</b>
4705   @code
4706   UINT64  Msr;
4707
4708   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);
4709   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);
4710   @endcode
4711   @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
4712 **/
4713 #define MSR_HASWELL_E_C11_PMON_EVNTSEL2  0x00000EB3
4714
4715 /**
4716   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
4717
4718   @param  ECX  MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)
4719   @param  EAX  Lower 32-bits of MSR value.
4720   @param  EDX  Upper 32-bits of MSR value.
4721
4722   <b>Example usage</b>
4723   @code
4724   UINT64  Msr;
4725
4726   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);
4727   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);
4728   @endcode
4729   @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
4730 **/
4731 #define MSR_HASWELL_E_C11_PMON_EVNTSEL3  0x00000EB4
4732
4733 /**
4734   Package. Uncore C-box 11 perfmon box wide filter0.
4735
4736   @param  ECX  MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)
4737   @param  EAX  Lower 32-bits of MSR value.
4738   @param  EDX  Upper 32-bits of MSR value.
4739
4740   <b>Example usage</b>
4741   @code
4742   UINT64  Msr;
4743
4744   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);
4745   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);
4746   @endcode
4747   @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.
4748 **/
4749 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER0  0x00000EB5
4750
4751 /**
4752   Package. Uncore C-box 11 perfmon box wide filter1.
4753
4754   @param  ECX  MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)
4755   @param  EAX  Lower 32-bits of MSR value.
4756   @param  EDX  Upper 32-bits of MSR value.
4757
4758   <b>Example usage</b>
4759   @code
4760   UINT64  Msr;
4761
4762   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);
4763   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);
4764   @endcode
4765   @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
4766 **/
4767 #define MSR_HASWELL_E_C11_PMON_BOX_FILTER1  0x00000EB6
4768
4769 /**
4770   Package. Uncore C-box 11 perfmon box wide status.
4771
4772   @param  ECX  MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)
4773   @param  EAX  Lower 32-bits of MSR value.
4774   @param  EDX  Upper 32-bits of MSR value.
4775
4776   <b>Example usage</b>
4777   @code
4778   UINT64  Msr;
4779
4780   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);
4781   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);
4782   @endcode
4783   @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.
4784 **/
4785 #define MSR_HASWELL_E_C11_PMON_BOX_STATUS  0x00000EB7
4786
4787 /**
4788   Package. Uncore C-box 11 perfmon counter 0.
4789
4790   @param  ECX  MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)
4791   @param  EAX  Lower 32-bits of MSR value.
4792   @param  EDX  Upper 32-bits of MSR value.
4793
4794   <b>Example usage</b>
4795   @code
4796   UINT64  Msr;
4797
4798   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);
4799   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);
4800   @endcode
4801   @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
4802 **/
4803 #define MSR_HASWELL_E_C11_PMON_CTR0  0x00000EB8
4804
4805 /**
4806   Package. Uncore C-box 11 perfmon counter 1.
4807
4808   @param  ECX  MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)
4809   @param  EAX  Lower 32-bits of MSR value.
4810   @param  EDX  Upper 32-bits of MSR value.
4811
4812   <b>Example usage</b>
4813   @code
4814   UINT64  Msr;
4815
4816   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);
4817   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);
4818   @endcode
4819   @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
4820 **/
4821 #define MSR_HASWELL_E_C11_PMON_CTR1  0x00000EB9
4822
4823 /**
4824   Package. Uncore C-box 11 perfmon counter 2.
4825
4826   @param  ECX  MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)
4827   @param  EAX  Lower 32-bits of MSR value.
4828   @param  EDX  Upper 32-bits of MSR value.
4829
4830   <b>Example usage</b>
4831   @code
4832   UINT64  Msr;
4833
4834   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);
4835   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);
4836   @endcode
4837   @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
4838 **/
4839 #define MSR_HASWELL_E_C11_PMON_CTR2  0x00000EBA
4840
4841 /**
4842   Package. Uncore C-box 11 perfmon counter 3.
4843
4844   @param  ECX  MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)
4845   @param  EAX  Lower 32-bits of MSR value.
4846   @param  EDX  Upper 32-bits of MSR value.
4847
4848   <b>Example usage</b>
4849   @code
4850   UINT64  Msr;
4851
4852   Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);
4853   AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);
4854   @endcode
4855   @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
4856 **/
4857 #define MSR_HASWELL_E_C11_PMON_CTR3  0x00000EBB
4858
4859 /**
4860   Package. Uncore C-box 12 perfmon local box wide control.
4861
4862   @param  ECX  MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)
4863   @param  EAX  Lower 32-bits of MSR value.
4864   @param  EDX  Upper 32-bits of MSR value.
4865
4866   <b>Example usage</b>
4867   @code
4868   UINT64  Msr;
4869
4870   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);
4871   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);
4872   @endcode
4873   @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
4874 **/
4875 #define MSR_HASWELL_E_C12_PMON_BOX_CTL  0x00000EC0
4876
4877 /**
4878   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
4879
4880   @param  ECX  MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)
4881   @param  EAX  Lower 32-bits of MSR value.
4882   @param  EDX  Upper 32-bits of MSR value.
4883
4884   <b>Example usage</b>
4885   @code
4886   UINT64  Msr;
4887
4888   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);
4889   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);
4890   @endcode
4891   @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
4892 **/
4893 #define MSR_HASWELL_E_C12_PMON_EVNTSEL0  0x00000EC1
4894
4895 /**
4896   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
4897
4898   @param  ECX  MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)
4899   @param  EAX  Lower 32-bits of MSR value.
4900   @param  EDX  Upper 32-bits of MSR value.
4901
4902   <b>Example usage</b>
4903   @code
4904   UINT64  Msr;
4905
4906   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);
4907   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);
4908   @endcode
4909   @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
4910 **/
4911 #define MSR_HASWELL_E_C12_PMON_EVNTSEL1  0x00000EC2
4912
4913 /**
4914   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
4915
4916   @param  ECX  MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)
4917   @param  EAX  Lower 32-bits of MSR value.
4918   @param  EDX  Upper 32-bits of MSR value.
4919
4920   <b>Example usage</b>
4921   @code
4922   UINT64  Msr;
4923
4924   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);
4925   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);
4926   @endcode
4927   @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
4928 **/
4929 #define MSR_HASWELL_E_C12_PMON_EVNTSEL2  0x00000EC3
4930
4931 /**
4932   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
4933
4934   @param  ECX  MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)
4935   @param  EAX  Lower 32-bits of MSR value.
4936   @param  EDX  Upper 32-bits of MSR value.
4937
4938   <b>Example usage</b>
4939   @code
4940   UINT64  Msr;
4941
4942   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);
4943   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);
4944   @endcode
4945   @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
4946 **/
4947 #define MSR_HASWELL_E_C12_PMON_EVNTSEL3  0x00000EC4
4948
4949 /**
4950   Package. Uncore C-box 12 perfmon box wide filter0.
4951
4952   @param  ECX  MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)
4953   @param  EAX  Lower 32-bits of MSR value.
4954   @param  EDX  Upper 32-bits of MSR value.
4955
4956   <b>Example usage</b>
4957   @code
4958   UINT64  Msr;
4959
4960   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);
4961   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);
4962   @endcode
4963   @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.
4964 **/
4965 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER0  0x00000EC5
4966
4967 /**
4968   Package. Uncore C-box 12 perfmon box wide filter1.
4969
4970   @param  ECX  MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)
4971   @param  EAX  Lower 32-bits of MSR value.
4972   @param  EDX  Upper 32-bits of MSR value.
4973
4974   <b>Example usage</b>
4975   @code
4976   UINT64  Msr;
4977
4978   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);
4979   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);
4980   @endcode
4981   @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
4982 **/
4983 #define MSR_HASWELL_E_C12_PMON_BOX_FILTER1  0x00000EC6
4984
4985 /**
4986   Package. Uncore C-box 12 perfmon box wide status.
4987
4988   @param  ECX  MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)
4989   @param  EAX  Lower 32-bits of MSR value.
4990   @param  EDX  Upper 32-bits of MSR value.
4991
4992   <b>Example usage</b>
4993   @code
4994   UINT64  Msr;
4995
4996   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);
4997   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);
4998   @endcode
4999   @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.
5000 **/
5001 #define MSR_HASWELL_E_C12_PMON_BOX_STATUS  0x00000EC7
5002
5003 /**
5004   Package. Uncore C-box 12 perfmon counter 0.
5005
5006   @param  ECX  MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)
5007   @param  EAX  Lower 32-bits of MSR value.
5008   @param  EDX  Upper 32-bits of MSR value.
5009
5010   <b>Example usage</b>
5011   @code
5012   UINT64  Msr;
5013
5014   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);
5015   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);
5016   @endcode
5017   @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
5018 **/
5019 #define MSR_HASWELL_E_C12_PMON_CTR0  0x00000EC8
5020
5021 /**
5022   Package. Uncore C-box 12 perfmon counter 1.
5023
5024   @param  ECX  MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)
5025   @param  EAX  Lower 32-bits of MSR value.
5026   @param  EDX  Upper 32-bits of MSR value.
5027
5028   <b>Example usage</b>
5029   @code
5030   UINT64  Msr;
5031
5032   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);
5033   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);
5034   @endcode
5035   @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
5036 **/
5037 #define MSR_HASWELL_E_C12_PMON_CTR1  0x00000EC9
5038
5039 /**
5040   Package. Uncore C-box 12 perfmon counter 2.
5041
5042   @param  ECX  MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)
5043   @param  EAX  Lower 32-bits of MSR value.
5044   @param  EDX  Upper 32-bits of MSR value.
5045
5046   <b>Example usage</b>
5047   @code
5048   UINT64  Msr;
5049
5050   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);
5051   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);
5052   @endcode
5053   @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
5054 **/
5055 #define MSR_HASWELL_E_C12_PMON_CTR2  0x00000ECA
5056
5057 /**
5058   Package. Uncore C-box 12 perfmon counter 3.
5059
5060   @param  ECX  MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)
5061   @param  EAX  Lower 32-bits of MSR value.
5062   @param  EDX  Upper 32-bits of MSR value.
5063
5064   <b>Example usage</b>
5065   @code
5066   UINT64  Msr;
5067
5068   Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);
5069   AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);
5070   @endcode
5071   @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
5072 **/
5073 #define MSR_HASWELL_E_C12_PMON_CTR3  0x00000ECB
5074
5075 /**
5076   Package. Uncore C-box 13 perfmon local box wide control.
5077
5078   @param  ECX  MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)
5079   @param  EAX  Lower 32-bits of MSR value.
5080   @param  EDX  Upper 32-bits of MSR value.
5081
5082   <b>Example usage</b>
5083   @code
5084   UINT64  Msr;
5085
5086   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);
5087   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);
5088   @endcode
5089   @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
5090 **/
5091 #define MSR_HASWELL_E_C13_PMON_BOX_CTL  0x00000ED0
5092
5093 /**
5094   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
5095
5096   @param  ECX  MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)
5097   @param  EAX  Lower 32-bits of MSR value.
5098   @param  EDX  Upper 32-bits of MSR value.
5099
5100   <b>Example usage</b>
5101   @code
5102   UINT64  Msr;
5103
5104   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);
5105   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);
5106   @endcode
5107   @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
5108 **/
5109 #define MSR_HASWELL_E_C13_PMON_EVNTSEL0  0x00000ED1
5110
5111 /**
5112   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
5113
5114   @param  ECX  MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)
5115   @param  EAX  Lower 32-bits of MSR value.
5116   @param  EDX  Upper 32-bits of MSR value.
5117
5118   <b>Example usage</b>
5119   @code
5120   UINT64  Msr;
5121
5122   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);
5123   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);
5124   @endcode
5125   @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
5126 **/
5127 #define MSR_HASWELL_E_C13_PMON_EVNTSEL1  0x00000ED2
5128
5129 /**
5130   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
5131
5132   @param  ECX  MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)
5133   @param  EAX  Lower 32-bits of MSR value.
5134   @param  EDX  Upper 32-bits of MSR value.
5135
5136   <b>Example usage</b>
5137   @code
5138   UINT64  Msr;
5139
5140   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);
5141   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);
5142   @endcode
5143   @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
5144 **/
5145 #define MSR_HASWELL_E_C13_PMON_EVNTSEL2  0x00000ED3
5146
5147 /**
5148   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
5149
5150   @param  ECX  MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)
5151   @param  EAX  Lower 32-bits of MSR value.
5152   @param  EDX  Upper 32-bits of MSR value.
5153
5154   <b>Example usage</b>
5155   @code
5156   UINT64  Msr;
5157
5158   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);
5159   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);
5160   @endcode
5161   @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
5162 **/
5163 #define MSR_HASWELL_E_C13_PMON_EVNTSEL3  0x00000ED4
5164
5165 /**
5166   Package. Uncore C-box 13 perfmon box wide filter0.
5167
5168   @param  ECX  MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)
5169   @param  EAX  Lower 32-bits of MSR value.
5170   @param  EDX  Upper 32-bits of MSR value.
5171
5172   <b>Example usage</b>
5173   @code
5174   UINT64  Msr;
5175
5176   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);
5177   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);
5178   @endcode
5179   @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.
5180 **/
5181 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER0  0x00000ED5
5182
5183 /**
5184   Package. Uncore C-box 13 perfmon box wide filter1.
5185
5186   @param  ECX  MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)
5187   @param  EAX  Lower 32-bits of MSR value.
5188   @param  EDX  Upper 32-bits of MSR value.
5189
5190   <b>Example usage</b>
5191   @code
5192   UINT64  Msr;
5193
5194   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);
5195   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);
5196   @endcode
5197   @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
5198 **/
5199 #define MSR_HASWELL_E_C13_PMON_BOX_FILTER1  0x00000ED6
5200
5201 /**
5202   Package. Uncore C-box 13 perfmon box wide status.
5203
5204   @param  ECX  MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)
5205   @param  EAX  Lower 32-bits of MSR value.
5206   @param  EDX  Upper 32-bits of MSR value.
5207
5208   <b>Example usage</b>
5209   @code
5210   UINT64  Msr;
5211
5212   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);
5213   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);
5214   @endcode
5215   @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.
5216 **/
5217 #define MSR_HASWELL_E_C13_PMON_BOX_STATUS  0x00000ED7
5218
5219 /**
5220   Package. Uncore C-box 13 perfmon counter 0.
5221
5222   @param  ECX  MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)
5223   @param  EAX  Lower 32-bits of MSR value.
5224   @param  EDX  Upper 32-bits of MSR value.
5225
5226   <b>Example usage</b>
5227   @code
5228   UINT64  Msr;
5229
5230   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);
5231   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);
5232   @endcode
5233   @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
5234 **/
5235 #define MSR_HASWELL_E_C13_PMON_CTR0  0x00000ED8
5236
5237 /**
5238   Package. Uncore C-box 13 perfmon counter 1.
5239
5240   @param  ECX  MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)
5241   @param  EAX  Lower 32-bits of MSR value.
5242   @param  EDX  Upper 32-bits of MSR value.
5243
5244   <b>Example usage</b>
5245   @code
5246   UINT64  Msr;
5247
5248   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);
5249   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);
5250   @endcode
5251   @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
5252 **/
5253 #define MSR_HASWELL_E_C13_PMON_CTR1  0x00000ED9
5254
5255 /**
5256   Package. Uncore C-box 13 perfmon counter 2.
5257
5258   @param  ECX  MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)
5259   @param  EAX  Lower 32-bits of MSR value.
5260   @param  EDX  Upper 32-bits of MSR value.
5261
5262   <b>Example usage</b>
5263   @code
5264   UINT64  Msr;
5265
5266   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);
5267   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);
5268   @endcode
5269   @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
5270 **/
5271 #define MSR_HASWELL_E_C13_PMON_CTR2  0x00000EDA
5272
5273 /**
5274   Package. Uncore C-box 13 perfmon counter 3.
5275
5276   @param  ECX  MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)
5277   @param  EAX  Lower 32-bits of MSR value.
5278   @param  EDX  Upper 32-bits of MSR value.
5279
5280   <b>Example usage</b>
5281   @code
5282   UINT64  Msr;
5283
5284   Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);
5285   AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);
5286   @endcode
5287   @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
5288 **/
5289 #define MSR_HASWELL_E_C13_PMON_CTR3  0x00000EDB
5290
5291 /**
5292   Package. Uncore C-box 14 perfmon local box wide control.
5293
5294   @param  ECX  MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)
5295   @param  EAX  Lower 32-bits of MSR value.
5296   @param  EDX  Upper 32-bits of MSR value.
5297
5298   <b>Example usage</b>
5299   @code
5300   UINT64  Msr;
5301
5302   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);
5303   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);
5304   @endcode
5305   @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
5306 **/
5307 #define MSR_HASWELL_E_C14_PMON_BOX_CTL  0x00000EE0
5308
5309 /**
5310   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
5311
5312   @param  ECX  MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)
5313   @param  EAX  Lower 32-bits of MSR value.
5314   @param  EDX  Upper 32-bits of MSR value.
5315
5316   <b>Example usage</b>
5317   @code
5318   UINT64  Msr;
5319
5320   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);
5321   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);
5322   @endcode
5323   @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
5324 **/
5325 #define MSR_HASWELL_E_C14_PMON_EVNTSEL0  0x00000EE1
5326
5327 /**
5328   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
5329
5330   @param  ECX  MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)
5331   @param  EAX  Lower 32-bits of MSR value.
5332   @param  EDX  Upper 32-bits of MSR value.
5333
5334   <b>Example usage</b>
5335   @code
5336   UINT64  Msr;
5337
5338   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);
5339   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);
5340   @endcode
5341   @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
5342 **/
5343 #define MSR_HASWELL_E_C14_PMON_EVNTSEL1  0x00000EE2
5344
5345 /**
5346   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
5347
5348   @param  ECX  MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)
5349   @param  EAX  Lower 32-bits of MSR value.
5350   @param  EDX  Upper 32-bits of MSR value.
5351
5352   <b>Example usage</b>
5353   @code
5354   UINT64  Msr;
5355
5356   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);
5357   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);
5358   @endcode
5359   @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
5360 **/
5361 #define MSR_HASWELL_E_C14_PMON_EVNTSEL2  0x00000EE3
5362
5363 /**
5364   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
5365
5366   @param  ECX  MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)
5367   @param  EAX  Lower 32-bits of MSR value.
5368   @param  EDX  Upper 32-bits of MSR value.
5369
5370   <b>Example usage</b>
5371   @code
5372   UINT64  Msr;
5373
5374   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);
5375   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);
5376   @endcode
5377   @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
5378 **/
5379 #define MSR_HASWELL_E_C14_PMON_EVNTSEL3  0x00000EE4
5380
5381 /**
5382   Package. Uncore C-box 14 perfmon box wide filter0.
5383
5384   @param  ECX  MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)
5385   @param  EAX  Lower 32-bits of MSR value.
5386   @param  EDX  Upper 32-bits of MSR value.
5387
5388   <b>Example usage</b>
5389   @code
5390   UINT64  Msr;
5391
5392   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);
5393   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);
5394   @endcode
5395   @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
5396 **/
5397 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER  0x00000EE5
5398
5399 /**
5400   Package. Uncore C-box 14 perfmon box wide filter1.
5401
5402   @param  ECX  MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)
5403   @param  EAX  Lower 32-bits of MSR value.
5404   @param  EDX  Upper 32-bits of MSR value.
5405
5406   <b>Example usage</b>
5407   @code
5408   UINT64  Msr;
5409
5410   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);
5411   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);
5412   @endcode
5413   @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
5414 **/
5415 #define MSR_HASWELL_E_C14_PMON_BOX_FILTER1  0x00000EE6
5416
5417 /**
5418   Package. Uncore C-box 14 perfmon box wide status.
5419
5420   @param  ECX  MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)
5421   @param  EAX  Lower 32-bits of MSR value.
5422   @param  EDX  Upper 32-bits of MSR value.
5423
5424   <b>Example usage</b>
5425   @code
5426   UINT64  Msr;
5427
5428   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);
5429   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);
5430   @endcode
5431   @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.
5432 **/
5433 #define MSR_HASWELL_E_C14_PMON_BOX_STATUS  0x00000EE7
5434
5435 /**
5436   Package. Uncore C-box 14 perfmon counter 0.
5437
5438   @param  ECX  MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)
5439   @param  EAX  Lower 32-bits of MSR value.
5440   @param  EDX  Upper 32-bits of MSR value.
5441
5442   <b>Example usage</b>
5443   @code
5444   UINT64  Msr;
5445
5446   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);
5447   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);
5448   @endcode
5449   @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
5450 **/
5451 #define MSR_HASWELL_E_C14_PMON_CTR0  0x00000EE8
5452
5453 /**
5454   Package. Uncore C-box 14 perfmon counter 1.
5455
5456   @param  ECX  MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)
5457   @param  EAX  Lower 32-bits of MSR value.
5458   @param  EDX  Upper 32-bits of MSR value.
5459
5460   <b>Example usage</b>
5461   @code
5462   UINT64  Msr;
5463
5464   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);
5465   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);
5466   @endcode
5467   @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
5468 **/
5469 #define MSR_HASWELL_E_C14_PMON_CTR1  0x00000EE9
5470
5471 /**
5472   Package. Uncore C-box 14 perfmon counter 2.
5473
5474   @param  ECX  MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)
5475   @param  EAX  Lower 32-bits of MSR value.
5476   @param  EDX  Upper 32-bits of MSR value.
5477
5478   <b>Example usage</b>
5479   @code
5480   UINT64  Msr;
5481
5482   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);
5483   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);
5484   @endcode
5485   @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
5486 **/
5487 #define MSR_HASWELL_E_C14_PMON_CTR2  0x00000EEA
5488
5489 /**
5490   Package. Uncore C-box 14 perfmon counter 3.
5491
5492   @param  ECX  MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)
5493   @param  EAX  Lower 32-bits of MSR value.
5494   @param  EDX  Upper 32-bits of MSR value.
5495
5496   <b>Example usage</b>
5497   @code
5498   UINT64  Msr;
5499
5500   Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);
5501   AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);
5502   @endcode
5503   @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
5504 **/
5505 #define MSR_HASWELL_E_C14_PMON_CTR3  0x00000EEB
5506
5507 /**
5508   Package. Uncore C-box 15 perfmon local box wide control.
5509
5510   @param  ECX  MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)
5511   @param  EAX  Lower 32-bits of MSR value.
5512   @param  EDX  Upper 32-bits of MSR value.
5513
5514   <b>Example usage</b>
5515   @code
5516   UINT64  Msr;
5517
5518   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);
5519   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);
5520   @endcode
5521   @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.
5522 **/
5523 #define MSR_HASWELL_E_C15_PMON_BOX_CTL  0x00000EF0
5524
5525 /**
5526   Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.
5527
5528   @param  ECX  MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)
5529   @param  EAX  Lower 32-bits of MSR value.
5530   @param  EDX  Upper 32-bits of MSR value.
5531
5532   <b>Example usage</b>
5533   @code
5534   UINT64  Msr;
5535
5536   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);
5537   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);
5538   @endcode
5539   @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.
5540 **/
5541 #define MSR_HASWELL_E_C15_PMON_EVNTSEL0  0x00000EF1
5542
5543 /**
5544   Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.
5545
5546   @param  ECX  MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)
5547   @param  EAX  Lower 32-bits of MSR value.
5548   @param  EDX  Upper 32-bits of MSR value.
5549
5550   <b>Example usage</b>
5551   @code
5552   UINT64  Msr;
5553
5554   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);
5555   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);
5556   @endcode
5557   @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.
5558 **/
5559 #define MSR_HASWELL_E_C15_PMON_EVNTSEL1  0x00000EF2
5560
5561 /**
5562   Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.
5563
5564   @param  ECX  MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)
5565   @param  EAX  Lower 32-bits of MSR value.
5566   @param  EDX  Upper 32-bits of MSR value.
5567
5568   <b>Example usage</b>
5569   @code
5570   UINT64  Msr;
5571
5572   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);
5573   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);
5574   @endcode
5575   @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.
5576 **/
5577 #define MSR_HASWELL_E_C15_PMON_EVNTSEL2  0x00000EF3
5578
5579 /**
5580   Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.
5581
5582   @param  ECX  MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)
5583   @param  EAX  Lower 32-bits of MSR value.
5584   @param  EDX  Upper 32-bits of MSR value.
5585
5586   <b>Example usage</b>
5587   @code
5588   UINT64  Msr;
5589
5590   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);
5591   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);
5592   @endcode
5593   @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.
5594 **/
5595 #define MSR_HASWELL_E_C15_PMON_EVNTSEL3  0x00000EF4
5596
5597 /**
5598   Package. Uncore C-box 15 perfmon box wide filter0.
5599
5600   @param  ECX  MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)
5601   @param  EAX  Lower 32-bits of MSR value.
5602   @param  EDX  Upper 32-bits of MSR value.
5603
5604   <b>Example usage</b>
5605   @code
5606   UINT64  Msr;
5607
5608   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);
5609   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);
5610   @endcode
5611   @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.
5612 **/
5613 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER0  0x00000EF5
5614
5615 /**
5616   Package. Uncore C-box 15 perfmon box wide filter1.
5617
5618   @param  ECX  MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)
5619   @param  EAX  Lower 32-bits of MSR value.
5620   @param  EDX  Upper 32-bits of MSR value.
5621
5622   <b>Example usage</b>
5623   @code
5624   UINT64  Msr;
5625
5626   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);
5627   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);
5628   @endcode
5629   @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.
5630 **/
5631 #define MSR_HASWELL_E_C15_PMON_BOX_FILTER1  0x00000EF6
5632
5633 /**
5634   Package. Uncore C-box 15 perfmon box wide status.
5635
5636   @param  ECX  MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)
5637   @param  EAX  Lower 32-bits of MSR value.
5638   @param  EDX  Upper 32-bits of MSR value.
5639
5640   <b>Example usage</b>
5641   @code
5642   UINT64  Msr;
5643
5644   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);
5645   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);
5646   @endcode
5647   @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.
5648 **/
5649 #define MSR_HASWELL_E_C15_PMON_BOX_STATUS  0x00000EF7
5650
5651 /**
5652   Package. Uncore C-box 15 perfmon counter 0.
5653
5654   @param  ECX  MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)
5655   @param  EAX  Lower 32-bits of MSR value.
5656   @param  EDX  Upper 32-bits of MSR value.
5657
5658   <b>Example usage</b>
5659   @code
5660   UINT64  Msr;
5661
5662   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);
5663   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);
5664   @endcode
5665   @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.
5666 **/
5667 #define MSR_HASWELL_E_C15_PMON_CTR0  0x00000EF8
5668
5669 /**
5670   Package. Uncore C-box 15 perfmon counter 1.
5671
5672   @param  ECX  MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)
5673   @param  EAX  Lower 32-bits of MSR value.
5674   @param  EDX  Upper 32-bits of MSR value.
5675
5676   <b>Example usage</b>
5677   @code
5678   UINT64  Msr;
5679
5680   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);
5681   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);
5682   @endcode
5683   @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.
5684 **/
5685 #define MSR_HASWELL_E_C15_PMON_CTR1  0x00000EF9
5686
5687 /**
5688   Package. Uncore C-box 15 perfmon counter 2.
5689
5690   @param  ECX  MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)
5691   @param  EAX  Lower 32-bits of MSR value.
5692   @param  EDX  Upper 32-bits of MSR value.
5693
5694   <b>Example usage</b>
5695   @code
5696   UINT64  Msr;
5697
5698   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);
5699   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);
5700   @endcode
5701   @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.
5702 **/
5703 #define MSR_HASWELL_E_C15_PMON_CTR2  0x00000EFA
5704
5705 /**
5706   Package. Uncore C-box 15 perfmon counter 3.
5707
5708   @param  ECX  MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)
5709   @param  EAX  Lower 32-bits of MSR value.
5710   @param  EDX  Upper 32-bits of MSR value.
5711
5712   <b>Example usage</b>
5713   @code
5714   UINT64  Msr;
5715
5716   Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);
5717   AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);
5718   @endcode
5719   @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.
5720 **/
5721 #define MSR_HASWELL_E_C15_PMON_CTR3  0x00000EFB
5722
5723 /**
5724   Package. Uncore C-box 16 perfmon for box-wide control.
5725
5726   @param  ECX  MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)
5727   @param  EAX  Lower 32-bits of MSR value.
5728   @param  EDX  Upper 32-bits of MSR value.
5729
5730   <b>Example usage</b>
5731   @code
5732   UINT64  Msr;
5733
5734   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);
5735   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);
5736   @endcode
5737   @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.
5738 **/
5739 #define MSR_HASWELL_E_C16_PMON_BOX_CTL  0x00000F00
5740
5741 /**
5742   Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.
5743
5744   @param  ECX  MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)
5745   @param  EAX  Lower 32-bits of MSR value.
5746   @param  EDX  Upper 32-bits of MSR value.
5747
5748   <b>Example usage</b>
5749   @code
5750   UINT64  Msr;
5751
5752   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);
5753   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);
5754   @endcode
5755   @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.
5756 **/
5757 #define MSR_HASWELL_E_C16_PMON_EVNTSEL0  0x00000F01
5758
5759 /**
5760   Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.
5761
5762   @param  ECX  MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)
5763   @param  EAX  Lower 32-bits of MSR value.
5764   @param  EDX  Upper 32-bits of MSR value.
5765
5766   <b>Example usage</b>
5767   @code
5768   UINT64  Msr;
5769
5770   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);
5771   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);
5772   @endcode
5773   @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.
5774 **/
5775 #define MSR_HASWELL_E_C16_PMON_EVNTSEL1  0x00000F02
5776
5777 /**
5778   Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.
5779
5780   @param  ECX  MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)
5781   @param  EAX  Lower 32-bits of MSR value.
5782   @param  EDX  Upper 32-bits of MSR value.
5783
5784   <b>Example usage</b>
5785   @code
5786   UINT64  Msr;
5787
5788   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);
5789   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);
5790   @endcode
5791   @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.
5792 **/
5793 #define MSR_HASWELL_E_C16_PMON_EVNTSEL2  0x00000F03
5794
5795 /**
5796   Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.
5797
5798   @param  ECX  MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)
5799   @param  EAX  Lower 32-bits of MSR value.
5800   @param  EDX  Upper 32-bits of MSR value.
5801
5802   <b>Example usage</b>
5803   @code
5804   UINT64  Msr;
5805
5806   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);
5807   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);
5808   @endcode
5809   @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.
5810 **/
5811 #define MSR_HASWELL_E_C16_PMON_EVNTSEL3  0x00000F04
5812
5813 /**
5814   Package. Uncore C-box 16 perfmon box wide filter 0.
5815
5816   @param  ECX  MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)
5817   @param  EAX  Lower 32-bits of MSR value.
5818   @param  EDX  Upper 32-bits of MSR value.
5819
5820   <b>Example usage</b>
5821   @code
5822   UINT64  Msr;
5823
5824   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);
5825   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);
5826   @endcode
5827   @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.
5828 **/
5829 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER0  0x00000F05
5830
5831 /**
5832   Package. Uncore C-box 16 perfmon box wide filter 1.
5833
5834   @param  ECX  MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)
5835   @param  EAX  Lower 32-bits of MSR value.
5836   @param  EDX  Upper 32-bits of MSR value.
5837
5838   <b>Example usage</b>
5839   @code
5840   UINT64  Msr;
5841
5842   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);
5843   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);
5844   @endcode
5845   @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.
5846 **/
5847 #define MSR_HASWELL_E_C16_PMON_BOX_FILTER1  0x00000F06
5848
5849 /**
5850   Package. Uncore C-box 16 perfmon box wide status.
5851
5852   @param  ECX  MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)
5853   @param  EAX  Lower 32-bits of MSR value.
5854   @param  EDX  Upper 32-bits of MSR value.
5855
5856   <b>Example usage</b>
5857   @code
5858   UINT64  Msr;
5859
5860   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);
5861   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);
5862   @endcode
5863   @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.
5864 **/
5865 #define MSR_HASWELL_E_C16_PMON_BOX_STATUS  0x00000F07
5866
5867 /**
5868   Package. Uncore C-box 16 perfmon counter 0.
5869
5870   @param  ECX  MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)
5871   @param  EAX  Lower 32-bits of MSR value.
5872   @param  EDX  Upper 32-bits of MSR value.
5873
5874   <b>Example usage</b>
5875   @code
5876   UINT64  Msr;
5877
5878   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);
5879   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);
5880   @endcode
5881   @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.
5882 **/
5883 #define MSR_HASWELL_E_C16_PMON_CTR0  0x00000F08
5884
5885 /**
5886   Package. Uncore C-box 16 perfmon counter 1.
5887
5888   @param  ECX  MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)
5889   @param  EAX  Lower 32-bits of MSR value.
5890   @param  EDX  Upper 32-bits of MSR value.
5891
5892   <b>Example usage</b>
5893   @code
5894   UINT64  Msr;
5895
5896   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);
5897   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);
5898   @endcode
5899   @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.
5900 **/
5901 #define MSR_HASWELL_E_C16_PMON_CTR1  0x00000F09
5902
5903 /**
5904   Package. Uncore C-box 16 perfmon counter 2.
5905
5906   @param  ECX  MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)
5907   @param  EAX  Lower 32-bits of MSR value.
5908   @param  EDX  Upper 32-bits of MSR value.
5909
5910   <b>Example usage</b>
5911   @code
5912   UINT64  Msr;
5913
5914   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);
5915   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);
5916   @endcode
5917   @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.
5918 **/
5919 #define MSR_HASWELL_E_C16_PMON_CTR2  0x00000F0A
5920
5921 /**
5922   Package. Uncore C-box 16 perfmon counter 3.
5923
5924   @param  ECX  MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)
5925   @param  EAX  Lower 32-bits of MSR value.
5926   @param  EDX  Upper 32-bits of MSR value.
5927
5928   <b>Example usage</b>
5929   @code
5930   UINT64  Msr;
5931
5932   Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);
5933   AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);
5934   @endcode
5935   @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.
5936 **/
5937 #define MSR_HASWELL_E_C16_PMON_CTR3  0x00000E0B
5938
5939 /**
5940   Package. Uncore C-box 17 perfmon for box-wide control.
5941
5942   @param  ECX  MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)
5943   @param  EAX  Lower 32-bits of MSR value.
5944   @param  EDX  Upper 32-bits of MSR value.
5945
5946   <b>Example usage</b>
5947   @code
5948   UINT64  Msr;
5949
5950   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);
5951   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);
5952   @endcode
5953   @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.
5954 **/
5955 #define MSR_HASWELL_E_C17_PMON_BOX_CTL  0x00000F10
5956
5957 /**
5958   Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.
5959
5960   @param  ECX  MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)
5961   @param  EAX  Lower 32-bits of MSR value.
5962   @param  EDX  Upper 32-bits of MSR value.
5963
5964   <b>Example usage</b>
5965   @code
5966   UINT64  Msr;
5967
5968   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);
5969   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);
5970   @endcode
5971   @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.
5972 **/
5973 #define MSR_HASWELL_E_C17_PMON_EVNTSEL0  0x00000F11
5974
5975 /**
5976   Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.
5977
5978   @param  ECX  MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)
5979   @param  EAX  Lower 32-bits of MSR value.
5980   @param  EDX  Upper 32-bits of MSR value.
5981
5982   <b>Example usage</b>
5983   @code
5984   UINT64  Msr;
5985
5986   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);
5987   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);
5988   @endcode
5989   @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.
5990 **/
5991 #define MSR_HASWELL_E_C17_PMON_EVNTSEL1  0x00000F12
5992
5993 /**
5994   Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.
5995
5996   @param  ECX  MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)
5997   @param  EAX  Lower 32-bits of MSR value.
5998   @param  EDX  Upper 32-bits of MSR value.
5999
6000   <b>Example usage</b>
6001   @code
6002   UINT64  Msr;
6003
6004   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);
6005   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);
6006   @endcode
6007   @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.
6008 **/
6009 #define MSR_HASWELL_E_C17_PMON_EVNTSEL2  0x00000F13
6010
6011 /**
6012   Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.
6013
6014   @param  ECX  MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)
6015   @param  EAX  Lower 32-bits of MSR value.
6016   @param  EDX  Upper 32-bits of MSR value.
6017
6018   <b>Example usage</b>
6019   @code
6020   UINT64  Msr;
6021
6022   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);
6023   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);
6024   @endcode
6025   @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.
6026 **/
6027 #define MSR_HASWELL_E_C17_PMON_EVNTSEL3  0x00000F14
6028
6029 /**
6030   Package. Uncore C-box 17 perfmon box wide filter 0.
6031
6032   @param  ECX  MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)
6033   @param  EAX  Lower 32-bits of MSR value.
6034   @param  EDX  Upper 32-bits of MSR value.
6035
6036   <b>Example usage</b>
6037   @code
6038   UINT64  Msr;
6039
6040   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);
6041   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);
6042   @endcode
6043   @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.
6044 **/
6045 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER0  0x00000F15
6046
6047 /**
6048   Package. Uncore C-box 17 perfmon box wide filter1.
6049
6050   @param  ECX  MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)
6051   @param  EAX  Lower 32-bits of MSR value.
6052   @param  EDX  Upper 32-bits of MSR value.
6053
6054   <b>Example usage</b>
6055   @code
6056   UINT64  Msr;
6057
6058   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);
6059   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);
6060   @endcode
6061   @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.
6062 **/
6063 #define MSR_HASWELL_E_C17_PMON_BOX_FILTER1  0x00000F16
6064
6065 /**
6066   Package. Uncore C-box 17 perfmon box wide status.
6067
6068   @param  ECX  MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)
6069   @param  EAX  Lower 32-bits of MSR value.
6070   @param  EDX  Upper 32-bits of MSR value.
6071
6072   <b>Example usage</b>
6073   @code
6074   UINT64  Msr;
6075
6076   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);
6077   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);
6078   @endcode
6079   @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.
6080 **/
6081 #define MSR_HASWELL_E_C17_PMON_BOX_STATUS  0x00000F17
6082
6083 /**
6084   Package. Uncore C-box 17 perfmon counter n.
6085
6086   @param  ECX  MSR_HASWELL_E_C17_PMON_CTRn
6087   @param  EAX  Lower 32-bits of MSR value.
6088   @param  EDX  Upper 32-bits of MSR value.
6089
6090   <b>Example usage</b>
6091   @code
6092   UINT64  Msr;
6093
6094   Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
6095   AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);
6096   @endcode
6097   @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.
6098         MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.
6099         MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.
6100         MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.
6101   @{
6102 **/
6103 #define MSR_HASWELL_E_C17_PMON_CTR0  0x00000F18
6104 #define MSR_HASWELL_E_C17_PMON_CTR1  0x00000F19
6105 #define MSR_HASWELL_E_C17_PMON_CTR2  0x00000F1A
6106 #define MSR_HASWELL_E_C17_PMON_CTR3  0x00000F1B
6107 /// @}
6108
6109 #endif