2 MSR Definitions for Intel processors based on the Haswell microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __HASWELL_MSR_H__
19 #define __HASWELL_MSR_H__
21 #include <Register/Intel/ArchitecturalMsr.h>
24 Is Intel processors based on the Haswell microarchitecture?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x3C || \
36 DisplayModel == 0x45 || \
37 DisplayModel == 0x46 \
44 @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE)
45 @param EAX Lower 32-bits of MSR value.
46 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
47 @param EDX Upper 32-bits of MSR value.
48 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
52 MSR_HASWELL_PLATFORM_INFO_REGISTER Msr;
54 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);
55 AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);
57 @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
59 #define MSR_HASWELL_PLATFORM_INFO 0x000000CE
62 MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO
66 /// Individual bit fields
71 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
72 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
75 UINT32 MaximumNonTurboRatio
: 8;
76 UINT32 Reserved2
: 12;
78 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
79 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
80 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
81 /// Turbo mode is disabled.
83 UINT32 RatioLimit
: 1;
85 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
86 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
87 /// and when set to 0, indicates TDP Limit for Turbo mode is not
93 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,
94 /// indicates that LPM is supported, and when set to 0, indicates LPM is
97 UINT32 LowPowerModeSupport
: 1;
99 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
100 /// TDP level available. 01: One additional TDP level available. 02: Two
101 /// additional TDP level available. 11: Reserved.
103 UINT32 ConfigTDPLevels
: 2;
104 UINT32 Reserved4
: 5;
106 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
107 /// minimum ratio (maximum efficiency) that the processor can operates, in
110 UINT32 MaximumEfficiencyRatio
: 8;
112 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
113 /// minimum supported operating ratio in units of 100 MHz.
115 UINT32 MinimumOperatingRatio
: 8;
116 UINT32 Reserved5
: 8;
119 /// All bit fields as a 64-bit value
122 } MSR_HASWELL_PLATFORM_INFO_REGISTER
;
125 Thread. Performance Event Select for Counter n (R/W) Supports all fields
126 described inTable 2-2 and the fields below.
128 @param ECX MSR_HASWELL_IA32_PERFEVTSELn
129 @param EAX Lower 32-bits of MSR value.
130 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
131 @param EDX Upper 32-bits of MSR value.
132 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
136 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr;
138 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);
139 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);
141 @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
142 MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
143 MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
146 #define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186
147 #define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187
148 #define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189
152 MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0,
153 #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.
157 /// Individual bit fields
161 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
163 UINT32 EventSelect
: 8;
165 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
166 /// detect on the selected event logic.
170 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
174 /// [Bit 17] OS: Counts while in privilege level is ring 0.
178 /// [Bit 18] Edge: Enables edge detection if set.
182 /// [Bit 19] PC: enables pin control.
186 /// [Bit 20] INT: enables interrupt on counter overflow.
190 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
191 /// event conditions occurring across all logical processors sharing a
192 /// processor core. When set to 0, the counter only increments the
193 /// associated event conditions occurring in the logical processor which
194 /// programmed the MSR.
198 /// [Bit 22] EN: enables the corresponding performance counter to commence
199 /// counting when this bit is set.
203 /// [Bit 23] INV: invert the CMASK.
207 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
208 /// performance counter increments each cycle if the event count is
209 /// greater than or equal to the CMASK.
212 UINT32 Reserved
: 32;
214 /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
215 /// AnyThread (bit 21) should be cleared to prevent incorrect results.
218 UINT32 Reserved2
: 31;
221 /// All bit fields as a 64-bit value
224 } MSR_HASWELL_IA32_PERFEVTSEL_REGISTER
;
227 Thread. Performance Event Select for Counter 2 (R/W) Supports all fields
228 described inTable 2-2 and the fields below.
230 @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)
231 @param EAX Lower 32-bits of MSR value.
232 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
233 @param EDX Upper 32-bits of MSR value.
234 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
238 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr;
240 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);
241 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);
243 @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
245 #define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188
248 MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2
252 /// Individual bit fields
256 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
258 UINT32 EventSelect
: 8;
260 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
261 /// detect on the selected event logic.
265 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
269 /// [Bit 17] OS: Counts while in privilege level is ring 0.
273 /// [Bit 18] Edge: Enables edge detection if set.
277 /// [Bit 19] PC: enables pin control.
281 /// [Bit 20] INT: enables interrupt on counter overflow.
285 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
286 /// event conditions occurring across all logical processors sharing a
287 /// processor core. When set to 0, the counter only increments the
288 /// associated event conditions occurring in the logical processor which
289 /// programmed the MSR.
293 /// [Bit 22] EN: enables the corresponding performance counter to commence
294 /// counting when this bit is set.
298 /// [Bit 23] INV: invert the CMASK.
302 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
303 /// performance counter increments each cycle if the event count is
304 /// greater than or equal to the CMASK.
307 UINT32 Reserved
: 32;
309 /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
310 /// AnyThread (bit 21) should be cleared to prevent incorrect results.
314 /// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and
315 /// in sampling, spurious PMI may occur and transactions may continuously
316 /// abort near overflow conditions. Software should favor using IN_TXCP
317 /// for counting over sampling. If sampling, software should use large
318 /// "sample-after" value after clearing the counter configured to use
319 /// IN_TXCP and also always reset the counter even when no overflow
320 /// condition was reported.
323 UINT32 Reserved2
: 30;
326 /// All bit fields as a 64-bit value
329 } MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER
;
332 Thread. Last Branch Record Filtering Select Register (R/W).
334 @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8)
335 @param EAX Lower 32-bits of MSR value.
336 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
337 @param EDX Upper 32-bits of MSR value.
338 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
342 MSR_HASWELL_LBR_SELECT_REGISTER Msr;
344 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);
345 AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);
347 @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
349 #define MSR_HASWELL_LBR_SELECT 0x000001C8
352 MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT
356 /// Individual bit fields
360 /// [Bit 0] CPL_EQ_0.
364 /// [Bit 1] CPL_NEQ_0.
366 UINT32 CPL_NEQ_0
: 1;
372 /// [Bit 3] NEAR_REL_CALL.
374 UINT32 NEAR_REL_CALL
: 1;
376 /// [Bit 4] NEAR_IND_CALL.
378 UINT32 NEAR_IND_CALL
: 1;
380 /// [Bit 5] NEAR_RET.
384 /// [Bit 6] NEAR_IND_JMP.
386 UINT32 NEAR_IND_JMP
: 1;
388 /// [Bit 7] NEAR_REL_JMP.
390 UINT32 NEAR_REL_JMP
: 1;
392 /// [Bit 8] FAR_BRANCH.
394 UINT32 FAR_BRANCH
: 1;
396 /// [Bit 9] EN_CALL_STACK.
398 UINT32 EN_CALL_STACK
: 1;
399 UINT32 Reserved1
: 22;
400 UINT32 Reserved2
: 32;
403 /// All bit fields as a 32-bit value
407 /// All bit fields as a 64-bit value
410 } MSR_HASWELL_LBR_SELECT_REGISTER
;
413 Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines
414 the interrupt response time limit used by the processor to manage transition
415 to package C6 or C7 state. The latency programmed in this register is for
416 the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state.
417 Note: C-state values are processor specific C-state code names, unrelated to
418 MWAIT extension C-state parameters or ACPI C-States.
420 @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B)
421 @param EAX Lower 32-bits of MSR value.
422 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
423 @param EDX Upper 32-bits of MSR value.
424 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
428 MSR_HASWELL_PKGC_IRTL1_REGISTER Msr;
430 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);
431 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);
433 @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
435 #define MSR_HASWELL_PKGC_IRTL1 0x0000060B
438 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1
442 /// Individual bit fields
446 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
447 /// that should be used to decide if the package should be put into a
448 /// package C6 or C7 state.
450 UINT32 InterruptResponseTimeLimit
: 10;
452 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
453 /// of the interrupt response time limit. See Table 2-19 for supported
454 /// time unit encodings.
457 UINT32 Reserved1
: 2;
459 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
460 /// valid and can be used by the processor for package C-sate management.
463 UINT32 Reserved2
: 16;
464 UINT32 Reserved3
: 32;
467 /// All bit fields as a 32-bit value
471 /// All bit fields as a 64-bit value
474 } MSR_HASWELL_PKGC_IRTL1_REGISTER
;
477 Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines
478 the interrupt response time limit used by the processor to manage transition
479 to package C6 or C7 state. The latency programmed in this register is for
480 the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.
481 Note: C-state values are processor specific C-state code names, unrelated to
482 MWAIT extension C-state parameters or ACPI C-States.
484 @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C)
485 @param EAX Lower 32-bits of MSR value.
486 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
487 @param EDX Upper 32-bits of MSR value.
488 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
492 MSR_HASWELL_PKGC_IRTL2_REGISTER Msr;
494 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);
495 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);
497 @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
499 #define MSR_HASWELL_PKGC_IRTL2 0x0000060C
502 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2
506 /// Individual bit fields
510 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
511 /// that should be used to decide if the package should be put into a
512 /// package C6 or C7 state.
514 UINT32 InterruptResponseTimeLimit
: 10;
516 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
517 /// of the interrupt response time limit. See Table 2-19 for supported
518 /// time unit encodings.
521 UINT32 Reserved1
: 2;
523 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
524 /// valid and can be used by the processor for package C-sate management.
527 UINT32 Reserved2
: 16;
528 UINT32 Reserved3
: 32;
531 /// All bit fields as a 32-bit value
535 /// All bit fields as a 64-bit value
538 } MSR_HASWELL_PKGC_IRTL2_REGISTER
;
541 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
543 @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613)
544 @param EAX Lower 32-bits of MSR value.
545 @param EDX Upper 32-bits of MSR value.
551 Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);
553 @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
555 #define MSR_HASWELL_PKG_PERF_STATUS 0x00000613
558 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
560 @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)
561 @param EAX Lower 32-bits of MSR value.
562 @param EDX Upper 32-bits of MSR value.
568 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);
570 @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
572 #define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619
575 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
578 @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)
579 @param EAX Lower 32-bits of MSR value.
580 @param EDX Upper 32-bits of MSR value.
586 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);
588 @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
590 #define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B
593 Package. Base TDP Ratio (R/O).
595 @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)
596 @param EAX Lower 32-bits of MSR value.
597 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
598 @param EDX Upper 32-bits of MSR value.
599 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
603 MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr;
605 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);
607 @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
609 #define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648
612 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL
616 /// Individual bit fields
620 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
621 /// specific processor (in units of 100 MHz).
623 UINT32 Config_TDP_Base
: 8;
624 UINT32 Reserved1
: 24;
625 UINT32 Reserved2
: 32;
628 /// All bit fields as a 32-bit value
632 /// All bit fields as a 64-bit value
635 } MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER
;
638 Package. ConfigTDP Level 1 ratio and power level (R/O).
640 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)
641 @param EAX Lower 32-bits of MSR value.
642 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
643 @param EDX Upper 32-bits of MSR value.
644 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
648 MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr;
650 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);
652 @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
654 #define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649
657 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1
661 /// Individual bit fields
665 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
667 UINT32 PKG_TDP_LVL1
: 15;
668 UINT32 Reserved1
: 1;
670 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
671 /// for this specific processor.
673 UINT32 Config_TDP_LVL1_Ratio
: 8;
674 UINT32 Reserved2
: 8;
676 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
679 UINT32 PKG_MAX_PWR_LVL1
: 15;
681 /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
684 UINT32 PKG_MIN_PWR_LVL1
: 16;
685 UINT32 Reserved3
: 1;
688 /// All bit fields as a 64-bit value
691 } MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER
;
694 Package. ConfigTDP Level 2 ratio and power level (R/O).
696 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)
697 @param EAX Lower 32-bits of MSR value.
698 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
699 @param EDX Upper 32-bits of MSR value.
700 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
704 MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr;
706 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);
708 @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
710 #define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A
713 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2
717 /// Individual bit fields
721 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
723 UINT32 PKG_TDP_LVL2
: 15;
724 UINT32 Reserved1
: 1;
726 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
727 /// for this specific processor.
729 UINT32 Config_TDP_LVL2_Ratio
: 8;
730 UINT32 Reserved2
: 8;
732 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
735 UINT32 PKG_MAX_PWR_LVL2
: 15;
737 /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
740 UINT32 PKG_MIN_PWR_LVL2
: 16;
741 UINT32 Reserved3
: 1;
744 /// All bit fields as a 64-bit value
747 } MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER
;
750 Package. ConfigTDP Control (R/W).
752 @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)
753 @param EAX Lower 32-bits of MSR value.
754 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
755 @param EDX Upper 32-bits of MSR value.
756 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
760 MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr;
762 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);
763 AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);
765 @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
767 #define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B
770 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL
774 /// Individual bit fields
778 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
780 UINT32 TDP_LEVEL
: 2;
781 UINT32 Reserved1
: 29;
783 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
784 /// this register is locked until a reset.
786 UINT32 Config_TDP_Lock
: 1;
787 UINT32 Reserved2
: 32;
790 /// All bit fields as a 32-bit value
794 /// All bit fields as a 64-bit value
797 } MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER
;
800 Package. ConfigTDP Control (R/W).
802 @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)
803 @param EAX Lower 32-bits of MSR value.
804 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
805 @param EDX Upper 32-bits of MSR value.
806 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
810 MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr;
812 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);
813 AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);
815 @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
817 #define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C
820 MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO
824 /// Individual bit fields
828 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
831 UINT32 MAX_NON_TURBO_RATIO
: 8;
832 UINT32 Reserved1
: 23;
834 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
835 /// content of this register is locked until a reset.
837 UINT32 TURBO_ACTIVATION_RATIO_Lock
: 1;
838 UINT32 Reserved2
: 32;
841 /// All bit fields as a 32-bit value
845 /// All bit fields as a 64-bit value
848 } MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER
;
851 Core. C-State Configuration Control (R/W) Note: C-state values are processor
852 specific C-state code names, unrelated to MWAIT extension C-state parameters
853 or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.
855 @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
856 @param EAX Lower 32-bits of MSR value.
857 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
858 @param EDX Upper 32-bits of MSR value.
859 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
863 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
865 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);
866 AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
868 @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
870 #define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2
873 MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL
877 /// Individual bit fields
881 /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
882 /// processor-specific C-state code name (consuming the least power) for
883 /// the package. The default is set as factory-configured package C-state
884 /// limit. The following C-state code name encodings are supported: 0000b:
885 /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
886 /// 0100b: C7 0101b: C7s Package C states C7 are not available to
887 /// processor with signature 06_3CH.
890 UINT32 Reserved1
: 6;
892 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
895 UINT32 Reserved2
: 4;
897 /// [Bit 15] CFG Lock (R/WO).
900 UINT32 Reserved3
: 9;
902 /// [Bit 25] C3 State Auto Demotion Enable (R/W).
904 UINT32 C3AutoDemotion
: 1;
906 /// [Bit 26] C1 State Auto Demotion Enable (R/W).
908 UINT32 C1AutoDemotion
: 1;
910 /// [Bit 27] Enable C3 Undemotion (R/W).
912 UINT32 C3Undemotion
: 1;
914 /// [Bit 28] Enable C1 Undemotion (R/W).
916 UINT32 C1Undemotion
: 1;
917 UINT32 Reserved4
: 3;
918 UINT32 Reserved5
: 32;
921 /// All bit fields as a 32-bit value
925 /// All bit fields as a 64-bit value
928 } MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER
;
931 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
932 Enhancement. Accessible only while in SMM.
934 @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D)
935 @param EAX Lower 32-bits of MSR value.
936 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
937 @param EDX Upper 32-bits of MSR value.
938 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
942 MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr;
944 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);
945 AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);
947 @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
949 #define MSR_HASWELL_SMM_MCA_CAP 0x0000017D
952 MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP
956 /// Individual bit fields
959 UINT32 Reserved1
: 32;
960 UINT32 Reserved2
: 26;
962 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
963 /// SMM code access restriction is supported and the
964 /// MSR_SMM_FEATURE_CONTROL is supported.
966 UINT32 SMM_Code_Access_Chk
: 1;
968 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
969 /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is
972 UINT32 Long_Flow_Indication
: 1;
973 UINT32 Reserved3
: 4;
976 /// All bit fields as a 64-bit value
979 } MSR_HASWELL_SMM_MCA_CAP_REGISTER
;
982 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
983 RW if MSR_PLATFORM_INFO.[28] = 1.
985 @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)
986 @param EAX Lower 32-bits of MSR value.
987 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
988 @param EDX Upper 32-bits of MSR value.
989 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
993 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr;
995 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);
997 @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
999 #define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD
1002 MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT
1006 /// Individual bit fields
1010 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
1011 /// limit of 1 core active.
1013 UINT32 Maximum1C
: 8;
1015 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
1016 /// limit of 2 core active.
1018 UINT32 Maximum2C
: 8;
1020 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
1021 /// limit of 3 core active.
1023 UINT32 Maximum3C
: 8;
1025 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
1026 /// limit of 4 core active.
1028 UINT32 Maximum4C
: 8;
1029 UINT32 Reserved
: 32;
1032 /// All bit fields as a 32-bit value
1036 /// All bit fields as a 64-bit value
1039 } MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER
;
1042 Package. Uncore PMU global control.
1044 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)
1045 @param EAX Lower 32-bits of MSR value.
1046 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
1047 @param EDX Upper 32-bits of MSR value.
1048 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
1050 <b>Example usage</b>
1052 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
1054 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);
1055 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
1057 @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
1059 #define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391
1062 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL
1066 /// Individual bit fields
1070 /// [Bit 0] Core 0 select.
1072 UINT32 PMI_Sel_Core0
: 1;
1074 /// [Bit 1] Core 1 select.
1076 UINT32 PMI_Sel_Core1
: 1;
1078 /// [Bit 2] Core 2 select.
1080 UINT32 PMI_Sel_Core2
: 1;
1082 /// [Bit 3] Core 3 select.
1084 UINT32 PMI_Sel_Core3
: 1;
1085 UINT32 Reserved1
: 15;
1086 UINT32 Reserved2
: 10;
1088 /// [Bit 29] Enable all uncore counters.
1092 /// [Bit 30] Enable wake on PMI.
1096 /// [Bit 31] Enable Freezing counter when overflow.
1099 UINT32 Reserved3
: 32;
1102 /// All bit fields as a 32-bit value
1106 /// All bit fields as a 64-bit value
1109 } MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
;
1112 Package. Uncore PMU main status.
1114 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)
1115 @param EAX Lower 32-bits of MSR value.
1116 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
1117 @param EDX Upper 32-bits of MSR value.
1118 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
1120 <b>Example usage</b>
1122 MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
1124 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);
1125 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
1127 @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
1129 #define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392
1132 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS
1136 /// Individual bit fields
1140 /// [Bit 0] Fixed counter overflowed.
1144 /// [Bit 1] An ARB counter overflowed.
1147 UINT32 Reserved1
: 1;
1149 /// [Bit 3] A CBox counter overflowed (on any slice).
1152 UINT32 Reserved2
: 28;
1153 UINT32 Reserved3
: 32;
1156 /// All bit fields as a 32-bit value
1160 /// All bit fields as a 64-bit value
1163 } MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER
;
1166 Package. Uncore fixed counter control (R/W).
1168 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)
1169 @param EAX Lower 32-bits of MSR value.
1170 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
1171 @param EDX Upper 32-bits of MSR value.
1172 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
1174 <b>Example usage</b>
1176 MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr;
1178 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);
1179 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);
1181 @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
1183 #define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394
1186 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL
1190 /// Individual bit fields
1193 UINT32 Reserved1
: 20;
1195 /// [Bit 20] Enable overflow propagation.
1197 UINT32 EnableOverflow
: 1;
1198 UINT32 Reserved2
: 1;
1200 /// [Bit 22] Enable counting.
1202 UINT32 EnableCounting
: 1;
1203 UINT32 Reserved3
: 9;
1204 UINT32 Reserved4
: 32;
1207 /// All bit fields as a 32-bit value
1211 /// All bit fields as a 64-bit value
1214 } MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER
;
1217 Package. Uncore fixed counter.
1219 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)
1220 @param EAX Lower 32-bits of MSR value.
1221 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
1222 @param EDX Upper 32-bits of MSR value.
1223 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
1225 <b>Example usage</b>
1227 MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr;
1229 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);
1230 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);
1232 @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
1234 #define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395
1237 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR
1241 /// Individual bit fields
1245 /// [Bits 31:0] Current count.
1247 UINT32 CurrentCount
: 32;
1249 /// [Bits 47:32] Current count.
1251 UINT32 CurrentCountHi
: 16;
1252 UINT32 Reserved
: 16;
1255 /// All bit fields as a 64-bit value
1258 } MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER
;
1261 Package. Uncore C-Box configuration information (R/O).
1263 @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)
1264 @param EAX Lower 32-bits of MSR value.
1265 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
1266 @param EDX Upper 32-bits of MSR value.
1267 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
1269 <b>Example usage</b>
1271 MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr;
1273 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);
1275 @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
1277 #define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396
1280 MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG
1284 /// Individual bit fields
1288 /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".
1291 UINT32 Reserved1
: 28;
1292 UINT32 Reserved2
: 32;
1295 /// All bit fields as a 32-bit value
1299 /// All bit fields as a 64-bit value
1302 } MSR_HASWELL_UNC_CBO_CONFIG_REGISTER
;
1305 Package. Uncore Arb unit, performance counter 0.
1307 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)
1308 @param EAX Lower 32-bits of MSR value.
1309 @param EDX Upper 32-bits of MSR value.
1311 <b>Example usage</b>
1315 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);
1316 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);
1318 @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
1320 #define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0
1323 Package. Uncore Arb unit, performance counter 1.
1325 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)
1326 @param EAX Lower 32-bits of MSR value.
1327 @param EDX Upper 32-bits of MSR value.
1329 <b>Example usage</b>
1333 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);
1334 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);
1336 @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
1338 #define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1
1341 Package. Uncore Arb unit, counter 0 event select MSR.
1343 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)
1344 @param EAX Lower 32-bits of MSR value.
1345 @param EDX Upper 32-bits of MSR value.
1347 <b>Example usage</b>
1351 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);
1352 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);
1354 @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
1356 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2
1359 Package. Uncore Arb unit, counter 1 event select MSR.
1361 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)
1362 @param EAX Lower 32-bits of MSR value.
1363 @param EDX Upper 32-bits of MSR value.
1365 <b>Example usage</b>
1369 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);
1370 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);
1372 @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
1374 #define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3
1377 Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability
1378 Enhancement. Accessible only while in SMM.
1380 @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)
1381 @param EAX Lower 32-bits of MSR value.
1382 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
1383 @param EDX Upper 32-bits of MSR value.
1384 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
1386 <b>Example usage</b>
1388 MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr;
1390 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);
1391 AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);
1393 @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.
1395 #define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0
1398 MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL
1402 /// Individual bit fields
1406 /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from
1407 /// further changes.
1410 UINT32 Reserved1
: 1;
1412 /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if
1413 /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the
1414 /// logical processors are prevented from executing SMM code outside the
1415 /// ranges defined by the SMRR. When set to '1' any logical processor in
1416 /// the package that attempts to execute SMM code not within the ranges
1417 /// defined by the SMRR will assert an unrecoverable MCE.
1419 UINT32 SMM_Code_Chk_En
: 1;
1420 UINT32 Reserved2
: 29;
1421 UINT32 Reserved3
: 32;
1424 /// All bit fields as a 32-bit value
1428 /// All bit fields as a 64-bit value
1431 } MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER
;
1434 Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical
1435 processors in the package. Available only while in SMM and
1436 MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
1438 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1439 processor of its state in a long flow of internal operation which
1440 delays servicing an interrupt. The corresponding bit will be set at
1441 the start of long events such as: Microcode Update Load, C6, WBINVD,
1442 Ratio Change, Throttle. The bit is automatically cleared at the end of
1443 each long event. The reset value of this field is 0. Only bit
1444 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
1447 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1448 processor of its state in a long flow of internal operation which
1449 delays servicing an interrupt. The corresponding bit will be set at
1450 the start of long events such as: Microcode Update Load, C6, WBINVD,
1451 Ratio Change, Throttle. The bit is automatically cleared at the end of
1452 each long event. The reset value of this field is 0. Only bit
1453 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
1456 @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2)
1457 @param EAX Lower 32-bits of MSR value.
1458 @param EDX Upper 32-bits of MSR value.
1460 <b>Example usage</b>
1464 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);
1466 @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.
1468 #define MSR_HASWELL_SMM_DELAYED 0x000004E2
1471 Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical
1472 processors in the package. Available only while in SMM.
1474 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1475 processor of its blocked state to service an SMI. The corresponding
1476 bit will be set if the logical processor is in one of the following
1477 states: Wait For SIPI or SENTER Sleep. The reset value of this field
1478 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
1479 ECX=PKG_LVL):EBX[15:0] can be updated.
1482 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
1483 processor of its blocked state to service an SMI. The corresponding
1484 bit will be set if the logical processor is in one of the following
1485 states: Wait For SIPI or SENTER Sleep. The reset value of this field
1486 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
1487 ECX=PKG_LVL):EBX[15:0] can be updated.
1489 @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3)
1490 @param EAX Lower 32-bits of MSR value.
1491 @param EDX Upper 32-bits of MSR value.
1493 <b>Example usage</b>
1497 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);
1499 @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.
1501 #define MSR_HASWELL_SMM_BLOCKED 0x000004E3
1504 Package. Unit Multipliers used in RAPL Interfaces (R/O).
1506 @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)
1507 @param EAX Lower 32-bits of MSR value.
1508 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
1509 @param EDX Upper 32-bits of MSR value.
1510 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
1512 <b>Example usage</b>
1514 MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr;
1516 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);
1518 @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1520 #define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606
1523 MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT
1527 /// Individual bit fields
1531 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
1533 UINT32 PowerUnits
: 4;
1534 UINT32 Reserved1
: 4;
1536 /// [Bits 12:8] Package. Energy Status Units Energy related information
1537 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
1538 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
1541 UINT32 EnergyStatusUnits
: 5;
1542 UINT32 Reserved2
: 3;
1544 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
1547 UINT32 TimeUnits
: 4;
1548 UINT32 Reserved3
: 12;
1549 UINT32 Reserved4
: 32;
1552 /// All bit fields as a 32-bit value
1556 /// All bit fields as a 64-bit value
1559 } MSR_HASWELL_RAPL_POWER_UNIT_REGISTER
;
1562 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1565 @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)
1566 @param EAX Lower 32-bits of MSR value.
1567 @param EDX Upper 32-bits of MSR value.
1569 <b>Example usage</b>
1573 Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);
1575 @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1577 #define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639
1580 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1583 @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)
1584 @param EAX Lower 32-bits of MSR value.
1585 @param EDX Upper 32-bits of MSR value.
1587 <b>Example usage</b>
1591 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);
1592 AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);
1594 @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
1596 #define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640
1599 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1602 @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)
1603 @param EAX Lower 32-bits of MSR value.
1604 @param EDX Upper 32-bits of MSR value.
1606 <b>Example usage</b>
1610 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);
1612 @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
1614 #define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641
1617 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
1620 @param ECX MSR_HASWELL_PP1_POLICY (0x00000642)
1621 @param EAX Lower 32-bits of MSR value.
1622 @param EDX Upper 32-bits of MSR value.
1624 <b>Example usage</b>
1628 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);
1629 AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);
1631 @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
1633 #define MSR_HASWELL_PP1_POLICY 0x00000642
1636 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1637 refers to processor core frequency).
1639 @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)
1640 @param EAX Lower 32-bits of MSR value.
1641 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
1642 @param EDX Upper 32-bits of MSR value.
1643 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
1645 <b>Example usage</b>
1647 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
1649 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);
1650 AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
1652 @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
1654 #define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690
1657 MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS
1661 /// Individual bit fields
1665 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
1666 /// reduced below the operating system request due to assertion of
1667 /// external PROCHOT.
1669 UINT32 PROCHOT_Status
: 1;
1671 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
1672 /// operating system request due to a thermal event.
1674 UINT32 ThermalStatus
: 1;
1675 UINT32 Reserved1
: 2;
1677 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
1678 /// below the operating system request due to Processor Graphics driver
1681 UINT32 GraphicsDriverStatus
: 1;
1683 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
1684 /// When set, frequency is reduced below the operating system request
1685 /// because the processor has detected that utilization is low.
1687 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
: 1;
1689 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
1690 /// below the operating system request due to a thermal alert from the
1691 /// Voltage Regulator.
1693 UINT32 VRThermAlertStatus
: 1;
1694 UINT32 Reserved2
: 1;
1696 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
1697 /// reduced below the operating system request due to electrical design
1698 /// point constraints (e.g. maximum electrical current consumption).
1700 UINT32 ElectricalDesignPointStatus
: 1;
1702 /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced
1703 /// below the operating system request due to domain-level power limiting.
1705 UINT32 PLStatus
: 1;
1707 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
1708 /// frequency is reduced below the operating system request due to
1709 /// package-level power limiting PL1.
1711 UINT32 PL1Status
: 1;
1713 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
1714 /// frequency is reduced below the operating system request due to
1715 /// package-level power limiting PL2.
1717 UINT32 PL2Status
: 1;
1719 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced
1720 /// below the operating system request due to multi-core turbo limits.
1722 UINT32 MaxTurboLimitStatus
: 1;
1724 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
1725 /// is reduced below the operating system request due to Turbo transition
1726 /// attenuation. This prevents performance degradation due to frequent
1727 /// operating ratio changes.
1729 UINT32 TurboTransitionAttenuationStatus
: 1;
1730 UINT32 Reserved3
: 2;
1732 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1733 /// has asserted since the log bit was last cleared. This log bit will
1734 /// remain set until cleared by software writing 0.
1736 UINT32 PROCHOT_Log
: 1;
1738 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1739 /// has asserted since the log bit was last cleared. This log bit will
1740 /// remain set until cleared by software writing 0.
1742 UINT32 ThermalLog
: 1;
1743 UINT32 Reserved4
: 2;
1745 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
1746 /// Driver Status bit has asserted since the log bit was last cleared.
1747 /// This log bit will remain set until cleared by software writing 0.
1749 UINT32 GraphicsDriverLog
: 1;
1751 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
1752 /// indicates that the Autonomous Utilization-Based Frequency Control
1753 /// Status bit has asserted since the log bit was last cleared. This log
1754 /// bit will remain set until cleared by software writing 0.
1756 UINT32 AutonomousUtilizationBasedFrequencyControlLog
: 1;
1758 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1759 /// Alert Status bit has asserted since the log bit was last cleared. This
1760 /// log bit will remain set until cleared by software writing 0.
1762 UINT32 VRThermAlertLog
: 1;
1763 UINT32 Reserved5
: 1;
1765 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1766 /// Status bit has asserted since the log bit was last cleared. This log
1767 /// bit will remain set until cleared by software writing 0.
1769 UINT32 ElectricalDesignPointLog
: 1;
1771 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
1772 /// Power Limiting Status bit has asserted since the log bit was last
1773 /// cleared. This log bit will remain set until cleared by software
1778 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
1779 /// that the Package Level PL1 Power Limiting Status bit has asserted
1780 /// since the log bit was last cleared. This log bit will remain set until
1781 /// cleared by software writing 0.
1785 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
1786 /// the Package Level PL2 Power Limiting Status bit has asserted since the
1787 /// log bit was last cleared. This log bit will remain set until cleared
1788 /// by software writing 0.
1792 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
1793 /// Limit Status bit has asserted since the log bit was last cleared. This
1794 /// log bit will remain set until cleared by software writing 0.
1796 UINT32 MaxTurboLimitLog
: 1;
1798 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
1799 /// Turbo Transition Attenuation Status bit has asserted since the log bit
1800 /// was last cleared. This log bit will remain set until cleared by
1801 /// software writing 0.
1803 UINT32 TurboTransitionAttenuationLog
: 1;
1804 UINT32 Reserved6
: 2;
1805 UINT32 Reserved7
: 32;
1808 /// All bit fields as a 32-bit value
1812 /// All bit fields as a 64-bit value
1815 } MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
;
1818 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)
1819 (frequency refers to processor graphics frequency).
1821 @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
1822 @param EAX Lower 32-bits of MSR value.
1823 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1824 @param EDX Upper 32-bits of MSR value.
1825 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
1827 <b>Example usage</b>
1829 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;
1831 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);
1832 AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
1834 @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.
1836 #define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0
1839 MSR information returned for MSR index
1840 #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS
1844 /// Individual bit fields
1848 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
1849 /// operating system request due to assertion of external PROCHOT.
1851 UINT32 PROCHOT_Status
: 1;
1853 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
1854 /// operating system request due to a thermal event.
1856 UINT32 ThermalStatus
: 1;
1857 UINT32 Reserved1
: 2;
1859 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
1860 /// below the operating system request due to Processor Graphics driver
1863 UINT32 GraphicsDriverStatus
: 1;
1865 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
1866 /// When set, frequency is reduced below the operating system request
1867 /// because the processor has detected that utilization is low.
1869 UINT32 AutonomousUtilizationBasedFrequencyControlStatus
: 1;
1871 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
1872 /// below the operating system request due to a thermal alert from the
1873 /// Voltage Regulator.
1875 UINT32 VRThermAlertStatus
: 1;
1876 UINT32 Reserved2
: 1;
1878 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
1879 /// reduced below the operating system request due to electrical design
1880 /// point constraints (e.g. maximum electrical current consumption).
1882 UINT32 ElectricalDesignPointStatus
: 1;
1884 /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is
1885 /// reduced below the operating system request due to domain-level power
1888 UINT32 GraphicsPowerLimitingStatus
: 1;
1890 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
1891 /// frequency is reduced below the operating system request due to
1892 /// package-level power limiting PL1.
1894 UINT32 PL1STatus
: 1;
1896 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
1897 /// frequency is reduced below the operating system request due to
1898 /// package-level power limiting PL2.
1900 UINT32 PL2Status
: 1;
1901 UINT32 Reserved3
: 4;
1903 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
1904 /// has asserted since the log bit was last cleared. This log bit will
1905 /// remain set until cleared by software writing 0.
1907 UINT32 PROCHOT_Log
: 1;
1909 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
1910 /// has asserted since the log bit was last cleared. This log bit will
1911 /// remain set until cleared by software writing 0.
1913 UINT32 ThermalLog
: 1;
1914 UINT32 Reserved4
: 2;
1916 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
1917 /// Driver Status bit has asserted since the log bit was last cleared.
1918 /// This log bit will remain set until cleared by software writing 0.
1920 UINT32 GraphicsDriverLog
: 1;
1922 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
1923 /// indicates that the Autonomous Utilization-Based Frequency Control
1924 /// Status bit has asserted since the log bit was last cleared. This log
1925 /// bit will remain set until cleared by software writing 0.
1927 UINT32 AutonomousUtilizationBasedFrequencyControlLog
: 1;
1929 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
1930 /// Alert Status bit has asserted since the log bit was last cleared. This
1931 /// log bit will remain set until cleared by software writing 0.
1933 UINT32 VRThermAlertLog
: 1;
1934 UINT32 Reserved5
: 1;
1936 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
1937 /// Status bit has asserted since the log bit was last cleared. This log
1938 /// bit will remain set until cleared by software writing 0.
1940 UINT32 ElectricalDesignPointLog
: 1;
1942 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
1943 /// Power Limiting Status bit has asserted since the log bit was last
1944 /// cleared. This log bit will remain set until cleared by software
1947 UINT32 CorePowerLimitingLog
: 1;
1949 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
1950 /// that the Package Level PL1 Power Limiting Status bit has asserted
1951 /// since the log bit was last cleared. This log bit will remain set until
1952 /// cleared by software writing 0.
1956 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
1957 /// the Package Level PL2 Power Limiting Status bit has asserted since the
1958 /// log bit was last cleared. This log bit will remain set until cleared
1959 /// by software writing 0.
1963 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
1964 /// Limit Status bit has asserted since the log bit was last cleared. This
1965 /// log bit will remain set until cleared by software writing 0.
1967 UINT32 MaxTurboLimitLog
: 1;
1969 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
1970 /// Turbo Transition Attenuation Status bit has asserted since the log bit
1971 /// was last cleared. This log bit will remain set until cleared by
1972 /// software writing 0.
1974 UINT32 TurboTransitionAttenuationLog
: 1;
1975 UINT32 Reserved6
: 2;
1976 UINT32 Reserved7
: 32;
1979 /// All bit fields as a 32-bit value
1983 /// All bit fields as a 64-bit value
1986 } MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
;
1989 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)
1990 (frequency refers to ring interconnect in the uncore).
1992 @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)
1993 @param EAX Lower 32-bits of MSR value.
1994 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
1995 @param EDX Upper 32-bits of MSR value.
1996 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
1998 <b>Example usage</b>
2000 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr;
2002 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);
2003 AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);
2005 @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.
2007 #define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1
2010 MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS
2014 /// Individual bit fields
2018 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
2019 /// operating system request due to assertion of external PROCHOT.
2021 UINT32 PROCHOT_Status
: 1;
2023 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
2024 /// operating system request due to a thermal event.
2026 UINT32 ThermalStatus
: 1;
2027 UINT32 Reserved1
: 4;
2029 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
2030 /// below the operating system request due to a thermal alert from the
2031 /// Voltage Regulator.
2033 UINT32 VRThermAlertStatus
: 1;
2034 UINT32 Reserved2
: 1;
2036 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
2037 /// reduced below the operating system request due to electrical design
2038 /// point constraints (e.g. maximum electrical current consumption).
2040 UINT32 ElectricalDesignPointStatus
: 1;
2041 UINT32 Reserved3
: 1;
2043 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
2044 /// frequency is reduced below the operating system request due to
2045 /// package-level power limiting PL1.
2047 UINT32 PL1STatus
: 1;
2049 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
2050 /// frequency is reduced below the operating system request due to
2051 /// package-level power limiting PL2.
2053 UINT32 PL2Status
: 1;
2054 UINT32 Reserved4
: 4;
2056 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit
2057 /// has asserted since the log bit was last cleared. This log bit will
2058 /// remain set until cleared by software writing 0.
2060 UINT32 PROCHOT_Log
: 1;
2062 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit
2063 /// has asserted since the log bit was last cleared. This log bit will
2064 /// remain set until cleared by software writing 0.
2066 UINT32 ThermalLog
: 1;
2067 UINT32 Reserved5
: 2;
2069 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics
2070 /// Driver Status bit has asserted since the log bit was last cleared.
2071 /// This log bit will remain set until cleared by software writing 0.
2073 UINT32 GraphicsDriverLog
: 1;
2075 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,
2076 /// indicates that the Autonomous Utilization-Based Frequency Control
2077 /// Status bit has asserted since the log bit was last cleared. This log
2078 /// bit will remain set until cleared by software writing 0.
2080 UINT32 AutonomousUtilizationBasedFrequencyControlLog
: 1;
2082 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm
2083 /// Alert Status bit has asserted since the log bit was last cleared. This
2084 /// log bit will remain set until cleared by software writing 0.
2086 UINT32 VRThermAlertLog
: 1;
2087 UINT32 Reserved6
: 1;
2089 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP
2090 /// Status bit has asserted since the log bit was last cleared. This log
2091 /// bit will remain set until cleared by software writing 0.
2093 UINT32 ElectricalDesignPointLog
: 1;
2095 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core
2096 /// Power Limiting Status bit has asserted since the log bit was last
2097 /// cleared. This log bit will remain set until cleared by software
2100 UINT32 CorePowerLimitingLog
: 1;
2102 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates
2103 /// that the Package Level PL1 Power Limiting Status bit has asserted
2104 /// since the log bit was last cleared. This log bit will remain set until
2105 /// cleared by software writing 0.
2109 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
2110 /// the Package Level PL2 Power Limiting Status bit has asserted since the
2111 /// log bit was last cleared. This log bit will remain set until cleared
2112 /// by software writing 0.
2116 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
2117 /// Limit Status bit has asserted since the log bit was last cleared. This
2118 /// log bit will remain set until cleared by software writing 0.
2120 UINT32 MaxTurboLimitLog
: 1;
2122 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
2123 /// Turbo Transition Attenuation Status bit has asserted since the log bit
2124 /// was last cleared. This log bit will remain set until cleared by
2125 /// software writing 0.
2127 UINT32 TurboTransitionAttenuationLog
: 1;
2128 UINT32 Reserved7
: 2;
2129 UINT32 Reserved8
: 32;
2132 /// All bit fields as a 32-bit value
2136 /// All bit fields as a 64-bit value
2139 } MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
;
2142 Package. Uncore C-Box 0, counter 0 event select MSR.
2144 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
2145 @param EAX Lower 32-bits of MSR value.
2146 @param EDX Upper 32-bits of MSR value.
2148 <b>Example usage</b>
2152 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);
2153 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);
2155 @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
2157 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700
2160 Package. Uncore C-Box 0, counter 1 event select MSR.
2162 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
2163 @param EAX Lower 32-bits of MSR value.
2164 @param EDX Upper 32-bits of MSR value.
2166 <b>Example usage</b>
2170 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);
2171 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);
2173 @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
2175 #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701
2178 Package. Uncore C-Box 0, performance counter 0.
2180 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)
2181 @param EAX Lower 32-bits of MSR value.
2182 @param EDX Upper 32-bits of MSR value.
2184 <b>Example usage</b>
2188 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);
2189 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);
2191 @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
2193 #define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706
2196 Package. Uncore C-Box 0, performance counter 1.
2198 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)
2199 @param EAX Lower 32-bits of MSR value.
2200 @param EDX Upper 32-bits of MSR value.
2202 <b>Example usage</b>
2206 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);
2207 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);
2209 @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
2211 #define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707
2214 Package. Uncore C-Box 1, counter 0 event select MSR.
2216 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
2217 @param EAX Lower 32-bits of MSR value.
2218 @param EDX Upper 32-bits of MSR value.
2220 <b>Example usage</b>
2224 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);
2225 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);
2227 @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
2229 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710
2232 Package. Uncore C-Box 1, counter 1 event select MSR.
2234 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
2235 @param EAX Lower 32-bits of MSR value.
2236 @param EDX Upper 32-bits of MSR value.
2238 <b>Example usage</b>
2242 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);
2243 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);
2245 @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
2247 #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711
2250 Package. Uncore C-Box 1, performance counter 0.
2252 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)
2253 @param EAX Lower 32-bits of MSR value.
2254 @param EDX Upper 32-bits of MSR value.
2256 <b>Example usage</b>
2260 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);
2261 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);
2263 @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
2265 #define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716
2268 Package. Uncore C-Box 1, performance counter 1.
2270 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)
2271 @param EAX Lower 32-bits of MSR value.
2272 @param EDX Upper 32-bits of MSR value.
2274 <b>Example usage</b>
2278 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);
2279 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);
2281 @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
2283 #define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717
2286 Package. Uncore C-Box 2, counter 0 event select MSR.
2288 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
2289 @param EAX Lower 32-bits of MSR value.
2290 @param EDX Upper 32-bits of MSR value.
2292 <b>Example usage</b>
2296 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);
2297 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);
2299 @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
2301 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720
2304 Package. Uncore C-Box 2, counter 1 event select MSR.
2306 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
2307 @param EAX Lower 32-bits of MSR value.
2308 @param EDX Upper 32-bits of MSR value.
2310 <b>Example usage</b>
2314 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);
2315 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);
2317 @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
2319 #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721
2322 Package. Uncore C-Box 2, performance counter 0.
2324 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)
2325 @param EAX Lower 32-bits of MSR value.
2326 @param EDX Upper 32-bits of MSR value.
2328 <b>Example usage</b>
2332 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);
2333 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);
2335 @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
2337 #define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726
2340 Package. Uncore C-Box 2, performance counter 1.
2342 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)
2343 @param EAX Lower 32-bits of MSR value.
2344 @param EDX Upper 32-bits of MSR value.
2346 <b>Example usage</b>
2350 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);
2351 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);
2353 @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
2355 #define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727
2358 Package. Uncore C-Box 3, counter 0 event select MSR.
2360 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
2361 @param EAX Lower 32-bits of MSR value.
2362 @param EDX Upper 32-bits of MSR value.
2364 <b>Example usage</b>
2368 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);
2369 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);
2371 @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
2373 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730
2376 Package. Uncore C-Box 3, counter 1 event select MSR.
2378 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
2379 @param EAX Lower 32-bits of MSR value.
2380 @param EDX Upper 32-bits of MSR value.
2382 <b>Example usage</b>
2386 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);
2387 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);
2389 @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
2391 #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731
2394 Package. Uncore C-Box 3, performance counter 0.
2396 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)
2397 @param EAX Lower 32-bits of MSR value.
2398 @param EDX Upper 32-bits of MSR value.
2400 <b>Example usage</b>
2404 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);
2405 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);
2407 @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
2409 #define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736
2412 Package. Uncore C-Box 3, performance counter 1.
2414 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)
2415 @param EAX Lower 32-bits of MSR value.
2416 @param EDX Upper 32-bits of MSR value.
2418 <b>Example usage</b>
2422 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);
2423 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);
2425 @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
2427 #define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737
2430 Package. Note: C-state values are processor specific C-state code names,
2431 unrelated to MWAIT extension C-state parameters or ACPI C-States.
2433 @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)
2434 @param EAX Lower 32-bits of MSR value.
2435 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
2436 @param EDX Upper 32-bits of MSR value.
2437 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
2439 <b>Example usage</b>
2441 MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr;
2443 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);
2444 AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);
2446 @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.
2448 #define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630
2451 MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY
2455 /// Individual bit fields
2459 /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset
2460 /// that this package is in processor-specific C8 states. Count at the
2461 /// same frequency as the TSC.
2463 UINT32 C8ResidencyCounter
: 32;
2465 /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last
2466 /// reset that this package is in processor-specific C8 states. Count at
2467 /// the same frequency as the TSC.
2469 UINT32 C8ResidencyCounterHi
: 28;
2470 UINT32 Reserved
: 4;
2473 /// All bit fields as a 64-bit value
2476 } MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER
;
2479 Package. Note: C-state values are processor specific C-state code names,
2480 unrelated to MWAIT extension C-state parameters or ACPI C-States.
2482 @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)
2483 @param EAX Lower 32-bits of MSR value.
2484 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
2485 @param EDX Upper 32-bits of MSR value.
2486 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
2488 <b>Example usage</b>
2490 MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr;
2492 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);
2493 AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);
2495 @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.
2497 #define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631
2500 MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY
2504 /// Individual bit fields
2508 /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset
2509 /// that this package is in processor-specific C9 states. Count at the
2510 /// same frequency as the TSC.
2512 UINT32 C9ResidencyCounter
: 32;
2514 /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last
2515 /// reset that this package is in processor-specific C9 states. Count at
2516 /// the same frequency as the TSC.
2518 UINT32 C9ResidencyCounterHi
: 28;
2519 UINT32 Reserved
: 4;
2522 /// All bit fields as a 64-bit value
2525 } MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER
;
2528 Package. Note: C-state values are processor specific C-state code names,
2529 unrelated to MWAIT extension C-state parameters or ACPI C-States.
2531 @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)
2532 @param EAX Lower 32-bits of MSR value.
2533 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
2534 @param EDX Upper 32-bits of MSR value.
2535 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
2537 <b>Example usage</b>
2539 MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr;
2541 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);
2542 AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);
2544 @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
2546 #define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632
2549 MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY
2553 /// Individual bit fields
2557 /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last
2558 /// reset that this package is in processor-specific C10 states. Count at
2559 /// the same frequency as the TSC.
2561 UINT32 C10ResidencyCounter
: 32;
2563 /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last
2564 /// reset that this package is in processor-specific C10 states. Count at
2565 /// the same frequency as the TSC.
2567 UINT32 C10ResidencyCounterHi
: 28;
2568 UINT32 Reserved
: 4;
2571 /// All bit fields as a 64-bit value
2574 } MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER
;