MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h

   1 /** @file
   2   MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __IVY_BRIDGE_MSR_H__
  19 #define __IVY_BRIDGE_MSR_H__
  20
  21 #include <Register/Intel/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Intel processors based on the Ivy Bridge microarchitecture?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x06 && \
  34    (                        \
  35     DisplayModel == 0x3A || \
  36     DisplayModel == 0x3E    \
  37     )                       \
  38    )
  39
  40 /**
  41   Package. See http://biosbits.org.
  42
  43   @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)
  44   @param  EAX  Lower 32-bits of MSR value.
  45                Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
  46   @param  EDX  Upper 32-bits of MSR value.
  47                Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
  48
  49   <b>Example usage</b>
  50   @code
  51   MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER  Msr;
  52
  53   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
  54   AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
  55   @endcode
  56   @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
  57 **/
  58 #define MSR_IVY_BRIDGE_PLATFORM_INFO  0x000000CE
  59
  60 /**
  61   MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO
  62 **/
  63 typedef union {
  64   ///
  65   /// Individual bit fields
  66   ///
  67   struct {
  68     UINT32    Reserved1              : 8;
  69     ///
  70     /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
  71     /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
  72     /// MHz.
  73     ///
  74     UINT32    MaximumNonTurboRatio   : 8;
  75     UINT32    Reserved2              : 12;
  76     ///
  77     /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
  78     /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
  79     /// enabled, and when set to 0, indicates Programmable Ratio Limits for
  80     /// Turbo mode is disabled.
  81     ///
  82     UINT32    RatioLimit             : 1;
  83     ///
  84     /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
  85     /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
  86     /// and when set to 0, indicates TDP Limit for Turbo mode is not
  87     /// programmable.
  88     ///
  89     UINT32    TDPLimit               : 1;
  90     UINT32    Reserved3              : 2;
  91     ///
  92     /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O)  When set to 1,
  93     /// indicates that LPM is supported, and when set to 0, indicates LPM is
  94     /// not supported.
  95     ///
  96     UINT32    LowPowerModeSupport    : 1;
  97     ///
  98     /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
  99     /// TDP level available. 01: One additional TDP level available. 02: Two
 100     /// additional TDP level available. 11: Reserved.
 101     ///
 102     UINT32    ConfigTDPLevels        : 2;
 103     UINT32    Reserved4              : 5;
 104     ///
 105     /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
 106     /// minimum ratio (maximum efficiency) that the processor can operates, in
 107     /// units of 100MHz.
 108     ///
 109     UINT32    MaximumEfficiencyRatio : 8;
 110     ///
 111     /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
 112     /// minimum supported operating ratio in units of 100 MHz.
 113     ///
 114     UINT32    MinimumOperatingRatio  : 8;
 115     UINT32    Reserved5              : 8;
 116   } Bits;
 117   ///
 118   /// All bit fields as a 64-bit value
 119   ///
 120   UINT64    Uint64;
 121 } MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;
 122
 123 /**
 124   Core. C-State Configuration Control (R/W)  Note: C-state values are
 125   processor specific C-state code names, unrelated to MWAIT extension C-state
 126   parameters or ACPI C-States. See http://biosbits.org.
 127
 128   @param  ECX  MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
 129   @param  EAX  Lower 32-bits of MSR value.
 130                Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
 131   @param  EDX  Upper 32-bits of MSR value.
 132                Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
 133
 134   <b>Example usage</b>
 135   @code
 136   MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
 137
 138   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);
 139   AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
 140   @endcode
 141   @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 142 **/
 143 #define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL  0x000000E2
 144
 145 /**
 146   MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL
 147 **/
 148 typedef union {
 149   ///
 150   /// Individual bit fields
 151   ///
 152   struct {
 153     ///
 154     /// [Bits 2:0] Package C-State Limit (R/W)  Specifies the lowest
 155     /// processor-specific C-state code name (consuming the least power). for
 156     /// the package. The default is set as factory-configured package C-state
 157     /// limit. The following C-state code name encodings are supported: 000b:
 158     /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
 159     /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
 160     /// This field cannot be used to limit package C-state to C3.
 161     ///
 162     UINT32    Limit          : 3;
 163     UINT32    Reserved1      : 7;
 164     ///
 165     /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
 166     /// IO_read instructions sent to IO register specified by
 167     /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
 168     ///
 169     UINT32    IO_MWAIT       : 1;
 170     UINT32    Reserved2      : 4;
 171     ///
 172     /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
 173     /// until next reset.
 174     ///
 175     UINT32    CFGLock        : 1;
 176     UINT32    Reserved3      : 9;
 177     ///
 178     /// [Bit 25] C3 state auto demotion enable (R/W)  When set, the processor
 179     /// will conditionally demote C6/C7 requests to C3 based on uncore
 180     /// auto-demote information.
 181     ///
 182     UINT32    C3AutoDemotion : 1;
 183     ///
 184     /// [Bit 26] C1 state auto demotion enable (R/W)  When set, the processor
 185     /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
 186     /// auto-demote information.
 187     ///
 188     UINT32    C1AutoDemotion : 1;
 189     ///
 190     /// [Bit 27] Enable C3 undemotion (R/W)  When set, enables undemotion from
 191     /// demoted C3.
 192     ///
 193     UINT32    C3Undemotion   : 1;
 194     ///
 195     /// [Bit 28] Enable C1 undemotion (R/W)  When set, enables undemotion from
 196     /// demoted C1.
 197     ///
 198     UINT32    C1Undemotion   : 1;
 199     UINT32    Reserved4      : 3;
 200     UINT32    Reserved5      : 32;
 201   } Bits;
 202   ///
 203   /// All bit fields as a 32-bit value
 204   ///
 205   UINT32    Uint32;
 206   ///
 207   /// All bit fields as a 64-bit value
 208   ///
 209   UINT64    Uint64;
 210 } MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;
 211
 212 /**
 213   Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
 214   Domains.".
 215
 216   @param  ECX  MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
 217   @param  EAX  Lower 32-bits of MSR value.
 218   @param  EDX  Upper 32-bits of MSR value.
 219
 220   <b>Example usage</b>
 221   @code
 222   UINT64  Msr;
 223
 224   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);
 225   @endcode
 226   @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
 227 **/
 228 #define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS  0x00000639
 229
 230 /**
 231   Package. Base TDP Ratio (R/O).
 232
 233   @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)
 234   @param  EAX  Lower 32-bits of MSR value.
 235                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
 236   @param  EDX  Upper 32-bits of MSR value.
 237                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
 238
 239   <b>Example usage</b>
 240   @code
 241   MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER  Msr;
 242
 243   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);
 244   @endcode
 245   @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
 246 **/
 247 #define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL  0x00000648
 248
 249 /**
 250   MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL
 251 **/
 252 typedef union {
 253   ///
 254   /// Individual bit fields
 255   ///
 256   struct {
 257     ///
 258     /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
 259     /// specific processor (in units of 100 MHz).
 260     ///
 261     UINT32    Config_TDP_Base : 8;
 262     UINT32    Reserved1       : 24;
 263     UINT32    Reserved2       : 32;
 264   } Bits;
 265   ///
 266   /// All bit fields as a 32-bit value
 267   ///
 268   UINT32    Uint32;
 269   ///
 270   /// All bit fields as a 64-bit value
 271   ///
 272   UINT64    Uint64;
 273 } MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;
 274
 275 /**
 276   Package. ConfigTDP Level 1 ratio and power level (R/O).
 277
 278   @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)
 279   @param  EAX  Lower 32-bits of MSR value.
 280                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
 281   @param  EDX  Upper 32-bits of MSR value.
 282                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
 283
 284   <b>Example usage</b>
 285   @code
 286   MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER  Msr;
 287
 288   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);
 289   @endcode
 290   @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
 291 **/
 292 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1  0x00000649
 293
 294 /**
 295   MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1
 296 **/
 297 typedef union {
 298   ///
 299   /// Individual bit fields
 300   ///
 301   struct {
 302     ///
 303     /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
 304     ///
 305     UINT32    PKG_TDP_LVL1          : 15;
 306     UINT32    Reserved1             : 1;
 307     ///
 308     /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
 309     /// for this specific processor.
 310     ///
 311     UINT32    Config_TDP_LVL1_Ratio : 8;
 312     UINT32    Reserved2             : 8;
 313     ///
 314     /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
 315     /// Level 1.
 316     ///
 317     UINT32    PKG_MAX_PWR_LVL1      : 15;
 318     UINT32    Reserved3             : 1;
 319     ///
 320     /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
 321     /// Level 1.
 322     ///
 323     UINT32    PKG_MIN_PWR_LVL1      : 15;
 324     UINT32    Reserved4             : 1;
 325   } Bits;
 326   ///
 327   /// All bit fields as a 64-bit value
 328   ///
 329   UINT64    Uint64;
 330 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;
 331
 332 /**
 333   Package. ConfigTDP Level 2 ratio and power level (R/O).
 334
 335   @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)
 336   @param  EAX  Lower 32-bits of MSR value.
 337                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
 338   @param  EDX  Upper 32-bits of MSR value.
 339                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
 340
 341   <b>Example usage</b>
 342   @code
 343   MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER  Msr;
 344
 345   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);
 346   @endcode
 347   @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
 348 **/
 349 #define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2  0x0000064A
 350
 351 /**
 352   MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2
 353 **/
 354 typedef union {
 355   ///
 356   /// Individual bit fields
 357   ///
 358   struct {
 359     ///
 360     /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
 361     ///
 362     UINT32    PKG_TDP_LVL2          : 15;
 363     UINT32    Reserved1             : 1;
 364     ///
 365     /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
 366     /// for this specific processor.
 367     ///
 368     UINT32    Config_TDP_LVL2_Ratio : 8;
 369     UINT32    Reserved2             : 8;
 370     ///
 371     /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
 372     /// Level 2.
 373     ///
 374     UINT32    PKG_MAX_PWR_LVL2      : 15;
 375     UINT32    Reserved3             : 1;
 376     ///
 377     /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
 378     /// Level 2.
 379     ///
 380     UINT32    PKG_MIN_PWR_LVL2      : 15;
 381     UINT32    Reserved4             : 1;
 382   } Bits;
 383   ///
 384   /// All bit fields as a 64-bit value
 385   ///
 386   UINT64    Uint64;
 387 } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;
 388
 389 /**
 390   Package. ConfigTDP Control (R/W).
 391
 392   @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)
 393   @param  EAX  Lower 32-bits of MSR value.
 394                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
 395   @param  EDX  Upper 32-bits of MSR value.
 396                Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
 397
 398   <b>Example usage</b>
 399   @code
 400   MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER  Msr;
 401
 402   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);
 403   AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);
 404   @endcode
 405   @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
 406 **/
 407 #define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL  0x0000064B
 408
 409 /**
 410   MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL
 411 **/
 412 typedef union {
 413   ///
 414   /// Individual bit fields
 415   ///
 416   struct {
 417     ///
 418     /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
 419     ///
 420     UINT32    TDP_LEVEL       : 2;
 421     UINT32    Reserved1       : 29;
 422     ///
 423     /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
 424     /// this register is locked until a reset.
 425     ///
 426     UINT32    Config_TDP_Lock : 1;
 427     UINT32    Reserved2       : 32;
 428   } Bits;
 429   ///
 430   /// All bit fields as a 32-bit value
 431   ///
 432   UINT32    Uint32;
 433   ///
 434   /// All bit fields as a 64-bit value
 435   ///
 436   UINT64    Uint64;
 437 } MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;
 438
 439 /**
 440   Package. ConfigTDP Control (R/W).
 441
 442   @param  ECX  MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)
 443   @param  EAX  Lower 32-bits of MSR value.
 444                Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
 445   @param  EDX  Upper 32-bits of MSR value.
 446                Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
 447
 448   <b>Example usage</b>
 449   @code
 450   MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER  Msr;
 451
 452   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);
 453   AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);
 454   @endcode
 455   @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
 456 **/
 457 #define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO  0x0000064C
 458
 459 /**
 460   MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO
 461 **/
 462 typedef union {
 463   ///
 464   /// Individual bit fields
 465   ///
 466   struct {
 467     ///
 468     /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
 469     /// field.
 470     ///
 471     UINT32    MAX_NON_TURBO_RATIO         : 8;
 472     UINT32    Reserved1                   : 23;
 473     ///
 474     /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
 475     /// content of this register is locked until a reset.
 476     ///
 477     UINT32    TURBO_ACTIVATION_RATIO_Lock : 1;
 478     UINT32    Reserved2                   : 32;
 479   } Bits;
 480   ///
 481   /// All bit fields as a 32-bit value
 482   ///
 483   UINT32    Uint32;
 484   ///
 485   /// All bit fields as a 64-bit value
 486   ///
 487   UINT64    Uint64;
 488 } MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;
 489
 490 /**
 491   Package. Protected Processor Inventory Number Enable Control (R/W).
 492
 493   @param  ECX  MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)
 494   @param  EAX  Lower 32-bits of MSR value.
 495                Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
 496   @param  EDX  Upper 32-bits of MSR value.
 497                Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
 498
 499   <b>Example usage</b>
 500   @code
 501   MSR_IVY_BRIDGE_PPIN_CTL_REGISTER  Msr;
 502
 503   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
 504   AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);
 505   @endcode
 506   @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
 507 **/
 508 #define MSR_IVY_BRIDGE_PPIN_CTL  0x0000004E
 509
 510 /**
 511   MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL
 512 **/
 513 typedef union {
 514   ///
 515   /// Individual bit fields
 516   ///
 517   struct {
 518     ///
 519     /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.
 520     /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit
 521     /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to
 522     /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged
 523     /// inventory initialization agent to access MSR_PPIN. After reading
 524     /// MSR_PPIN, the privileged inventory initialization agent should write
 525     /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
 526     /// prevent unauthorized modification to MSR_PPIN_CTL.
 527     ///
 528     UINT32    LockOut     : 1;
 529     ///
 530     /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
 531     /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will
 532     /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default
 533     /// is 0.
 534     ///
 535     UINT32    Enable_PPIN : 1;
 536     UINT32    Reserved1   : 30;
 537     UINT32    Reserved2   : 32;
 538   } Bits;
 539   ///
 540   /// All bit fields as a 32-bit value
 541   ///
 542   UINT32    Uint32;
 543   ///
 544   /// All bit fields as a 64-bit value
 545   ///
 546   UINT64    Uint64;
 547 } MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;
 548
 549 /**
 550   Package. Protected Processor Inventory Number (R/O). Protected Processor
 551   Inventory Number (R/O) A unique value within a given CPUID
 552   family/model/stepping signature that a privileged inventory initialization
 553   agent can access to identify each physical processor, when access to
 554   MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
 555   MSR_PPIN_CTL[bits 1:0] = '10b'.
 556
 557   @param  ECX  MSR_IVY_BRIDGE_PPIN (0x0000004F)
 558   @param  EAX  Lower 32-bits of MSR value.
 559   @param  EDX  Upper 32-bits of MSR value.
 560
 561   <b>Example usage</b>
 562   @code
 563   UINT64  Msr;
 564
 565   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);
 566   @endcode
 567   @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.
 568 **/
 569 #define MSR_IVY_BRIDGE_PPIN  0x0000004F
 570
 571 /**
 572   Package. See http://biosbits.org.
 573
 574   @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)
 575   @param  EAX  Lower 32-bits of MSR value.
 576                Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
 577   @param  EDX  Upper 32-bits of MSR value.
 578                Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
 579
 580   <b>Example usage</b>
 581   @code
 582   MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER  Msr;
 583
 584   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
 585   AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);
 586   @endcode
 587   @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.
 588 **/
 589 #define MSR_IVY_BRIDGE_PLATFORM_INFO_1  0x000000CE
 590
 591 /**
 592   MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1
 593 **/
 594 typedef union {
 595   ///
 596   /// Individual bit fields
 597   ///
 598   struct {
 599     UINT32    Reserved1              : 8;
 600     ///
 601     /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
 602     /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
 603     /// MHz.
 604     ///
 605     UINT32    MaximumNonTurboRatio   : 8;
 606     UINT32    Reserved2              : 7;
 607     ///
 608     /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that
 609     /// Protected Processor Inventory Number (PPIN) capability can be enabled
 610     /// for privileged system inventory agent to read PPIN from MSR_PPIN. When
 611     /// set to 0, PPIN capability is not supported. An attempt to access
 612     /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.
 613     ///
 614     UINT32    PPIN_CAP               : 1;
 615     UINT32    Reserved3              : 4;
 616     ///
 617     /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
 618     /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
 619     /// enabled, and when set to 0, indicates Programmable Ratio Limits for
 620     /// Turbo mode is disabled.
 621     ///
 622     UINT32    RatioLimit             : 1;
 623     ///
 624     /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
 625     /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
 626     /// and when set to 0, indicates TDP Limit for Turbo mode is not
 627     /// programmable.
 628     ///
 629     UINT32    TDPLimit               : 1;
 630     ///
 631     /// [Bit 30] Package. Programmable TJ OFFSET (R/O)  When set to 1,
 632     /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
 633     /// specify an temperature offset.
 634     ///
 635     UINT32    TJOFFSET               : 1;
 636     UINT32    Reserved4              : 1;
 637     UINT32    Reserved5              : 8;
 638     ///
 639     /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
 640     /// minimum ratio (maximum efficiency) that the processor can operates, in
 641     /// units of 100MHz.
 642     ///
 643     UINT32    MaximumEfficiencyRatio : 8;
 644     UINT32    Reserved6              : 16;
 645   } Bits;
 646   ///
 647   /// All bit fields as a 64-bit value
 648   ///
 649   UINT64    Uint64;
 650 } MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;
 651
 652 /**
 653   Package. MC Bank Error Configuration (R/W).
 654
 655   @param  ECX  MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)
 656   @param  EAX  Lower 32-bits of MSR value.
 657                Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
 658   @param  EDX  Upper 32-bits of MSR value.
 659                Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
 660
 661   <b>Example usage</b>
 662   @code
 663   MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER  Msr;
 664
 665   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);
 666   AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
 667   @endcode
 668   @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
 669 **/
 670 #define MSR_IVY_BRIDGE_ERROR_CONTROL  0x0000017F
 671
 672 /**
 673   MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL
 674 **/
 675 typedef union {
 676   ///
 677   /// Individual bit fields
 678   ///
 679   struct {
 680     UINT32    Reserved1         : 1;
 681     ///
 682     /// [Bit 1] MemError Log Enable (R/W)  When set, enables IMC status bank
 683     /// to log additional info in bits 36:32.
 684     ///
 685     UINT32    MemErrorLogEnable : 1;
 686     UINT32    Reserved2         : 30;
 687     UINT32    Reserved3         : 32;
 688   } Bits;
 689   ///
 690   /// All bit fields as a 32-bit value
 691   ///
 692   UINT32    Uint32;
 693   ///
 694   /// All bit fields as a 64-bit value
 695   ///
 696   UINT64    Uint64;
 697 } MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;
 698
 699 /**
 700   Package.
 701
 702   @param  ECX  MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
 703   @param  EAX  Lower 32-bits of MSR value.
 704                Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
 705   @param  EDX  Upper 32-bits of MSR value.
 706                Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
 707
 708   <b>Example usage</b>
 709   @code
 710   MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER  Msr;
 711
 712   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);
 713   AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
 714   @endcode
 715   @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
 716 **/
 717 #define MSR_IVY_BRIDGE_TEMPERATURE_TARGET  0x000001A2
 718
 719 /**
 720   MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET
 721 **/
 722 typedef union {
 723   ///
 724   /// Individual bit fields
 725   ///
 726   struct {
 727     UINT32    Reserved1           : 16;
 728     ///
 729     /// [Bits 23:16] Temperature Target (RO)  The minimum temperature at which
 730     /// PROCHOT# will be asserted. The value is degree C.
 731     ///
 732     UINT32    TemperatureTarget   : 8;
 733     ///
 734     /// [Bits 27:24] TCC Activation Offset (R/W)  Specifies a temperature
 735     /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#
 736     /// will assert at the offset target temperature. Write is permitted only
 737     /// MSR_PLATFORM_INFO.[30] is set.
 738     ///
 739     UINT32    TCCActivationOffset : 4;
 740     UINT32    Reserved2           : 4;
 741     UINT32    Reserved3           : 32;
 742   } Bits;
 743   ///
 744   /// All bit fields as a 32-bit value
 745   ///
 746   UINT32    Uint32;
 747   ///
 748   /// All bit fields as a 64-bit value
 749   ///
 750   UINT64    Uint64;
 751 } MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;
 752
 753 /**
 754   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 755   RW if MSR_PLATFORM_INFO.[28] = 1.
 756
 757   @param  ECX  MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)
 758   @param  EAX  Lower 32-bits of MSR value.
 759                Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
 760   @param  EDX  Upper 32-bits of MSR value.
 761                Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
 762
 763   <b>Example usage</b>
 764   @code
 765   MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER  Msr;
 766
 767   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);
 768   @endcode
 769   @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
 770 **/
 771 #define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1  0x000001AE
 772
 773 /**
 774   MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1
 775 **/
 776 typedef union {
 777   ///
 778   /// Individual bit fields
 779   ///
 780   struct {
 781     ///
 782     /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
 783     /// limit of 9 core active.
 784     ///
 785     UINT32    Maximum9C                             : 8;
 786     ///
 787     /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
 788     /// limit of 10core active.
 789     ///
 790     UINT32    Maximum10C                            : 8;
 791     ///
 792     /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
 793     /// limit of 11 core active.
 794     ///
 795     UINT32    Maximum11C                            : 8;
 796     ///
 797     /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
 798     /// limit of 12 core active.
 799     ///
 800     UINT32    Maximum12C                            : 8;
 801     ///
 802     /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
 803     /// limit of 13 core active.
 804     ///
 805     UINT32    Maximum13C                            : 8;
 806     ///
 807     /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
 808     /// limit of 14 core active.
 809     ///
 810     UINT32    Maximum14C                            : 8;
 811     ///
 812     /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
 813     /// limit of 15 core active.
 814     ///
 815     UINT32    Maximum15C                            : 8;
 816     UINT32    Reserved                              : 7;
 817     ///
 818     /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
 819     /// the processor uses override configuration specified in
 820     /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor
 821     /// uses factory-set configuration (Default).
 822     ///
 823     UINT32    TurboRatioLimitConfigurationSemaphore : 1;
 824   } Bits;
 825   ///
 826   /// All bit fields as a 64-bit value
 827   ///
 828   UINT64    Uint64;
 829 } MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;
 830
 831 /**
 832   Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.
 833
 834   @param  ECX  MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)
 835   @param  EAX  Lower 32-bits of MSR value.
 836                Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
 837   @param  EDX  Upper 32-bits of MSR value.
 838                Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
 839
 840   <b>Example usage</b>
 841   @code
 842   MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER  Msr;
 843
 844   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);
 845   @endcode
 846   @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
 847 **/
 848 #define MSR_IVY_BRIDGE_IA32_MC6_MISC  0x0000041B
 849
 850 /**
 851   MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC
 852 **/
 853 typedef union {
 854   ///
 855   /// Individual bit fields
 856   ///
 857   struct {
 858     ///
 859     /// [Bits 5:0] Recoverable Address LSB.
 860     ///
 861     UINT32    RecoverableAddressLSB   : 6;
 862     ///
 863     /// [Bits 8:6] Address Mode.
 864     ///
 865     UINT32    AddressMode             : 3;
 866     UINT32    Reserved1               : 7;
 867     ///
 868     /// [Bits 31:16] PCI Express Requestor ID.
 869     ///
 870     UINT32    PCIExpressRequestorID   : 16;
 871     ///
 872     /// [Bits 39:32] PCI Express Segment Number.
 873     ///
 874     UINT32    PCIExpressSegmentNumber : 8;
 875     UINT32    Reserved2               : 24;
 876   } Bits;
 877   ///
 878   /// All bit fields as a 64-bit value
 879   ///
 880   UINT64    Uint64;
 881 } MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;
 882
 883 /**
 884   Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
 885   15.3.2.4, "IA32_MCi_MISC MSRs.".
 886
 887   Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
 888   and its corresponding slice of L3.
 889
 890   @param  ECX  MSR_IVY_BRIDGE_IA32_MCi_CTL
 891   @param  EAX  Lower 32-bits of MSR value.
 892   @param  EDX  Upper 32-bits of MSR value.
 893
 894   <b>Example usage</b>
 895   @code
 896   UINT64  Msr;
 897
 898   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);
 899   AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);
 900   @endcode
 901   @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM.
 902         MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM.
 903         MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.
 904   @{
 905 **/
 906 #define MSR_IVY_BRIDGE_IA32_MC29_CTL  0x00000474
 907 #define MSR_IVY_BRIDGE_IA32_MC30_CTL  0x00000478
 908 #define MSR_IVY_BRIDGE_IA32_MC31_CTL  0x0000047C
 909 /// @}
 910
 911 /**
 912   Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
 913   15.3.2.4, "IA32_MCi_MISC MSRs.".
 914
 915   Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
 916   and its corresponding slice of L3.
 917
 918   @param  ECX  MSR_IVY_BRIDGE_IA32_MCi_STATUS
 919   @param  EAX  Lower 32-bits of MSR value.
 920   @param  EDX  Upper 32-bits of MSR value.
 921
 922   <b>Example usage</b>
 923   @code
 924   UINT64  Msr;
 925
 926   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);
 927   AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);
 928   @endcode
 929   @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM.
 930         MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM.
 931         MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.
 932   @{
 933 **/
 934 #define MSR_IVY_BRIDGE_IA32_MC29_STATUS  0x00000475
 935 #define MSR_IVY_BRIDGE_IA32_MC30_STATUS  0x00000479
 936 #define MSR_IVY_BRIDGE_IA32_MC31_STATUS  0x0000047D
 937 /// @}
 938
 939 /**
 940   Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
 941   15.3.2.4, "IA32_MCi_MISC MSRs.".
 942
 943   Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
 944   and its corresponding slice of L3.
 945
 946   @param  ECX  MSR_IVY_BRIDGE_IA32_MCi_ADDR
 947   @param  EAX  Lower 32-bits of MSR value.
 948   @param  EDX  Upper 32-bits of MSR value.
 949
 950   <b>Example usage</b>
 951   @code
 952   UINT64  Msr;
 953
 954   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);
 955   AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);
 956   @endcode
 957   @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM.
 958         MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM.
 959         MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.
 960   @{
 961 **/
 962 #define MSR_IVY_BRIDGE_IA32_MC29_ADDR  0x00000476
 963 #define MSR_IVY_BRIDGE_IA32_MC30_ADDR  0x0000047A
 964 #define MSR_IVY_BRIDGE_IA32_MC31_ADDR  0x0000047E
 965 /// @}
 966
 967 /**
 968   Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
 969   15.3.2.4, "IA32_MCi_MISC MSRs.".
 970
 971   Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
 972   and its corresponding slice of L3.
 973
 974   @param  ECX  MSR_IVY_BRIDGE_IA32_MCi_MISC
 975   @param  EAX  Lower 32-bits of MSR value.
 976   @param  EDX  Upper 32-bits of MSR value.
 977
 978   <b>Example usage</b>
 979   @code
 980   UINT64  Msr;
 981
 982   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);
 983   AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);
 984   @endcode
 985   @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM.
 986         MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM.
 987         MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.
 988   @{
 989 **/
 990 #define MSR_IVY_BRIDGE_IA32_MC29_MISC  0x00000477
 991 #define MSR_IVY_BRIDGE_IA32_MC30_MISC  0x0000047B
 992 #define MSR_IVY_BRIDGE_IA32_MC31_MISC  0x0000047F
 993 /// @}
 994
 995 /**
 996   Package. Package RAPL Perf Status (R/O).
 997
 998   @param  ECX  MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)
 999   @param  EAX  Lower 32-bits of MSR value.
1000   @param  EDX  Upper 32-bits of MSR value.
1001
1002   <b>Example usage</b>
1003   @code
1004   UINT64  Msr;
1005
1006   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);
1007   @endcode
1008   @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
1009 **/
1010 #define MSR_IVY_BRIDGE_PKG_PERF_STATUS  0x00000613
1011
1012 /**
1013   Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
1014   Domain.".
1015
1016   @param  ECX  MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
1017   @param  EAX  Lower 32-bits of MSR value.
1018   @param  EDX  Upper 32-bits of MSR value.
1019
1020   <b>Example usage</b>
1021   @code
1022   UINT64  Msr;
1023
1024   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);
1025   AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);
1026   @endcode
1027   @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
1028 **/
1029 #define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT  0x00000618
1030
1031 /**
1032   Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".
1033
1034   @param  ECX  MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
1035   @param  EAX  Lower 32-bits of MSR value.
1036   @param  EDX  Upper 32-bits of MSR value.
1037
1038   <b>Example usage</b>
1039   @code
1040   UINT64  Msr;
1041
1042   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);
1043   @endcode
1044   @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
1045 **/
1046 #define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS  0x00000619
1047
1048 /**
1049   Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1050   RAPL Domain.".
1051
1052   @param  ECX  MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
1053   @param  EAX  Lower 32-bits of MSR value.
1054   @param  EDX  Upper 32-bits of MSR value.
1055
1056   <b>Example usage</b>
1057   @code
1058   UINT64  Msr;
1059
1060   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);
1061   @endcode
1062   @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
1063 **/
1064 #define MSR_IVY_BRIDGE_DRAM_PERF_STATUS  0x0000061B
1065
1066 /**
1067   Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1068
1069   @param  ECX  MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
1070   @param  EAX  Lower 32-bits of MSR value.
1071   @param  EDX  Upper 32-bits of MSR value.
1072
1073   <b>Example usage</b>
1074   @code
1075   UINT64  Msr;
1076
1077   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);
1078   AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);
1079   @endcode
1080   @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
1081 **/
1082 #define MSR_IVY_BRIDGE_DRAM_POWER_INFO  0x0000061C
1083
1084 /**
1085   Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
1086
1087   @param  ECX  MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
1088   @param  EAX  Lower 32-bits of MSR value.
1089                Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
1090   @param  EDX  Upper 32-bits of MSR value.
1091                Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
1092
1093   <b>Example usage</b>
1094   @code
1095   MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER  Msr;
1096
1097   Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);
1098   AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
1099   @endcode
1100   @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1101 **/
1102 #define MSR_IVY_BRIDGE_PEBS_ENABLE  0x000003F1
1103
1104 /**
1105   MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE
1106 **/
1107 typedef union {
1108   ///
1109   /// Individual bit fields
1110   ///
1111   struct {
1112     ///
1113     /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1114     ///
1115     UINT32    PEBS_EN_PMC0 : 1;
1116     ///
1117     /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1118     ///
1119     UINT32    PEBS_EN_PMC1 : 1;
1120     ///
1121     /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1122     ///
1123     UINT32    PEBS_EN_PMC2 : 1;
1124     ///
1125     /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1126     ///
1127     UINT32    PEBS_EN_PMC3 : 1;
1128     UINT32    Reserved1    : 28;
1129     ///
1130     /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1131     ///
1132     UINT32    LL_EN_PMC0   : 1;
1133     ///
1134     /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1135     ///
1136     UINT32    LL_EN_PMC1   : 1;
1137     ///
1138     /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1139     ///
1140     UINT32    LL_EN_PMC2   : 1;
1141     ///
1142     /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1143     ///
1144     UINT32    LL_EN_PMC3   : 1;
1145     UINT32    Reserved2    : 28;
1146   } Bits;
1147   ///
1148   /// All bit fields as a 64-bit value
1149   ///
1150   UINT64    Uint64;
1151 } MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;
1152
1153 /**
1154   Package. Uncore perfmon per-socket global control.
1155
1156   @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)
1157   @param  EAX  Lower 32-bits of MSR value.
1158   @param  EDX  Upper 32-bits of MSR value.
1159
1160   <b>Example usage</b>
1161   @code
1162   UINT64  Msr;
1163
1164   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);
1165   AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);
1166   @endcode
1167   @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
1168 **/
1169 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL  0x00000C00
1170
1171 /**
1172   Package. Uncore perfmon per-socket global status.
1173
1174   @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)
1175   @param  EAX  Lower 32-bits of MSR value.
1176   @param  EDX  Upper 32-bits of MSR value.
1177
1178   <b>Example usage</b>
1179   @code
1180   UINT64  Msr;
1181
1182   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);
1183   AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);
1184   @endcode
1185   @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
1186 **/
1187 #define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS  0x00000C01
1188
1189 /**
1190   Package. Uncore perfmon per-socket global configuration.
1191
1192   @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)
1193   @param  EAX  Lower 32-bits of MSR value.
1194   @param  EDX  Upper 32-bits of MSR value.
1195
1196   <b>Example usage</b>
1197   @code
1198   UINT64  Msr;
1199
1200   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);
1201   AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);
1202   @endcode
1203   @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
1204 **/
1205 #define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG  0x00000C06
1206
1207 /**
1208   Package. Uncore U-box perfmon U-box wide status.
1209
1210   @param  ECX  MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)
1211   @param  EAX  Lower 32-bits of MSR value.
1212   @param  EDX  Upper 32-bits of MSR value.
1213
1214   <b>Example usage</b>
1215   @code
1216   UINT64  Msr;
1217
1218   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);
1219   AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);
1220   @endcode
1221   @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
1222 **/
1223 #define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS  0x00000C15
1224
1225 /**
1226   Package. Uncore PCU perfmon box wide status.
1227
1228   @param  ECX  MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)
1229   @param  EAX  Lower 32-bits of MSR value.
1230   @param  EDX  Upper 32-bits of MSR value.
1231
1232   <b>Example usage</b>
1233   @code
1234   UINT64  Msr;
1235
1236   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);
1237   AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);
1238   @endcode
1239   @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
1240 **/
1241 #define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS  0x00000C35
1242
1243 /**
1244   Package. Uncore C-box 0 perfmon box wide filter1.
1245
1246   @param  ECX  MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)
1247   @param  EAX  Lower 32-bits of MSR value.
1248   @param  EDX  Upper 32-bits of MSR value.
1249
1250   <b>Example usage</b>
1251   @code
1252   UINT64  Msr;
1253
1254   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);
1255   AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);
1256   @endcode
1257   @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
1258 **/
1259 #define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1  0x00000D1A
1260
1261 /**
1262   Package. Uncore C-box 1 perfmon box wide filter1.
1263
1264   @param  ECX  MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)
1265   @param  EAX  Lower 32-bits of MSR value.
1266   @param  EDX  Upper 32-bits of MSR value.
1267
1268   <b>Example usage</b>
1269   @code
1270   UINT64  Msr;
1271
1272   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);
1273   AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);
1274   @endcode
1275   @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
1276 **/
1277 #define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1  0x00000D3A
1278
1279 /**
1280   Package. Uncore C-box 2 perfmon box wide filter1.
1281
1282   @param  ECX  MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)
1283   @param  EAX  Lower 32-bits of MSR value.
1284   @param  EDX  Upper 32-bits of MSR value.
1285
1286   <b>Example usage</b>
1287   @code
1288   UINT64  Msr;
1289
1290   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);
1291   AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);
1292   @endcode
1293   @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
1294 **/
1295 #define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1  0x00000D5A
1296
1297 /**
1298   Package. Uncore C-box 3 perfmon box wide filter1.
1299
1300   @param  ECX  MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)
1301   @param  EAX  Lower 32-bits of MSR value.
1302   @param  EDX  Upper 32-bits of MSR value.
1303
1304   <b>Example usage</b>
1305   @code
1306   UINT64  Msr;
1307
1308   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);
1309   AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);
1310   @endcode
1311   @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
1312 **/
1313 #define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1  0x00000D7A
1314
1315 /**
1316   Package. Uncore C-box 4 perfmon box wide filter1.
1317
1318   @param  ECX  MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)
1319   @param  EAX  Lower 32-bits of MSR value.
1320   @param  EDX  Upper 32-bits of MSR value.
1321
1322   <b>Example usage</b>
1323   @code
1324   UINT64  Msr;
1325
1326   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);
1327   AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);
1328   @endcode
1329   @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
1330 **/
1331 #define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1  0x00000D9A
1332
1333 /**
1334   Package. Uncore C-box 5 perfmon box wide filter1.
1335
1336   @param  ECX  MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)
1337   @param  EAX  Lower 32-bits of MSR value.
1338   @param  EDX  Upper 32-bits of MSR value.
1339
1340   <b>Example usage</b>
1341   @code
1342   UINT64  Msr;
1343
1344   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);
1345   AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);
1346   @endcode
1347   @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
1348 **/
1349 #define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1  0x00000DBA
1350
1351 /**
1352   Package. Uncore C-box 6 perfmon box wide filter1.
1353
1354   @param  ECX  MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)
1355   @param  EAX  Lower 32-bits of MSR value.
1356   @param  EDX  Upper 32-bits of MSR value.
1357
1358   <b>Example usage</b>
1359   @code
1360   UINT64  Msr;
1361
1362   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);
1363   AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);
1364   @endcode
1365   @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
1366 **/
1367 #define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1  0x00000DDA
1368
1369 /**
1370   Package. Uncore C-box 7 perfmon box wide filter1.
1371
1372   @param  ECX  MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)
1373   @param  EAX  Lower 32-bits of MSR value.
1374   @param  EDX  Upper 32-bits of MSR value.
1375
1376   <b>Example usage</b>
1377   @code
1378   UINT64  Msr;
1379
1380   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);
1381   AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);
1382   @endcode
1383   @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
1384 **/
1385 #define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1  0x00000DFA
1386
1387 /**
1388   Package. Uncore C-box 8 perfmon local box wide control.
1389
1390   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)
1391   @param  EAX  Lower 32-bits of MSR value.
1392   @param  EDX  Upper 32-bits of MSR value.
1393
1394   <b>Example usage</b>
1395   @code
1396   UINT64  Msr;
1397
1398   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);
1399   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);
1400   @endcode
1401   @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
1402 **/
1403 #define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL  0x00000E04
1404
1405 /**
1406   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
1407
1408   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)
1409   @param  EAX  Lower 32-bits of MSR value.
1410   @param  EDX  Upper 32-bits of MSR value.
1411
1412   <b>Example usage</b>
1413   @code
1414   UINT64  Msr;
1415
1416   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);
1417   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);
1418   @endcode
1419   @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
1420 **/
1421 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0  0x00000E10
1422
1423 /**
1424   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
1425
1426   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)
1427   @param  EAX  Lower 32-bits of MSR value.
1428   @param  EDX  Upper 32-bits of MSR value.
1429
1430   <b>Example usage</b>
1431   @code
1432   UINT64  Msr;
1433
1434   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);
1435   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);
1436   @endcode
1437   @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
1438 **/
1439 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1  0x00000E11
1440
1441 /**
1442   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
1443
1444   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)
1445   @param  EAX  Lower 32-bits of MSR value.
1446   @param  EDX  Upper 32-bits of MSR value.
1447
1448   <b>Example usage</b>
1449   @code
1450   UINT64  Msr;
1451
1452   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);
1453   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);
1454   @endcode
1455   @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
1456 **/
1457 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2  0x00000E12
1458
1459 /**
1460   Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
1461
1462   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)
1463   @param  EAX  Lower 32-bits of MSR value.
1464   @param  EDX  Upper 32-bits of MSR value.
1465
1466   <b>Example usage</b>
1467   @code
1468   UINT64  Msr;
1469
1470   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);
1471   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);
1472   @endcode
1473   @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
1474 **/
1475 #define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3  0x00000E13
1476
1477 /**
1478   Package. Uncore C-box 8 perfmon box wide filter.
1479
1480   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)
1481   @param  EAX  Lower 32-bits of MSR value.
1482   @param  EDX  Upper 32-bits of MSR value.
1483
1484   <b>Example usage</b>
1485   @code
1486   UINT64  Msr;
1487
1488   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);
1489   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);
1490   @endcode
1491   @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.
1492 **/
1493 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER  0x00000E14
1494
1495 /**
1496   Package. Uncore C-box 8 perfmon counter 0.
1497
1498   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)
1499   @param  EAX  Lower 32-bits of MSR value.
1500   @param  EDX  Upper 32-bits of MSR value.
1501
1502   <b>Example usage</b>
1503   @code
1504   UINT64  Msr;
1505
1506   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);
1507   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);
1508   @endcode
1509   @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
1510 **/
1511 #define MSR_IVY_BRIDGE_C8_PMON_CTR0  0x00000E16
1512
1513 /**
1514   Package. Uncore C-box 8 perfmon counter 1.
1515
1516   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)
1517   @param  EAX  Lower 32-bits of MSR value.
1518   @param  EDX  Upper 32-bits of MSR value.
1519
1520   <b>Example usage</b>
1521   @code
1522   UINT64  Msr;
1523
1524   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);
1525   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);
1526   @endcode
1527   @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
1528 **/
1529 #define MSR_IVY_BRIDGE_C8_PMON_CTR1  0x00000E17
1530
1531 /**
1532   Package. Uncore C-box 8 perfmon counter 2.
1533
1534   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)
1535   @param  EAX  Lower 32-bits of MSR value.
1536   @param  EDX  Upper 32-bits of MSR value.
1537
1538   <b>Example usage</b>
1539   @code
1540   UINT64  Msr;
1541
1542   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);
1543   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);
1544   @endcode
1545   @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
1546 **/
1547 #define MSR_IVY_BRIDGE_C8_PMON_CTR2  0x00000E18
1548
1549 /**
1550   Package. Uncore C-box 8 perfmon counter 3.
1551
1552   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)
1553   @param  EAX  Lower 32-bits of MSR value.
1554   @param  EDX  Upper 32-bits of MSR value.
1555
1556   <b>Example usage</b>
1557   @code
1558   UINT64  Msr;
1559
1560   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);
1561   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);
1562   @endcode
1563   @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
1564 **/
1565 #define MSR_IVY_BRIDGE_C8_PMON_CTR3  0x00000E19
1566
1567 /**
1568   Package. Uncore C-box 8 perfmon box wide filter1.
1569
1570   @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)
1571   @param  EAX  Lower 32-bits of MSR value.
1572   @param  EDX  Upper 32-bits of MSR value.
1573
1574   <b>Example usage</b>
1575   @code
1576   UINT64  Msr;
1577
1578   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);
1579   AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);
1580   @endcode
1581   @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
1582 **/
1583 #define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1  0x00000E1A
1584
1585 /**
1586   Package. Uncore C-box 9 perfmon local box wide control.
1587
1588   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)
1589   @param  EAX  Lower 32-bits of MSR value.
1590   @param  EDX  Upper 32-bits of MSR value.
1591
1592   <b>Example usage</b>
1593   @code
1594   UINT64  Msr;
1595
1596   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);
1597   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);
1598   @endcode
1599   @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
1600 **/
1601 #define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL  0x00000E24
1602
1603 /**
1604   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
1605
1606   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)
1607   @param  EAX  Lower 32-bits of MSR value.
1608   @param  EDX  Upper 32-bits of MSR value.
1609
1610   <b>Example usage</b>
1611   @code
1612   UINT64  Msr;
1613
1614   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);
1615   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);
1616   @endcode
1617   @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
1618 **/
1619 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0  0x00000E30
1620
1621 /**
1622   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
1623
1624   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)
1625   @param  EAX  Lower 32-bits of MSR value.
1626   @param  EDX  Upper 32-bits of MSR value.
1627
1628   <b>Example usage</b>
1629   @code
1630   UINT64  Msr;
1631
1632   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);
1633   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);
1634   @endcode
1635   @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
1636 **/
1637 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1  0x00000E31
1638
1639 /**
1640   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
1641
1642   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)
1643   @param  EAX  Lower 32-bits of MSR value.
1644   @param  EDX  Upper 32-bits of MSR value.
1645
1646   <b>Example usage</b>
1647   @code
1648   UINT64  Msr;
1649
1650   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);
1651   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);
1652   @endcode
1653   @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
1654 **/
1655 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2  0x00000E32
1656
1657 /**
1658   Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
1659
1660   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)
1661   @param  EAX  Lower 32-bits of MSR value.
1662   @param  EDX  Upper 32-bits of MSR value.
1663
1664   <b>Example usage</b>
1665   @code
1666   UINT64  Msr;
1667
1668   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);
1669   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);
1670   @endcode
1671   @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
1672 **/
1673 #define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3  0x00000E33
1674
1675 /**
1676   Package. Uncore C-box 9 perfmon box wide filter.
1677
1678   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)
1679   @param  EAX  Lower 32-bits of MSR value.
1680   @param  EDX  Upper 32-bits of MSR value.
1681
1682   <b>Example usage</b>
1683   @code
1684   UINT64  Msr;
1685
1686   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);
1687   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);
1688   @endcode
1689   @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.
1690 **/
1691 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER  0x00000E34
1692
1693 /**
1694   Package. Uncore C-box 9 perfmon counter 0.
1695
1696   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)
1697   @param  EAX  Lower 32-bits of MSR value.
1698   @param  EDX  Upper 32-bits of MSR value.
1699
1700   <b>Example usage</b>
1701   @code
1702   UINT64  Msr;
1703
1704   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);
1705   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);
1706   @endcode
1707   @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
1708 **/
1709 #define MSR_IVY_BRIDGE_C9_PMON_CTR0  0x00000E36
1710
1711 /**
1712   Package. Uncore C-box 9 perfmon counter 1.
1713
1714   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)
1715   @param  EAX  Lower 32-bits of MSR value.
1716   @param  EDX  Upper 32-bits of MSR value.
1717
1718   <b>Example usage</b>
1719   @code
1720   UINT64  Msr;
1721
1722   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);
1723   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);
1724   @endcode
1725   @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
1726 **/
1727 #define MSR_IVY_BRIDGE_C9_PMON_CTR1  0x00000E37
1728
1729 /**
1730   Package. Uncore C-box 9 perfmon counter 2.
1731
1732   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)
1733   @param  EAX  Lower 32-bits of MSR value.
1734   @param  EDX  Upper 32-bits of MSR value.
1735
1736   <b>Example usage</b>
1737   @code
1738   UINT64  Msr;
1739
1740   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);
1741   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);
1742   @endcode
1743   @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
1744 **/
1745 #define MSR_IVY_BRIDGE_C9_PMON_CTR2  0x00000E38
1746
1747 /**
1748   Package. Uncore C-box 9 perfmon counter 3.
1749
1750   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)
1751   @param  EAX  Lower 32-bits of MSR value.
1752   @param  EDX  Upper 32-bits of MSR value.
1753
1754   <b>Example usage</b>
1755   @code
1756   UINT64  Msr;
1757
1758   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);
1759   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);
1760   @endcode
1761   @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
1762 **/
1763 #define MSR_IVY_BRIDGE_C9_PMON_CTR3  0x00000E39
1764
1765 /**
1766   Package. Uncore C-box 9 perfmon box wide filter1.
1767
1768   @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)
1769   @param  EAX  Lower 32-bits of MSR value.
1770   @param  EDX  Upper 32-bits of MSR value.
1771
1772   <b>Example usage</b>
1773   @code
1774   UINT64  Msr;
1775
1776   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);
1777   AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);
1778   @endcode
1779   @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
1780 **/
1781 #define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1  0x00000E3A
1782
1783 /**
1784   Package. Uncore C-box 10 perfmon local box wide control.
1785
1786   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)
1787   @param  EAX  Lower 32-bits of MSR value.
1788   @param  EDX  Upper 32-bits of MSR value.
1789
1790   <b>Example usage</b>
1791   @code
1792   UINT64  Msr;
1793
1794   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);
1795   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);
1796   @endcode
1797   @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
1798 **/
1799 #define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL  0x00000E44
1800
1801 /**
1802   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
1803
1804   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)
1805   @param  EAX  Lower 32-bits of MSR value.
1806   @param  EDX  Upper 32-bits of MSR value.
1807
1808   <b>Example usage</b>
1809   @code
1810   UINT64  Msr;
1811
1812   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);
1813   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);
1814   @endcode
1815   @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
1816 **/
1817 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0  0x00000E50
1818
1819 /**
1820   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
1821
1822   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)
1823   @param  EAX  Lower 32-bits of MSR value.
1824   @param  EDX  Upper 32-bits of MSR value.
1825
1826   <b>Example usage</b>
1827   @code
1828   UINT64  Msr;
1829
1830   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);
1831   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);
1832   @endcode
1833   @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
1834 **/
1835 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1  0x00000E51
1836
1837 /**
1838   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
1839
1840   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)
1841   @param  EAX  Lower 32-bits of MSR value.
1842   @param  EDX  Upper 32-bits of MSR value.
1843
1844   <b>Example usage</b>
1845   @code
1846   UINT64  Msr;
1847
1848   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);
1849   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);
1850   @endcode
1851   @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
1852 **/
1853 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2  0x00000E52
1854
1855 /**
1856   Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
1857
1858   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)
1859   @param  EAX  Lower 32-bits of MSR value.
1860   @param  EDX  Upper 32-bits of MSR value.
1861
1862   <b>Example usage</b>
1863   @code
1864   UINT64  Msr;
1865
1866   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);
1867   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);
1868   @endcode
1869   @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
1870 **/
1871 #define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3  0x00000E53
1872
1873 /**
1874   Package. Uncore C-box 10 perfmon box wide filter.
1875
1876   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)
1877   @param  EAX  Lower 32-bits of MSR value.
1878   @param  EDX  Upper 32-bits of MSR value.
1879
1880   <b>Example usage</b>
1881   @code
1882   UINT64  Msr;
1883
1884   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);
1885   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);
1886   @endcode
1887   @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.
1888 **/
1889 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER  0x00000E54
1890
1891 /**
1892   Package. Uncore C-box 10 perfmon counter 0.
1893
1894   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)
1895   @param  EAX  Lower 32-bits of MSR value.
1896   @param  EDX  Upper 32-bits of MSR value.
1897
1898   <b>Example usage</b>
1899   @code
1900   UINT64  Msr;
1901
1902   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);
1903   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);
1904   @endcode
1905   @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
1906 **/
1907 #define MSR_IVY_BRIDGE_C10_PMON_CTR0  0x00000E56
1908
1909 /**
1910   Package. Uncore C-box 10 perfmon counter 1.
1911
1912   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)
1913   @param  EAX  Lower 32-bits of MSR value.
1914   @param  EDX  Upper 32-bits of MSR value.
1915
1916   <b>Example usage</b>
1917   @code
1918   UINT64  Msr;
1919
1920   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);
1921   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);
1922   @endcode
1923   @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
1924 **/
1925 #define MSR_IVY_BRIDGE_C10_PMON_CTR1  0x00000E57
1926
1927 /**
1928   Package. Uncore C-box 10 perfmon counter 2.
1929
1930   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)
1931   @param  EAX  Lower 32-bits of MSR value.
1932   @param  EDX  Upper 32-bits of MSR value.
1933
1934   <b>Example usage</b>
1935   @code
1936   UINT64  Msr;
1937
1938   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);
1939   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);
1940   @endcode
1941   @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
1942 **/
1943 #define MSR_IVY_BRIDGE_C10_PMON_CTR2  0x00000E58
1944
1945 /**
1946   Package. Uncore C-box 10 perfmon counter 3.
1947
1948   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)
1949   @param  EAX  Lower 32-bits of MSR value.
1950   @param  EDX  Upper 32-bits of MSR value.
1951
1952   <b>Example usage</b>
1953   @code
1954   UINT64  Msr;
1955
1956   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);
1957   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);
1958   @endcode
1959   @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
1960 **/
1961 #define MSR_IVY_BRIDGE_C10_PMON_CTR3  0x00000E59
1962
1963 /**
1964   Package. Uncore C-box 10 perfmon box wide filter1.
1965
1966   @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)
1967   @param  EAX  Lower 32-bits of MSR value.
1968   @param  EDX  Upper 32-bits of MSR value.
1969
1970   <b>Example usage</b>
1971   @code
1972   UINT64  Msr;
1973
1974   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);
1975   AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);
1976   @endcode
1977   @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
1978 **/
1979 #define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1  0x00000E5A
1980
1981 /**
1982   Package. Uncore C-box 11 perfmon local box wide control.
1983
1984   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)
1985   @param  EAX  Lower 32-bits of MSR value.
1986   @param  EDX  Upper 32-bits of MSR value.
1987
1988   <b>Example usage</b>
1989   @code
1990   UINT64  Msr;
1991
1992   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);
1993   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);
1994   @endcode
1995   @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
1996 **/
1997 #define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL  0x00000E64
1998
1999 /**
2000   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
2001
2002   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)
2003   @param  EAX  Lower 32-bits of MSR value.
2004   @param  EDX  Upper 32-bits of MSR value.
2005
2006   <b>Example usage</b>
2007   @code
2008   UINT64  Msr;
2009
2010   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);
2011   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);
2012   @endcode
2013   @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
2014 **/
2015 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0  0x00000E70
2016
2017 /**
2018   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
2019
2020   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)
2021   @param  EAX  Lower 32-bits of MSR value.
2022   @param  EDX  Upper 32-bits of MSR value.
2023
2024   <b>Example usage</b>
2025   @code
2026   UINT64  Msr;
2027
2028   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);
2029   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);
2030   @endcode
2031   @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
2032 **/
2033 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1  0x00000E71
2034
2035 /**
2036   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
2037
2038   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)
2039   @param  EAX  Lower 32-bits of MSR value.
2040   @param  EDX  Upper 32-bits of MSR value.
2041
2042   <b>Example usage</b>
2043   @code
2044   UINT64  Msr;
2045
2046   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);
2047   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);
2048   @endcode
2049   @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
2050 **/
2051 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2  0x00000E72
2052
2053 /**
2054   Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
2055
2056   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)
2057   @param  EAX  Lower 32-bits of MSR value.
2058   @param  EDX  Upper 32-bits of MSR value.
2059
2060   <b>Example usage</b>
2061   @code
2062   UINT64  Msr;
2063
2064   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);
2065   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);
2066   @endcode
2067   @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
2068 **/
2069 #define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3  0x00000E73
2070
2071 /**
2072   Package. Uncore C-box 11 perfmon box wide filter.
2073
2074   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)
2075   @param  EAX  Lower 32-bits of MSR value.
2076   @param  EDX  Upper 32-bits of MSR value.
2077
2078   <b>Example usage</b>
2079   @code
2080   UINT64  Msr;
2081
2082   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);
2083   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);
2084   @endcode
2085   @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.
2086 **/
2087 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER  0x00000E74
2088
2089 /**
2090   Package. Uncore C-box 11 perfmon counter 0.
2091
2092   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)
2093   @param  EAX  Lower 32-bits of MSR value.
2094   @param  EDX  Upper 32-bits of MSR value.
2095
2096   <b>Example usage</b>
2097   @code
2098   UINT64  Msr;
2099
2100   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);
2101   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);
2102   @endcode
2103   @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
2104 **/
2105 #define MSR_IVY_BRIDGE_C11_PMON_CTR0  0x00000E76
2106
2107 /**
2108   Package. Uncore C-box 11 perfmon counter 1.
2109
2110   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)
2111   @param  EAX  Lower 32-bits of MSR value.
2112   @param  EDX  Upper 32-bits of MSR value.
2113
2114   <b>Example usage</b>
2115   @code
2116   UINT64  Msr;
2117
2118   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);
2119   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);
2120   @endcode
2121   @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
2122 **/
2123 #define MSR_IVY_BRIDGE_C11_PMON_CTR1  0x00000E77
2124
2125 /**
2126   Package. Uncore C-box 11 perfmon counter 2.
2127
2128   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)
2129   @param  EAX  Lower 32-bits of MSR value.
2130   @param  EDX  Upper 32-bits of MSR value.
2131
2132   <b>Example usage</b>
2133   @code
2134   UINT64  Msr;
2135
2136   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);
2137   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);
2138   @endcode
2139   @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
2140 **/
2141 #define MSR_IVY_BRIDGE_C11_PMON_CTR2  0x00000E78
2142
2143 /**
2144   Package. Uncore C-box 11 perfmon counter 3.
2145
2146   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)
2147   @param  EAX  Lower 32-bits of MSR value.
2148   @param  EDX  Upper 32-bits of MSR value.
2149
2150   <b>Example usage</b>
2151   @code
2152   UINT64  Msr;
2153
2154   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);
2155   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);
2156   @endcode
2157   @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
2158 **/
2159 #define MSR_IVY_BRIDGE_C11_PMON_CTR3  0x00000E79
2160
2161 /**
2162   Package. Uncore C-box 11 perfmon box wide filter1.
2163
2164   @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)
2165   @param  EAX  Lower 32-bits of MSR value.
2166   @param  EDX  Upper 32-bits of MSR value.
2167
2168   <b>Example usage</b>
2169   @code
2170   UINT64  Msr;
2171
2172   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);
2173   AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);
2174   @endcode
2175   @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
2176 **/
2177 #define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1  0x00000E7A
2178
2179 /**
2180   Package. Uncore C-box 12 perfmon local box wide control.
2181
2182   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)
2183   @param  EAX  Lower 32-bits of MSR value.
2184   @param  EDX  Upper 32-bits of MSR value.
2185
2186   <b>Example usage</b>
2187   @code
2188   UINT64  Msr;
2189
2190   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);
2191   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);
2192   @endcode
2193   @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
2194 **/
2195 #define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL  0x00000E84
2196
2197 /**
2198   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
2199
2200   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)
2201   @param  EAX  Lower 32-bits of MSR value.
2202   @param  EDX  Upper 32-bits of MSR value.
2203
2204   <b>Example usage</b>
2205   @code
2206   UINT64  Msr;
2207
2208   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);
2209   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);
2210   @endcode
2211   @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
2212 **/
2213 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0  0x00000E90
2214
2215 /**
2216   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
2217
2218   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)
2219   @param  EAX  Lower 32-bits of MSR value.
2220   @param  EDX  Upper 32-bits of MSR value.
2221
2222   <b>Example usage</b>
2223   @code
2224   UINT64  Msr;
2225
2226   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);
2227   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);
2228   @endcode
2229   @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
2230 **/
2231 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1  0x00000E91
2232
2233 /**
2234   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
2235
2236   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)
2237   @param  EAX  Lower 32-bits of MSR value.
2238   @param  EDX  Upper 32-bits of MSR value.
2239
2240   <b>Example usage</b>
2241   @code
2242   UINT64  Msr;
2243
2244   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);
2245   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);
2246   @endcode
2247   @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
2248 **/
2249 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2  0x00000E92
2250
2251 /**
2252   Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
2253
2254   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)
2255   @param  EAX  Lower 32-bits of MSR value.
2256   @param  EDX  Upper 32-bits of MSR value.
2257
2258   <b>Example usage</b>
2259   @code
2260   UINT64  Msr;
2261
2262   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);
2263   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);
2264   @endcode
2265   @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
2266 **/
2267 #define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3  0x00000E93
2268
2269 /**
2270   Package. Uncore C-box 12 perfmon box wide filter.
2271
2272   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)
2273   @param  EAX  Lower 32-bits of MSR value.
2274   @param  EDX  Upper 32-bits of MSR value.
2275
2276   <b>Example usage</b>
2277   @code
2278   UINT64  Msr;
2279
2280   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);
2281   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);
2282   @endcode
2283   @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.
2284 **/
2285 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER  0x00000E94
2286
2287 /**
2288   Package. Uncore C-box 12 perfmon counter 0.
2289
2290   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)
2291   @param  EAX  Lower 32-bits of MSR value.
2292   @param  EDX  Upper 32-bits of MSR value.
2293
2294   <b>Example usage</b>
2295   @code
2296   UINT64  Msr;
2297
2298   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);
2299   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);
2300   @endcode
2301   @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
2302 **/
2303 #define MSR_IVY_BRIDGE_C12_PMON_CTR0  0x00000E96
2304
2305 /**
2306   Package. Uncore C-box 12 perfmon counter 1.
2307
2308   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)
2309   @param  EAX  Lower 32-bits of MSR value.
2310   @param  EDX  Upper 32-bits of MSR value.
2311
2312   <b>Example usage</b>
2313   @code
2314   UINT64  Msr;
2315
2316   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);
2317   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);
2318   @endcode
2319   @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
2320 **/
2321 #define MSR_IVY_BRIDGE_C12_PMON_CTR1  0x00000E97
2322
2323 /**
2324   Package. Uncore C-box 12 perfmon counter 2.
2325
2326   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)
2327   @param  EAX  Lower 32-bits of MSR value.
2328   @param  EDX  Upper 32-bits of MSR value.
2329
2330   <b>Example usage</b>
2331   @code
2332   UINT64  Msr;
2333
2334   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);
2335   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);
2336   @endcode
2337   @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
2338 **/
2339 #define MSR_IVY_BRIDGE_C12_PMON_CTR2  0x00000E98
2340
2341 /**
2342   Package. Uncore C-box 12 perfmon counter 3.
2343
2344   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)
2345   @param  EAX  Lower 32-bits of MSR value.
2346   @param  EDX  Upper 32-bits of MSR value.
2347
2348   <b>Example usage</b>
2349   @code
2350   UINT64  Msr;
2351
2352   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);
2353   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);
2354   @endcode
2355   @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
2356 **/
2357 #define MSR_IVY_BRIDGE_C12_PMON_CTR3  0x00000E99
2358
2359 /**
2360   Package. Uncore C-box 12 perfmon box wide filter1.
2361
2362   @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)
2363   @param  EAX  Lower 32-bits of MSR value.
2364   @param  EDX  Upper 32-bits of MSR value.
2365
2366   <b>Example usage</b>
2367   @code
2368   UINT64  Msr;
2369
2370   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);
2371   AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);
2372   @endcode
2373   @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
2374 **/
2375 #define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1  0x00000E9A
2376
2377 /**
2378   Package. Uncore C-box 13 perfmon local box wide control.
2379
2380   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)
2381   @param  EAX  Lower 32-bits of MSR value.
2382   @param  EDX  Upper 32-bits of MSR value.
2383
2384   <b>Example usage</b>
2385   @code
2386   UINT64  Msr;
2387
2388   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);
2389   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);
2390   @endcode
2391   @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
2392 **/
2393 #define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL  0x00000EA4
2394
2395 /**
2396   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
2397
2398   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)
2399   @param  EAX  Lower 32-bits of MSR value.
2400   @param  EDX  Upper 32-bits of MSR value.
2401
2402   <b>Example usage</b>
2403   @code
2404   UINT64  Msr;
2405
2406   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);
2407   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);
2408   @endcode
2409   @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
2410 **/
2411 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0  0x00000EB0
2412
2413 /**
2414   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
2415
2416   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)
2417   @param  EAX  Lower 32-bits of MSR value.
2418   @param  EDX  Upper 32-bits of MSR value.
2419
2420   <b>Example usage</b>
2421   @code
2422   UINT64  Msr;
2423
2424   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);
2425   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);
2426   @endcode
2427   @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
2428 **/
2429 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1  0x00000EB1
2430
2431 /**
2432   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
2433
2434   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)
2435   @param  EAX  Lower 32-bits of MSR value.
2436   @param  EDX  Upper 32-bits of MSR value.
2437
2438   <b>Example usage</b>
2439   @code
2440   UINT64  Msr;
2441
2442   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);
2443   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);
2444   @endcode
2445   @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
2446 **/
2447 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2  0x00000EB2
2448
2449 /**
2450   Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
2451
2452   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)
2453   @param  EAX  Lower 32-bits of MSR value.
2454   @param  EDX  Upper 32-bits of MSR value.
2455
2456   <b>Example usage</b>
2457   @code
2458   UINT64  Msr;
2459
2460   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);
2461   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);
2462   @endcode
2463   @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
2464 **/
2465 #define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3  0x00000EB3
2466
2467 /**
2468   Package. Uncore C-box 13 perfmon box wide filter.
2469
2470   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)
2471   @param  EAX  Lower 32-bits of MSR value.
2472   @param  EDX  Upper 32-bits of MSR value.
2473
2474   <b>Example usage</b>
2475   @code
2476   UINT64  Msr;
2477
2478   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);
2479   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);
2480   @endcode
2481   @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.
2482 **/
2483 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER  0x00000EB4
2484
2485 /**
2486   Package. Uncore C-box 13 perfmon counter 0.
2487
2488   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)
2489   @param  EAX  Lower 32-bits of MSR value.
2490   @param  EDX  Upper 32-bits of MSR value.
2491
2492   <b>Example usage</b>
2493   @code
2494   UINT64  Msr;
2495
2496   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);
2497   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);
2498   @endcode
2499   @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
2500 **/
2501 #define MSR_IVY_BRIDGE_C13_PMON_CTR0  0x00000EB6
2502
2503 /**
2504   Package. Uncore C-box 13 perfmon counter 1.
2505
2506   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)
2507   @param  EAX  Lower 32-bits of MSR value.
2508   @param  EDX  Upper 32-bits of MSR value.
2509
2510   <b>Example usage</b>
2511   @code
2512   UINT64  Msr;
2513
2514   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);
2515   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);
2516   @endcode
2517   @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
2518 **/
2519 #define MSR_IVY_BRIDGE_C13_PMON_CTR1  0x00000EB7
2520
2521 /**
2522   Package. Uncore C-box 13 perfmon counter 2.
2523
2524   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)
2525   @param  EAX  Lower 32-bits of MSR value.
2526   @param  EDX  Upper 32-bits of MSR value.
2527
2528   <b>Example usage</b>
2529   @code
2530   UINT64  Msr;
2531
2532   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);
2533   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);
2534   @endcode
2535   @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
2536 **/
2537 #define MSR_IVY_BRIDGE_C13_PMON_CTR2  0x00000EB8
2538
2539 /**
2540   Package. Uncore C-box 13 perfmon counter 3.
2541
2542   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)
2543   @param  EAX  Lower 32-bits of MSR value.
2544   @param  EDX  Upper 32-bits of MSR value.
2545
2546   <b>Example usage</b>
2547   @code
2548   UINT64  Msr;
2549
2550   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);
2551   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);
2552   @endcode
2553   @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
2554 **/
2555 #define MSR_IVY_BRIDGE_C13_PMON_CTR3  0x00000EB9
2556
2557 /**
2558   Package. Uncore C-box 13 perfmon box wide filter1.
2559
2560   @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)
2561   @param  EAX  Lower 32-bits of MSR value.
2562   @param  EDX  Upper 32-bits of MSR value.
2563
2564   <b>Example usage</b>
2565   @code
2566   UINT64  Msr;
2567
2568   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);
2569   AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);
2570   @endcode
2571   @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
2572 **/
2573 #define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1  0x00000EBA
2574
2575 /**
2576   Package. Uncore C-box 14 perfmon local box wide control.
2577
2578   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)
2579   @param  EAX  Lower 32-bits of MSR value.
2580   @param  EDX  Upper 32-bits of MSR value.
2581
2582   <b>Example usage</b>
2583   @code
2584   UINT64  Msr;
2585
2586   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);
2587   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);
2588   @endcode
2589   @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
2590 **/
2591 #define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL  0x00000EC4
2592
2593 /**
2594   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
2595
2596   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)
2597   @param  EAX  Lower 32-bits of MSR value.
2598   @param  EDX  Upper 32-bits of MSR value.
2599
2600   <b>Example usage</b>
2601   @code
2602   UINT64  Msr;
2603
2604   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);
2605   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);
2606   @endcode
2607   @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
2608 **/
2609 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0  0x00000ED0
2610
2611 /**
2612   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
2613
2614   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)
2615   @param  EAX  Lower 32-bits of MSR value.
2616   @param  EDX  Upper 32-bits of MSR value.
2617
2618   <b>Example usage</b>
2619   @code
2620   UINT64  Msr;
2621
2622   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);
2623   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);
2624   @endcode
2625   @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
2626 **/
2627 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1  0x00000ED1
2628
2629 /**
2630   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
2631
2632   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)
2633   @param  EAX  Lower 32-bits of MSR value.
2634   @param  EDX  Upper 32-bits of MSR value.
2635
2636   <b>Example usage</b>
2637   @code
2638   UINT64  Msr;
2639
2640   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);
2641   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);
2642   @endcode
2643   @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
2644 **/
2645 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2  0x00000ED2
2646
2647 /**
2648   Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
2649
2650   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)
2651   @param  EAX  Lower 32-bits of MSR value.
2652   @param  EDX  Upper 32-bits of MSR value.
2653
2654   <b>Example usage</b>
2655   @code
2656   UINT64  Msr;
2657
2658   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);
2659   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);
2660   @endcode
2661   @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
2662 **/
2663 #define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3  0x00000ED3
2664
2665 /**
2666   Package. Uncore C-box 14 perfmon box wide filter.
2667
2668   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)
2669   @param  EAX  Lower 32-bits of MSR value.
2670   @param  EDX  Upper 32-bits of MSR value.
2671
2672   <b>Example usage</b>
2673   @code
2674   UINT64  Msr;
2675
2676   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);
2677   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);
2678   @endcode
2679   @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
2680 **/
2681 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER  0x00000ED4
2682
2683 /**
2684   Package. Uncore C-box 14 perfmon counter 0.
2685
2686   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)
2687   @param  EAX  Lower 32-bits of MSR value.
2688   @param  EDX  Upper 32-bits of MSR value.
2689
2690   <b>Example usage</b>
2691   @code
2692   UINT64  Msr;
2693
2694   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);
2695   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);
2696   @endcode
2697   @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
2698 **/
2699 #define MSR_IVY_BRIDGE_C14_PMON_CTR0  0x00000ED6
2700
2701 /**
2702   Package. Uncore C-box 14 perfmon counter 1.
2703
2704   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)
2705   @param  EAX  Lower 32-bits of MSR value.
2706   @param  EDX  Upper 32-bits of MSR value.
2707
2708   <b>Example usage</b>
2709   @code
2710   UINT64  Msr;
2711
2712   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);
2713   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);
2714   @endcode
2715   @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
2716 **/
2717 #define MSR_IVY_BRIDGE_C14_PMON_CTR1  0x00000ED7
2718
2719 /**
2720   Package. Uncore C-box 14 perfmon counter 2.
2721
2722   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)
2723   @param  EAX  Lower 32-bits of MSR value.
2724   @param  EDX  Upper 32-bits of MSR value.
2725
2726   <b>Example usage</b>
2727   @code
2728   UINT64  Msr;
2729
2730   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);
2731   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);
2732   @endcode
2733   @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
2734 **/
2735 #define MSR_IVY_BRIDGE_C14_PMON_CTR2  0x00000ED8
2736
2737 /**
2738   Package. Uncore C-box 14 perfmon counter 3.
2739
2740   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)
2741   @param  EAX  Lower 32-bits of MSR value.
2742   @param  EDX  Upper 32-bits of MSR value.
2743
2744   <b>Example usage</b>
2745   @code
2746   UINT64  Msr;
2747
2748   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);
2749   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);
2750   @endcode
2751   @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
2752 **/
2753 #define MSR_IVY_BRIDGE_C14_PMON_CTR3  0x00000ED9
2754
2755 /**
2756   Package. Uncore C-box 14 perfmon box wide filter1.
2757
2758   @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)
2759   @param  EAX  Lower 32-bits of MSR value.
2760   @param  EDX  Upper 32-bits of MSR value.
2761
2762   <b>Example usage</b>
2763   @code
2764   UINT64  Msr;
2765
2766   Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);
2767   AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);
2768   @endcode
2769   @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
2770 **/
2771 #define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1  0x00000EDA
2772
2773 #endif