2 MSR Definitions for Intel processors based on the Nehalem microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __NEHALEM_MSR_H__
19 #define __NEHALEM_MSR_H__
21 #include <Register/Intel/ArchitecturalMsr.h>
24 Is Intel processors based on the Nehalem microarchitecture?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x1A || \
36 DisplayModel == 0x1E || \
37 DisplayModel == 0x1F || \
38 DisplayModel == 0x2E \
43 Package. Model Specific Platform ID (R).
45 @param ECX MSR_NEHALEM_PLATFORM_ID (0x00000017)
46 @param EAX Lower 32-bits of MSR value.
47 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
48 @param EDX Upper 32-bits of MSR value.
49 Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
53 MSR_NEHALEM_PLATFORM_ID_REGISTER Msr;
55 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);
57 @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
59 #define MSR_NEHALEM_PLATFORM_ID 0x00000017
62 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID
66 /// Individual bit fields
72 /// [Bits 52:50] See Table 2-2.
78 /// All bit fields as a 64-bit value
81 } MSR_NEHALEM_PLATFORM_ID_REGISTER
;
85 Thread. SMI Counter (R/O).
87 @param ECX MSR_NEHALEM_SMI_COUNT (0x00000034)
88 @param EAX Lower 32-bits of MSR value.
89 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
90 @param EDX Upper 32-bits of MSR value.
91 Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
95 MSR_NEHALEM_SMI_COUNT_REGISTER Msr;
97 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);
99 @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
101 #define MSR_NEHALEM_SMI_COUNT 0x00000034
104 MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT
108 /// Individual bit fields
112 /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last
119 /// All bit fields as a 32-bit value
123 /// All bit fields as a 64-bit value
126 } MSR_NEHALEM_SMI_COUNT_REGISTER
;
130 Package. see http://biosbits.org.
132 @param ECX MSR_NEHALEM_PLATFORM_INFO (0x000000CE)
133 @param EAX Lower 32-bits of MSR value.
134 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
135 @param EDX Upper 32-bits of MSR value.
136 Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
140 MSR_NEHALEM_PLATFORM_INFO_REGISTER Msr;
142 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);
143 AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);
145 @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
147 #define MSR_NEHALEM_PLATFORM_INFO 0x000000CE
150 MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO
154 /// Individual bit fields
159 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
160 /// of the frequency that invariant TSC runs at. The invariant TSC
161 /// frequency can be computed by multiplying this ratio by 133.33 MHz.
163 UINT32 MaximumNonTurboRatio
:8;
166 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
167 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
168 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
169 /// Turbo mode is disabled.
173 /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)
174 /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are
175 /// programmable, and when set to 0, indicates TDC and TDP Limits for
176 /// Turbo mode are not programmable.
178 UINT32 TDC_TDPLimit
:1;
182 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
183 /// minimum ratio (maximum efficiency) that the processor can operates, in
184 /// units of 133.33MHz.
186 UINT32 MaximumEfficiencyRatio
:8;
190 /// All bit fields as a 64-bit value
193 } MSR_NEHALEM_PLATFORM_INFO_REGISTER
;
197 Core. C-State Configuration Control (R/W) Note: C-state values are
198 processor specific C-state code names, unrelated to MWAIT extension C-state
199 parameters or ACPI CStates. See http://biosbits.org.
201 @param ECX MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)
202 @param EAX Lower 32-bits of MSR value.
203 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
204 @param EDX Upper 32-bits of MSR value.
205 Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
209 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
211 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);
212 AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
214 @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
216 #define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL 0x000000E2
219 MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL
223 /// Individual bit fields
227 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
228 /// processor-specific C-state code name (consuming the least power). for
229 /// the package. The default is set as factory-configured package C-state
230 /// limit. The following C-state code name encodings are supported: 000b:
231 /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
232 /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package
233 /// C-state limit. Note: This field cannot be used to limit package
239 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
240 /// IO_read instructions sent to IO register specified by
241 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
246 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
247 /// until next reset.
252 /// [Bit 24] Interrupt filtering enable (R/W) When set, processor cores
253 /// in a deep C-State will wake only when the event message is destined
254 /// for that core. When 0, all processor cores in a deep C-State will wake
255 /// for an event message.
257 UINT32 InterruptFiltering
:1;
259 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
260 /// will conditionally demote C6/C7 requests to C3 based on uncore
261 /// auto-demote information.
263 UINT32 C3AutoDemotion
:1;
265 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
266 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
267 /// auto-demote information.
269 UINT32 C1AutoDemotion
:1;
271 /// [Bit 27] Enable C3 Undemotion (R/W).
273 UINT32 C3Undemotion
:1;
275 /// [Bit 28] Enable C1 Undemotion (R/W).
277 UINT32 C1Undemotion
:1;
279 /// [Bit 29] Package C State Demotion Enable (R/W).
281 UINT32 CStateDemotion
:1;
283 /// [Bit 30] Package C State UnDemotion Enable (R/W).
285 UINT32 CStateUndemotion
:1;
290 /// All bit fields as a 32-bit value
294 /// All bit fields as a 64-bit value
297 } MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER
;
301 Core. Power Management IO Redirection in C-state (R/W) See
304 @param ECX MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)
305 @param EAX Lower 32-bits of MSR value.
306 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
307 @param EDX Upper 32-bits of MSR value.
308 Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
312 MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Msr;
314 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);
315 AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);
317 @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
319 #define MSR_NEHALEM_PMG_IO_CAPTURE_BASE 0x000000E4
322 MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE
326 /// Individual bit fields
330 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
331 /// visible to software for IO redirection. If IO MWAIT Redirection is
332 /// enabled, reads to this address will be consumed by the power
333 /// management logic and decoded to MWAIT instructions. When IO port
334 /// address redirection is enabled, this is the IO port address reported
335 /// to the OS/software.
339 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
340 /// maximum C-State code name to be included when IO read to MWAIT
341 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
342 /// is the max C-State to include 001b - C6 is the max C-State to include
343 /// 010b - C7 is the max C-State to include.
345 UINT32 CStateRange
:3;
350 /// All bit fields as a 32-bit value
354 /// All bit fields as a 64-bit value
357 } MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER
;
361 Enable Misc. Processor Features (R/W) Allows a variety of processor
362 functions to be enabled and disabled.
364 @param ECX MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)
365 @param EAX Lower 32-bits of MSR value.
366 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
367 @param EDX Upper 32-bits of MSR value.
368 Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
372 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Msr;
374 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);
375 AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);
377 @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
379 #define MSR_NEHALEM_IA32_MISC_ENABLE 0x000001A0
382 MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE
386 /// Individual bit fields
390 /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.
392 UINT32 FastStrings
:1;
395 /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See
396 /// Table 2-2. Default value is 1.
398 UINT32 AutomaticThermalControlCircuit
:1;
401 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.
403 UINT32 PerformanceMonitoring
:1;
406 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.
410 /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
416 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
422 /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.
427 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.
429 UINT32 LimitCpuidMaxval
:1;
431 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.
433 UINT32 xTPR_Message_Disable
:1;
437 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.
442 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
443 /// that support Intel Turbo Boost Technology, the turbo mode feature is
444 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
445 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
446 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
447 /// the power-on default value is used by BIOS to detect hardware support
448 /// of turbo mode. If power-on default value is 1, turbo mode is available
449 /// in the processor. If power-on default value is 0, turbo mode is not
452 UINT32 TurboModeDisable
:1;
453 UINT32 Reserved10
:25;
456 /// All bit fields as a 64-bit value
459 } MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER
;
465 @param ECX MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)
466 @param EAX Lower 32-bits of MSR value.
467 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
468 @param EDX Upper 32-bits of MSR value.
469 Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
473 MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Msr;
475 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);
476 AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);
478 @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
480 #define MSR_NEHALEM_TEMPERATURE_TARGET 0x000001A2
483 MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET
487 /// Individual bit fields
492 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
493 /// PROCHOT# will be asserted. The value is degree C.
495 UINT32 TemperatureTarget
:8;
500 /// All bit fields as a 32-bit value
504 /// All bit fields as a 64-bit value
507 } MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER
;
511 Miscellaneous Feature Control (R/W).
513 @param ECX MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)
514 @param EAX Lower 32-bits of MSR value.
515 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
516 @param EDX Upper 32-bits of MSR value.
517 Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
521 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Msr;
523 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);
524 AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);
526 @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
528 #define MSR_NEHALEM_MISC_FEATURE_CONTROL 0x000001A4
531 MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL
535 /// Individual bit fields
539 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
540 /// L2 hardware prefetcher, which fetches additional lines of code or data
541 /// into the L2 cache.
543 UINT32 L2HardwarePrefetcherDisable
:1;
545 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
546 /// disables the adjacent cache line prefetcher, which fetches the cache
547 /// line that comprises a cache line pair (128 bytes).
549 UINT32 L2AdjacentCacheLinePrefetcherDisable
:1;
551 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
552 /// the L1 data cache prefetcher, which fetches the next cache line into
555 UINT32 DCUHardwarePrefetcherDisable
:1;
557 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
558 /// data cache IP prefetcher, which uses sequential load history (based on
559 /// instruction Pointer of previous loads) to determine whether to
560 /// prefetch additional lines.
562 UINT32 DCUIPPrefetcherDisable
:1;
567 /// All bit fields as a 32-bit value
571 /// All bit fields as a 64-bit value
574 } MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER
;
578 Thread. Offcore Response Event Select Register (R/W).
580 @param ECX MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)
581 @param EAX Lower 32-bits of MSR value.
582 @param EDX Upper 32-bits of MSR value.
588 Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);
589 AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);
591 @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
593 #define MSR_NEHALEM_OFFCORE_RSP_0 0x000001A6
597 See http://biosbits.org.
599 @param ECX MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)
600 @param EAX Lower 32-bits of MSR value.
601 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
602 @param EDX Upper 32-bits of MSR value.
603 Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
607 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Msr;
609 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);
610 AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);
612 @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
614 #define MSR_NEHALEM_MISC_PWR_MGMT 0x000001AA
617 MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT
621 /// Individual bit fields
625 /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,
626 /// enables hardware coordination of Enhanced Intel Speedstep Technology
627 /// request from processor cores; When 1, disables hardware coordination
628 /// of Enhanced Intel Speedstep Technology requests.
630 UINT32 EISTHardwareCoordinationDisable
:1;
632 /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes
633 /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with
634 /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by
635 /// CPUID.(EAX=06h):ECX[3].
637 UINT32 EnergyPerformanceBiasEnable
:1;
642 /// All bit fields as a 32-bit value
646 /// All bit fields as a 64-bit value
649 } MSR_NEHALEM_MISC_PWR_MGMT_REGISTER
;
653 See http://biosbits.org.
655 @param ECX MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)
656 @param EAX Lower 32-bits of MSR value.
657 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
658 @param EDX Upper 32-bits of MSR value.
659 Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
663 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Msr;
665 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);
666 AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);
668 @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.
670 #define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT 0x000001AC
673 MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT
677 /// Individual bit fields
681 /// [Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt
686 /// [Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0
687 /// indicates override is not active, and a value = 1 indicates active.
689 UINT32 TDPLimitOverrideEnable
:1;
691 /// [Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp
696 /// [Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0
697 /// indicates override is not active, and a value = 1 indicates active.
699 UINT32 TDCLimitOverrideEnable
:1;
703 /// All bit fields as a 32-bit value
707 /// All bit fields as a 64-bit value
710 } MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
;
714 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
715 RW if MSR_PLATFORM_INFO.[28] = 1.
717 @param ECX MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)
718 @param EAX Lower 32-bits of MSR value.
719 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
720 @param EDX Upper 32-bits of MSR value.
721 Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
725 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Msr;
727 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);
729 @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
731 #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x000001AD
734 MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT
738 /// Individual bit fields
742 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
743 /// limit of 1 core active.
747 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
748 /// limit of 2 core active.
752 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
753 /// limit of 3 core active.
757 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
758 /// limit of 4 core active.
764 /// All bit fields as a 32-bit value
768 /// All bit fields as a 64-bit value
771 } MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER
;
775 Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
776 "Filtering of Last Branch Records.".
778 @param ECX MSR_NEHALEM_LBR_SELECT (0x000001C8)
779 @param EAX Lower 32-bits of MSR value.
780 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
781 @param EDX Upper 32-bits of MSR value.
782 Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
786 MSR_NEHALEM_LBR_SELECT_REGISTER Msr;
788 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);
789 AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);
791 @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
793 #define MSR_NEHALEM_LBR_SELECT 0x000001C8
796 MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT
800 /// Individual bit fields
804 /// [Bit 0] CPL_EQ_0.
808 /// [Bit 1] CPL_NEQ_0.
816 /// [Bit 3] NEAR_REL_CALL.
818 UINT32 NEAR_REL_CALL
:1;
820 /// [Bit 4] NEAR_IND_CALL.
822 UINT32 NEAR_IND_CALL
:1;
824 /// [Bit 5] NEAR_RET.
828 /// [Bit 6] NEAR_IND_JMP.
830 UINT32 NEAR_IND_JMP
:1;
832 /// [Bit 7] NEAR_REL_JMP.
834 UINT32 NEAR_REL_JMP
:1;
836 /// [Bit 8] FAR_BRANCH.
843 /// All bit fields as a 32-bit value
847 /// All bit fields as a 64-bit value
850 } MSR_NEHALEM_LBR_SELECT_REGISTER
;
854 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
855 that points to the MSR containing the most recent branch record. See
856 MSR_LASTBRANCH_0_FROM_IP (at 680H).
858 @param ECX MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)
859 @param EAX Lower 32-bits of MSR value.
860 @param EDX Upper 32-bits of MSR value.
866 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);
867 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);
869 @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
871 #define MSR_NEHALEM_LASTBRANCH_TOS 0x000001C9
875 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
876 last branch instruction that the processor executed prior to the last
877 exception that was generated or the last interrupt that was handled.
879 @param ECX MSR_NEHALEM_LER_FROM_LIP (0x000001DD)
880 @param EAX Lower 32-bits of MSR value.
881 @param EDX Upper 32-bits of MSR value.
887 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);
889 @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
891 #define MSR_NEHALEM_LER_FROM_LIP 0x000001DD
895 Thread. Last Exception Record To Linear IP (R) This area contains a pointer
896 to the target of the last branch instruction that the processor executed
897 prior to the last exception that was generated or the last interrupt that
900 @param ECX MSR_NEHALEM_LER_TO_LIP (0x000001DE)
901 @param EAX Lower 32-bits of MSR value.
902 @param EDX Upper 32-bits of MSR value.
908 Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);
910 @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
912 #define MSR_NEHALEM_LER_TO_LIP 0x000001DE
916 Core. Power Control Register. See http://biosbits.org.
918 @param ECX MSR_NEHALEM_POWER_CTL (0x000001FC)
919 @param EAX Lower 32-bits of MSR value.
920 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
921 @param EDX Upper 32-bits of MSR value.
922 Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
926 MSR_NEHALEM_POWER_CTL_REGISTER Msr;
928 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);
929 AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);
931 @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.
933 #define MSR_NEHALEM_POWER_CTL 0x000001FC
936 MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL
940 /// Individual bit fields
945 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the
946 /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
947 /// operating point when all execution cores enter MWAIT (C1).
954 /// All bit fields as a 32-bit value
958 /// All bit fields as a 64-bit value
961 } MSR_NEHALEM_POWER_CTL_REGISTER
;
967 @param ECX MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)
968 @param EAX Lower 32-bits of MSR value.
969 Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
970 @param EDX Upper 32-bits of MSR value.
971 Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
975 MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Msr;
977 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);
979 @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.
981 #define MSR_NEHALEM_PERF_GLOBAL_STATUS 0x0000038E
984 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS
988 /// Individual bit fields
994 /// [Bit 61] UNC_Ovf Uncore overflowed if 1.
1000 /// All bit fields as a 64-bit value
1003 } MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER
;
1009 @param ECX MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)
1010 @param EAX Lower 32-bits of MSR value.
1011 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
1012 @param EDX Upper 32-bits of MSR value.
1013 Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
1015 <b>Example usage</b>
1017 MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
1019 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);
1020 AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
1022 @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
1024 #define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL 0x00000390
1027 MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL
1031 /// Individual bit fields
1034 UINT32 Reserved1
:32;
1035 UINT32 Reserved2
:29;
1037 /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.
1039 UINT32 Ovf_Uncore
:1;
1043 /// All bit fields as a 64-bit value
1046 } MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER
;
1050 Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
1052 @param ECX MSR_NEHALEM_PEBS_ENABLE (0x000003F1)
1053 @param EAX Lower 32-bits of MSR value.
1054 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
1055 @param EDX Upper 32-bits of MSR value.
1056 Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
1058 <b>Example usage</b>
1060 MSR_NEHALEM_PEBS_ENABLE_REGISTER Msr;
1062 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);
1063 AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);
1065 @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1067 #define MSR_NEHALEM_PEBS_ENABLE 0x000003F1
1070 MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE
1074 /// Individual bit fields
1078 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1080 UINT32 PEBS_EN_PMC0
:1;
1082 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1084 UINT32 PEBS_EN_PMC1
:1;
1086 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1088 UINT32 PEBS_EN_PMC2
:1;
1090 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1092 UINT32 PEBS_EN_PMC3
:1;
1093 UINT32 Reserved1
:28;
1095 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1097 UINT32 LL_EN_PMC0
:1;
1099 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1101 UINT32 LL_EN_PMC1
:1;
1103 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1105 UINT32 LL_EN_PMC2
:1;
1107 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1109 UINT32 LL_EN_PMC3
:1;
1110 UINT32 Reserved2
:28;
1113 /// All bit fields as a 64-bit value
1116 } MSR_NEHALEM_PEBS_ENABLE_REGISTER
;
1120 Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring
1123 @param ECX MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)
1124 @param EAX Lower 32-bits of MSR value.
1125 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
1126 @param EDX Upper 32-bits of MSR value.
1127 Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
1129 <b>Example usage</b>
1131 MSR_NEHALEM_PEBS_LD_LAT_REGISTER Msr;
1133 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);
1134 AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);
1136 @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
1138 #define MSR_NEHALEM_PEBS_LD_LAT 0x000003F6
1141 MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT
1145 /// Individual bit fields
1149 /// [Bits 15:0] Minimum threshold latency value of tagged load operation
1150 /// that will be counted. (R/W).
1152 UINT32 MinimumThreshold
:16;
1153 UINT32 Reserved1
:16;
1154 UINT32 Reserved2
:32;
1157 /// All bit fields as a 32-bit value
1161 /// All bit fields as a 64-bit value
1164 } MSR_NEHALEM_PEBS_LD_LAT_REGISTER
;
1168 Package. Note: C-state values are processor specific C-state code names,
1169 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1170 Residency Counter. (R/O) Value since last reset that this package is in
1171 processor-specific C3 states. Count at the same frequency as the TSC.
1173 @param ECX MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)
1174 @param EAX Lower 32-bits of MSR value.
1175 @param EDX Upper 32-bits of MSR value.
1177 <b>Example usage</b>
1181 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);
1182 AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);
1184 @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1186 #define MSR_NEHALEM_PKG_C3_RESIDENCY 0x000003F8
1190 Package. Note: C-state values are processor specific C-state code names,
1191 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1192 Residency Counter. (R/O) Value since last reset that this package is in
1193 processor-specific C6 states. Count at the same frequency as the TSC.
1195 @param ECX MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)
1196 @param EAX Lower 32-bits of MSR value.
1197 @param EDX Upper 32-bits of MSR value.
1199 <b>Example usage</b>
1203 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);
1204 AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);
1206 @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1208 #define MSR_NEHALEM_PKG_C6_RESIDENCY 0x000003F9
1212 Package. Note: C-state values are processor specific C-state code names,
1213 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
1214 Residency Counter. (R/O) Value since last reset that this package is in
1215 processor-specific C7 states. Count at the same frequency as the TSC.
1217 @param ECX MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)
1218 @param EAX Lower 32-bits of MSR value.
1219 @param EDX Upper 32-bits of MSR value.
1221 <b>Example usage</b>
1225 Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);
1226 AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);
1228 @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1230 #define MSR_NEHALEM_PKG_C7_RESIDENCY 0x000003FA
1234 Core. Note: C-state values are processor specific C-state code names,
1235 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1236 Residency Counter. (R/O) Value since last reset that this core is in
1237 processor-specific C3 states. Count at the same frequency as the TSC.
1239 @param ECX MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)
1240 @param EAX Lower 32-bits of MSR value.
1241 @param EDX Upper 32-bits of MSR value.
1243 <b>Example usage</b>
1247 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);
1248 AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);
1250 @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
1252 #define MSR_NEHALEM_CORE_C3_RESIDENCY 0x000003FC
1256 Core. Note: C-state values are processor specific C-state code names,
1257 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1258 Residency Counter. (R/O) Value since last reset that this core is in
1259 processor-specific C6 states. Count at the same frequency as the TSC.
1261 @param ECX MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)
1262 @param EAX Lower 32-bits of MSR value.
1263 @param EDX Upper 32-bits of MSR value.
1265 <b>Example usage</b>
1269 Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);
1270 AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);
1272 @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1274 #define MSR_NEHALEM_CORE_C6_RESIDENCY 0x000003FD
1278 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
1279 branch record registers on the last branch record stack. The From_IP part of
1280 the stack contains pointers to the source instruction. See also: - Last
1281 Branch Record Stack TOS at 1C9H - Section 17.7.1 and record format in
1284 @param ECX MSR_NEHALEM_LASTBRANCH_n_FROM_IP
1285 @param EAX Lower 32-bits of MSR value.
1286 @param EDX Upper 32-bits of MSR value.
1288 <b>Example usage</b>
1292 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
1293 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);
1295 @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
1296 MSR_NEHALEM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
1297 MSR_NEHALEM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
1298 MSR_NEHALEM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
1299 MSR_NEHALEM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
1300 MSR_NEHALEM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
1301 MSR_NEHALEM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
1302 MSR_NEHALEM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
1303 MSR_NEHALEM_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
1304 MSR_NEHALEM_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
1305 MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
1306 MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
1307 MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
1308 MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
1309 MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
1310 MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
1313 #define MSR_NEHALEM_LASTBRANCH_0_FROM_IP 0x00000680
1314 #define MSR_NEHALEM_LASTBRANCH_1_FROM_IP 0x00000681
1315 #define MSR_NEHALEM_LASTBRANCH_2_FROM_IP 0x00000682
1316 #define MSR_NEHALEM_LASTBRANCH_3_FROM_IP 0x00000683
1317 #define MSR_NEHALEM_LASTBRANCH_4_FROM_IP 0x00000684
1318 #define MSR_NEHALEM_LASTBRANCH_5_FROM_IP 0x00000685
1319 #define MSR_NEHALEM_LASTBRANCH_6_FROM_IP 0x00000686
1320 #define MSR_NEHALEM_LASTBRANCH_7_FROM_IP 0x00000687
1321 #define MSR_NEHALEM_LASTBRANCH_8_FROM_IP 0x00000688
1322 #define MSR_NEHALEM_LASTBRANCH_9_FROM_IP 0x00000689
1323 #define MSR_NEHALEM_LASTBRANCH_10_FROM_IP 0x0000068A
1324 #define MSR_NEHALEM_LASTBRANCH_11_FROM_IP 0x0000068B
1325 #define MSR_NEHALEM_LASTBRANCH_12_FROM_IP 0x0000068C
1326 #define MSR_NEHALEM_LASTBRANCH_13_FROM_IP 0x0000068D
1327 #define MSR_NEHALEM_LASTBRANCH_14_FROM_IP 0x0000068E
1328 #define MSR_NEHALEM_LASTBRANCH_15_FROM_IP 0x0000068F
1333 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
1334 record registers on the last branch record stack. This part of the stack
1335 contains pointers to the destination instruction.
1337 @param ECX MSR_NEHALEM_LASTBRANCH_n_TO_IP
1338 @param EAX Lower 32-bits of MSR value.
1339 @param EDX Upper 32-bits of MSR value.
1341 <b>Example usage</b>
1345 Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
1346 AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);
1348 @note MSR_NEHALEM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
1349 MSR_NEHALEM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
1350 MSR_NEHALEM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
1351 MSR_NEHALEM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
1352 MSR_NEHALEM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
1353 MSR_NEHALEM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
1354 MSR_NEHALEM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
1355 MSR_NEHALEM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
1356 MSR_NEHALEM_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
1357 MSR_NEHALEM_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
1358 MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
1359 MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
1360 MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
1361 MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
1362 MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
1363 MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
1366 #define MSR_NEHALEM_LASTBRANCH_0_TO_IP 0x000006C0
1367 #define MSR_NEHALEM_LASTBRANCH_1_TO_IP 0x000006C1
1368 #define MSR_NEHALEM_LASTBRANCH_2_TO_IP 0x000006C2
1369 #define MSR_NEHALEM_LASTBRANCH_3_TO_IP 0x000006C3
1370 #define MSR_NEHALEM_LASTBRANCH_4_TO_IP 0x000006C4
1371 #define MSR_NEHALEM_LASTBRANCH_5_TO_IP 0x000006C5
1372 #define MSR_NEHALEM_LASTBRANCH_6_TO_IP 0x000006C6
1373 #define MSR_NEHALEM_LASTBRANCH_7_TO_IP 0x000006C7
1374 #define MSR_NEHALEM_LASTBRANCH_8_TO_IP 0x000006C8
1375 #define MSR_NEHALEM_LASTBRANCH_9_TO_IP 0x000006C9
1376 #define MSR_NEHALEM_LASTBRANCH_10_TO_IP 0x000006CA
1377 #define MSR_NEHALEM_LASTBRANCH_11_TO_IP 0x000006CB
1378 #define MSR_NEHALEM_LASTBRANCH_12_TO_IP 0x000006CC
1379 #define MSR_NEHALEM_LASTBRANCH_13_TO_IP 0x000006CD
1380 #define MSR_NEHALEM_LASTBRANCH_14_TO_IP 0x000006CE
1381 #define MSR_NEHALEM_LASTBRANCH_15_TO_IP 0x000006CF
1388 @param ECX MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)
1389 @param EAX Lower 32-bits of MSR value.
1390 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
1391 @param EDX Upper 32-bits of MSR value.
1392 Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
1394 <b>Example usage</b>
1396 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Msr;
1398 Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);
1399 AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);
1401 @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.
1403 #define MSR_NEHALEM_GQ_SNOOP_MESF 0x00000301
1406 MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF
1410 /// Individual bit fields
1414 /// [Bit 0] From M to S (R/W).
1418 /// [Bit 1] From E to S (R/W).
1422 /// [Bit 2] From S to S (R/W).
1426 /// [Bit 3] From F to S (R/W).
1430 /// [Bit 4] From M to I (R/W).
1434 /// [Bit 5] From E to I (R/W).
1438 /// [Bit 6] From S to I (R/W).
1442 /// [Bit 7] From F to I (R/W).
1445 UINT32 Reserved1
:24;
1446 UINT32 Reserved2
:32;
1449 /// All bit fields as a 32-bit value
1453 /// All bit fields as a 64-bit value
1456 } MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
;
1460 Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
1463 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)
1464 @param EAX Lower 32-bits of MSR value.
1465 @param EDX Upper 32-bits of MSR value.
1467 <b>Example usage</b>
1471 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);
1472 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);
1474 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.
1476 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL 0x00000391
1480 Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
1483 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)
1484 @param EAX Lower 32-bits of MSR value.
1485 @param EDX Upper 32-bits of MSR value.
1487 <b>Example usage</b>
1491 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);
1492 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);
1494 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.
1496 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS 0x00000392
1500 Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
1503 @param ECX MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)
1504 @param EAX Lower 32-bits of MSR value.
1505 @param EDX Upper 32-bits of MSR value.
1507 <b>Example usage</b>
1511 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);
1512 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);
1514 @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM.
1516 #define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL 0x00000393
1520 Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
1523 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)
1524 @param EAX Lower 32-bits of MSR value.
1525 @param EDX Upper 32-bits of MSR value.
1527 <b>Example usage</b>
1531 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);
1532 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);
1534 @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.
1536 #define MSR_NEHALEM_UNCORE_FIXED_CTR0 0x00000394
1540 Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
1543 @param ECX MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)
1544 @param EAX Lower 32-bits of MSR value.
1545 @param EDX Upper 32-bits of MSR value.
1547 <b>Example usage</b>
1551 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);
1552 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);
1554 @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.
1556 #define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL 0x00000395
1560 Package. See Section 18.3.1.2.3, "Uncore Address/Opcode Match MSR.".
1562 @param ECX MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)
1563 @param EAX Lower 32-bits of MSR value.
1564 @param EDX Upper 32-bits of MSR value.
1566 <b>Example usage</b>
1570 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);
1571 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);
1573 @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.
1575 #define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH 0x00000396
1579 Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration
1582 @param ECX MSR_NEHALEM_UNCORE_PMCi
1583 @param EAX Lower 32-bits of MSR value.
1584 @param EDX Upper 32-bits of MSR value.
1586 <b>Example usage</b>
1590 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
1591 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);
1593 @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM.
1594 MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM.
1595 MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM.
1596 MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM.
1597 MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM.
1598 MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM.
1599 MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM.
1600 MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.
1603 #define MSR_NEHALEM_UNCORE_PMC0 0x000003B0
1604 #define MSR_NEHALEM_UNCORE_PMC1 0x000003B1
1605 #define MSR_NEHALEM_UNCORE_PMC2 0x000003B2
1606 #define MSR_NEHALEM_UNCORE_PMC3 0x000003B3
1607 #define MSR_NEHALEM_UNCORE_PMC4 0x000003B4
1608 #define MSR_NEHALEM_UNCORE_PMC5 0x000003B5
1609 #define MSR_NEHALEM_UNCORE_PMC6 0x000003B6
1610 #define MSR_NEHALEM_UNCORE_PMC7 0x000003B7
1614 Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration
1617 @param ECX MSR_NEHALEM_UNCORE_PERFEVTSELi
1618 @param EAX Lower 32-bits of MSR value.
1619 @param EDX Upper 32-bits of MSR value.
1621 <b>Example usage</b>
1625 Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
1626 AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);
1628 @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM.
1629 MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM.
1630 MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM.
1631 MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM.
1632 MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM.
1633 MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM.
1634 MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM.
1635 MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.
1638 #define MSR_NEHALEM_UNCORE_PERFEVTSEL0 0x000003C0
1639 #define MSR_NEHALEM_UNCORE_PERFEVTSEL1 0x000003C1
1640 #define MSR_NEHALEM_UNCORE_PERFEVTSEL2 0x000003C2
1641 #define MSR_NEHALEM_UNCORE_PERFEVTSEL3 0x000003C3
1642 #define MSR_NEHALEM_UNCORE_PERFEVTSEL4 0x000003C4
1643 #define MSR_NEHALEM_UNCORE_PERFEVTSEL5 0x000003C5
1644 #define MSR_NEHALEM_UNCORE_PERFEVTSEL6 0x000003C6
1645 #define MSR_NEHALEM_UNCORE_PERFEVTSEL7 0x000003C7
1650 Package. Uncore W-box perfmon fixed counter.
1652 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)
1653 @param EAX Lower 32-bits of MSR value.
1654 @param EDX Upper 32-bits of MSR value.
1656 <b>Example usage</b>
1660 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);
1661 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);
1663 @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.
1665 #define MSR_NEHALEM_W_PMON_FIXED_CTR 0x00000394
1669 Package. Uncore U-box perfmon fixed counter control MSR.
1671 @param ECX MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)
1672 @param EAX Lower 32-bits of MSR value.
1673 @param EDX Upper 32-bits of MSR value.
1675 <b>Example usage</b>
1679 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);
1680 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);
1682 @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.
1684 #define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL 0x00000395
1688 Package. Uncore U-box perfmon global control MSR.
1690 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)
1691 @param EAX Lower 32-bits of MSR value.
1692 @param EDX Upper 32-bits of MSR value.
1694 <b>Example usage</b>
1698 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);
1699 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);
1701 @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.
1703 #define MSR_NEHALEM_U_PMON_GLOBAL_CTRL 0x00000C00
1707 Package. Uncore U-box perfmon global status MSR.
1709 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)
1710 @param EAX Lower 32-bits of MSR value.
1711 @param EDX Upper 32-bits of MSR value.
1713 <b>Example usage</b>
1717 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);
1718 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);
1720 @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.
1722 #define MSR_NEHALEM_U_PMON_GLOBAL_STATUS 0x00000C01
1726 Package. Uncore U-box perfmon global overflow control MSR.
1728 @param ECX MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)
1729 @param EAX Lower 32-bits of MSR value.
1730 @param EDX Upper 32-bits of MSR value.
1732 <b>Example usage</b>
1736 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);
1737 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);
1739 @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.
1741 #define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL 0x00000C02
1745 Package. Uncore U-box perfmon event select MSR.
1747 @param ECX MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)
1748 @param EAX Lower 32-bits of MSR value.
1749 @param EDX Upper 32-bits of MSR value.
1751 <b>Example usage</b>
1755 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);
1756 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);
1758 @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.
1760 #define MSR_NEHALEM_U_PMON_EVNT_SEL 0x00000C10
1764 Package. Uncore U-box perfmon counter MSR.
1766 @param ECX MSR_NEHALEM_U_PMON_CTR (0x00000C11)
1767 @param EAX Lower 32-bits of MSR value.
1768 @param EDX Upper 32-bits of MSR value.
1770 <b>Example usage</b>
1774 Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);
1775 AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);
1777 @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.
1779 #define MSR_NEHALEM_U_PMON_CTR 0x00000C11
1783 Package. Uncore B-box 0 perfmon local box control MSR.
1785 @param ECX MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)
1786 @param EAX Lower 32-bits of MSR value.
1787 @param EDX Upper 32-bits of MSR value.
1789 <b>Example usage</b>
1793 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);
1794 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);
1796 @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.
1798 #define MSR_NEHALEM_B0_PMON_BOX_CTRL 0x00000C20
1802 Package. Uncore B-box 0 perfmon local box status MSR.
1804 @param ECX MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)
1805 @param EAX Lower 32-bits of MSR value.
1806 @param EDX Upper 32-bits of MSR value.
1808 <b>Example usage</b>
1812 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);
1813 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);
1815 @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.
1817 #define MSR_NEHALEM_B0_PMON_BOX_STATUS 0x00000C21
1821 Package. Uncore B-box 0 perfmon local box overflow control MSR.
1823 @param ECX MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)
1824 @param EAX Lower 32-bits of MSR value.
1825 @param EDX Upper 32-bits of MSR value.
1827 <b>Example usage</b>
1831 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);
1832 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);
1834 @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.
1836 #define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL 0x00000C22
1840 Package. Uncore B-box 0 perfmon event select MSR.
1842 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)
1843 @param EAX Lower 32-bits of MSR value.
1844 @param EDX Upper 32-bits of MSR value.
1846 <b>Example usage</b>
1850 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);
1851 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);
1853 @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.
1855 #define MSR_NEHALEM_B0_PMON_EVNT_SEL0 0x00000C30
1859 Package. Uncore B-box 0 perfmon counter MSR.
1861 @param ECX MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)
1862 @param EAX Lower 32-bits of MSR value.
1863 @param EDX Upper 32-bits of MSR value.
1865 <b>Example usage</b>
1869 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);
1870 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);
1872 @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.
1874 #define MSR_NEHALEM_B0_PMON_CTR0 0x00000C31
1878 Package. Uncore B-box 0 perfmon event select MSR.
1880 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)
1881 @param EAX Lower 32-bits of MSR value.
1882 @param EDX Upper 32-bits of MSR value.
1884 <b>Example usage</b>
1888 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);
1889 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);
1891 @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.
1893 #define MSR_NEHALEM_B0_PMON_EVNT_SEL1 0x00000C32
1897 Package. Uncore B-box 0 perfmon counter MSR.
1899 @param ECX MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)
1900 @param EAX Lower 32-bits of MSR value.
1901 @param EDX Upper 32-bits of MSR value.
1903 <b>Example usage</b>
1907 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);
1908 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);
1910 @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.
1912 #define MSR_NEHALEM_B0_PMON_CTR1 0x00000C33
1916 Package. Uncore B-box 0 perfmon event select MSR.
1918 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)
1919 @param EAX Lower 32-bits of MSR value.
1920 @param EDX Upper 32-bits of MSR value.
1922 <b>Example usage</b>
1926 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);
1927 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);
1929 @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.
1931 #define MSR_NEHALEM_B0_PMON_EVNT_SEL2 0x00000C34
1935 Package. Uncore B-box 0 perfmon counter MSR.
1937 @param ECX MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)
1938 @param EAX Lower 32-bits of MSR value.
1939 @param EDX Upper 32-bits of MSR value.
1941 <b>Example usage</b>
1945 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);
1946 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);
1948 @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.
1950 #define MSR_NEHALEM_B0_PMON_CTR2 0x00000C35
1954 Package. Uncore B-box 0 perfmon event select MSR.
1956 @param ECX MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)
1957 @param EAX Lower 32-bits of MSR value.
1958 @param EDX Upper 32-bits of MSR value.
1960 <b>Example usage</b>
1964 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);
1965 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);
1967 @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.
1969 #define MSR_NEHALEM_B0_PMON_EVNT_SEL3 0x00000C36
1973 Package. Uncore B-box 0 perfmon counter MSR.
1975 @param ECX MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)
1976 @param EAX Lower 32-bits of MSR value.
1977 @param EDX Upper 32-bits of MSR value.
1979 <b>Example usage</b>
1983 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);
1984 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);
1986 @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.
1988 #define MSR_NEHALEM_B0_PMON_CTR3 0x00000C37
1992 Package. Uncore S-box 0 perfmon local box control MSR.
1994 @param ECX MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)
1995 @param EAX Lower 32-bits of MSR value.
1996 @param EDX Upper 32-bits of MSR value.
1998 <b>Example usage</b>
2002 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);
2003 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);
2005 @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.
2007 #define MSR_NEHALEM_S0_PMON_BOX_CTRL 0x00000C40
2011 Package. Uncore S-box 0 perfmon local box status MSR.
2013 @param ECX MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)
2014 @param EAX Lower 32-bits of MSR value.
2015 @param EDX Upper 32-bits of MSR value.
2017 <b>Example usage</b>
2021 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);
2022 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);
2024 @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.
2026 #define MSR_NEHALEM_S0_PMON_BOX_STATUS 0x00000C41
2030 Package. Uncore S-box 0 perfmon local box overflow control MSR.
2032 @param ECX MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)
2033 @param EAX Lower 32-bits of MSR value.
2034 @param EDX Upper 32-bits of MSR value.
2036 <b>Example usage</b>
2040 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);
2041 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);
2043 @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.
2045 #define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL 0x00000C42
2049 Package. Uncore S-box 0 perfmon event select MSR.
2051 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)
2052 @param EAX Lower 32-bits of MSR value.
2053 @param EDX Upper 32-bits of MSR value.
2055 <b>Example usage</b>
2059 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);
2060 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);
2062 @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.
2064 #define MSR_NEHALEM_S0_PMON_EVNT_SEL0 0x00000C50
2068 Package. Uncore S-box 0 perfmon counter MSR.
2070 @param ECX MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)
2071 @param EAX Lower 32-bits of MSR value.
2072 @param EDX Upper 32-bits of MSR value.
2074 <b>Example usage</b>
2078 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);
2079 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);
2081 @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
2083 #define MSR_NEHALEM_S0_PMON_CTR0 0x00000C51
2087 Package. Uncore S-box 0 perfmon event select MSR.
2089 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)
2090 @param EAX Lower 32-bits of MSR value.
2091 @param EDX Upper 32-bits of MSR value.
2093 <b>Example usage</b>
2097 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);
2098 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);
2100 @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.
2102 #define MSR_NEHALEM_S0_PMON_EVNT_SEL1 0x00000C52
2106 Package. Uncore S-box 0 perfmon counter MSR.
2108 @param ECX MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)
2109 @param EAX Lower 32-bits of MSR value.
2110 @param EDX Upper 32-bits of MSR value.
2112 <b>Example usage</b>
2116 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);
2117 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);
2119 @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
2121 #define MSR_NEHALEM_S0_PMON_CTR1 0x00000C53
2125 Package. Uncore S-box 0 perfmon event select MSR.
2127 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)
2128 @param EAX Lower 32-bits of MSR value.
2129 @param EDX Upper 32-bits of MSR value.
2131 <b>Example usage</b>
2135 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);
2136 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);
2138 @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.
2140 #define MSR_NEHALEM_S0_PMON_EVNT_SEL2 0x00000C54
2144 Package. Uncore S-box 0 perfmon counter MSR.
2146 @param ECX MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)
2147 @param EAX Lower 32-bits of MSR value.
2148 @param EDX Upper 32-bits of MSR value.
2150 <b>Example usage</b>
2154 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);
2155 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);
2157 @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
2159 #define MSR_NEHALEM_S0_PMON_CTR2 0x00000C55
2163 Package. Uncore S-box 0 perfmon event select MSR.
2165 @param ECX MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)
2166 @param EAX Lower 32-bits of MSR value.
2167 @param EDX Upper 32-bits of MSR value.
2169 <b>Example usage</b>
2173 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);
2174 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);
2176 @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.
2178 #define MSR_NEHALEM_S0_PMON_EVNT_SEL3 0x00000C56
2182 Package. Uncore S-box 0 perfmon counter MSR.
2184 @param ECX MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)
2185 @param EAX Lower 32-bits of MSR value.
2186 @param EDX Upper 32-bits of MSR value.
2188 <b>Example usage</b>
2192 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);
2193 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);
2195 @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
2197 #define MSR_NEHALEM_S0_PMON_CTR3 0x00000C57
2201 Package. Uncore B-box 1 perfmon local box control MSR.
2203 @param ECX MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)
2204 @param EAX Lower 32-bits of MSR value.
2205 @param EDX Upper 32-bits of MSR value.
2207 <b>Example usage</b>
2211 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);
2212 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);
2214 @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.
2216 #define MSR_NEHALEM_B1_PMON_BOX_CTRL 0x00000C60
2220 Package. Uncore B-box 1 perfmon local box status MSR.
2222 @param ECX MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)
2223 @param EAX Lower 32-bits of MSR value.
2224 @param EDX Upper 32-bits of MSR value.
2226 <b>Example usage</b>
2230 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);
2231 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);
2233 @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.
2235 #define MSR_NEHALEM_B1_PMON_BOX_STATUS 0x00000C61
2239 Package. Uncore B-box 1 perfmon local box overflow control MSR.
2241 @param ECX MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)
2242 @param EAX Lower 32-bits of MSR value.
2243 @param EDX Upper 32-bits of MSR value.
2245 <b>Example usage</b>
2249 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);
2250 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);
2252 @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.
2254 #define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL 0x00000C62
2258 Package. Uncore B-box 1 perfmon event select MSR.
2260 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)
2261 @param EAX Lower 32-bits of MSR value.
2262 @param EDX Upper 32-bits of MSR value.
2264 <b>Example usage</b>
2268 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);
2269 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);
2271 @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.
2273 #define MSR_NEHALEM_B1_PMON_EVNT_SEL0 0x00000C70
2277 Package. Uncore B-box 1 perfmon counter MSR.
2279 @param ECX MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)
2280 @param EAX Lower 32-bits of MSR value.
2281 @param EDX Upper 32-bits of MSR value.
2283 <b>Example usage</b>
2287 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);
2288 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);
2290 @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.
2292 #define MSR_NEHALEM_B1_PMON_CTR0 0x00000C71
2296 Package. Uncore B-box 1 perfmon event select MSR.
2298 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)
2299 @param EAX Lower 32-bits of MSR value.
2300 @param EDX Upper 32-bits of MSR value.
2302 <b>Example usage</b>
2306 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);
2307 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);
2309 @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.
2311 #define MSR_NEHALEM_B1_PMON_EVNT_SEL1 0x00000C72
2315 Package. Uncore B-box 1 perfmon counter MSR.
2317 @param ECX MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)
2318 @param EAX Lower 32-bits of MSR value.
2319 @param EDX Upper 32-bits of MSR value.
2321 <b>Example usage</b>
2325 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);
2326 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);
2328 @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.
2330 #define MSR_NEHALEM_B1_PMON_CTR1 0x00000C73
2334 Package. Uncore B-box 1 perfmon event select MSR.
2336 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)
2337 @param EAX Lower 32-bits of MSR value.
2338 @param EDX Upper 32-bits of MSR value.
2340 <b>Example usage</b>
2344 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);
2345 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);
2347 @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.
2349 #define MSR_NEHALEM_B1_PMON_EVNT_SEL2 0x00000C74
2353 Package. Uncore B-box 1 perfmon counter MSR.
2355 @param ECX MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)
2356 @param EAX Lower 32-bits of MSR value.
2357 @param EDX Upper 32-bits of MSR value.
2359 <b>Example usage</b>
2363 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);
2364 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);
2366 @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.
2368 #define MSR_NEHALEM_B1_PMON_CTR2 0x00000C75
2372 Package. Uncore B-box 1vperfmon event select MSR.
2374 @param ECX MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)
2375 @param EAX Lower 32-bits of MSR value.
2376 @param EDX Upper 32-bits of MSR value.
2378 <b>Example usage</b>
2382 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);
2383 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);
2385 @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.
2387 #define MSR_NEHALEM_B1_PMON_EVNT_SEL3 0x00000C76
2391 Package. Uncore B-box 1 perfmon counter MSR.
2393 @param ECX MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)
2394 @param EAX Lower 32-bits of MSR value.
2395 @param EDX Upper 32-bits of MSR value.
2397 <b>Example usage</b>
2401 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);
2402 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);
2404 @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.
2406 #define MSR_NEHALEM_B1_PMON_CTR3 0x00000C77
2410 Package. Uncore W-box perfmon local box control MSR.
2412 @param ECX MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)
2413 @param EAX Lower 32-bits of MSR value.
2414 @param EDX Upper 32-bits of MSR value.
2416 <b>Example usage</b>
2420 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);
2421 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);
2423 @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.
2425 #define MSR_NEHALEM_W_PMON_BOX_CTRL 0x00000C80
2429 Package. Uncore W-box perfmon local box status MSR.
2431 @param ECX MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)
2432 @param EAX Lower 32-bits of MSR value.
2433 @param EDX Upper 32-bits of MSR value.
2435 <b>Example usage</b>
2439 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);
2440 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);
2442 @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.
2444 #define MSR_NEHALEM_W_PMON_BOX_STATUS 0x00000C81
2448 Package. Uncore W-box perfmon local box overflow control MSR.
2450 @param ECX MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)
2451 @param EAX Lower 32-bits of MSR value.
2452 @param EDX Upper 32-bits of MSR value.
2454 <b>Example usage</b>
2458 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);
2459 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);
2461 @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.
2463 #define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL 0x00000C82
2467 Package. Uncore W-box perfmon event select MSR.
2469 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)
2470 @param EAX Lower 32-bits of MSR value.
2471 @param EDX Upper 32-bits of MSR value.
2473 <b>Example usage</b>
2477 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);
2478 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);
2480 @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.
2482 #define MSR_NEHALEM_W_PMON_EVNT_SEL0 0x00000C90
2486 Package. Uncore W-box perfmon counter MSR.
2488 @param ECX MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)
2489 @param EAX Lower 32-bits of MSR value.
2490 @param EDX Upper 32-bits of MSR value.
2492 <b>Example usage</b>
2496 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);
2497 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);
2499 @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.
2501 #define MSR_NEHALEM_W_PMON_CTR0 0x00000C91
2505 Package. Uncore W-box perfmon event select MSR.
2507 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)
2508 @param EAX Lower 32-bits of MSR value.
2509 @param EDX Upper 32-bits of MSR value.
2511 <b>Example usage</b>
2515 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);
2516 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);
2518 @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.
2520 #define MSR_NEHALEM_W_PMON_EVNT_SEL1 0x00000C92
2524 Package. Uncore W-box perfmon counter MSR.
2526 @param ECX MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)
2527 @param EAX Lower 32-bits of MSR value.
2528 @param EDX Upper 32-bits of MSR value.
2530 <b>Example usage</b>
2534 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);
2535 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);
2537 @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.
2539 #define MSR_NEHALEM_W_PMON_CTR1 0x00000C93
2543 Package. Uncore W-box perfmon event select MSR.
2545 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)
2546 @param EAX Lower 32-bits of MSR value.
2547 @param EDX Upper 32-bits of MSR value.
2549 <b>Example usage</b>
2553 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);
2554 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);
2556 @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.
2558 #define MSR_NEHALEM_W_PMON_EVNT_SEL2 0x00000C94
2562 Package. Uncore W-box perfmon counter MSR.
2564 @param ECX MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)
2565 @param EAX Lower 32-bits of MSR value.
2566 @param EDX Upper 32-bits of MSR value.
2568 <b>Example usage</b>
2572 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);
2573 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);
2575 @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.
2577 #define MSR_NEHALEM_W_PMON_CTR2 0x00000C95
2581 Package. Uncore W-box perfmon event select MSR.
2583 @param ECX MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)
2584 @param EAX Lower 32-bits of MSR value.
2585 @param EDX Upper 32-bits of MSR value.
2587 <b>Example usage</b>
2591 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);
2592 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);
2594 @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.
2596 #define MSR_NEHALEM_W_PMON_EVNT_SEL3 0x00000C96
2600 Package. Uncore W-box perfmon counter MSR.
2602 @param ECX MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)
2603 @param EAX Lower 32-bits of MSR value.
2604 @param EDX Upper 32-bits of MSR value.
2606 <b>Example usage</b>
2610 Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);
2611 AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);
2613 @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.
2615 #define MSR_NEHALEM_W_PMON_CTR3 0x00000C97
2619 Package. Uncore M-box 0 perfmon local box control MSR.
2621 @param ECX MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)
2622 @param EAX Lower 32-bits of MSR value.
2623 @param EDX Upper 32-bits of MSR value.
2625 <b>Example usage</b>
2629 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);
2630 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);
2632 @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.
2634 #define MSR_NEHALEM_M0_PMON_BOX_CTRL 0x00000CA0
2638 Package. Uncore M-box 0 perfmon local box status MSR.
2640 @param ECX MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)
2641 @param EAX Lower 32-bits of MSR value.
2642 @param EDX Upper 32-bits of MSR value.
2644 <b>Example usage</b>
2648 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);
2649 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);
2651 @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.
2653 #define MSR_NEHALEM_M0_PMON_BOX_STATUS 0x00000CA1
2657 Package. Uncore M-box 0 perfmon local box overflow control MSR.
2659 @param ECX MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)
2660 @param EAX Lower 32-bits of MSR value.
2661 @param EDX Upper 32-bits of MSR value.
2663 <b>Example usage</b>
2667 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);
2668 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);
2670 @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.
2672 #define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL 0x00000CA2
2676 Package. Uncore M-box 0 perfmon time stamp unit select MSR.
2678 @param ECX MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)
2679 @param EAX Lower 32-bits of MSR value.
2680 @param EDX Upper 32-bits of MSR value.
2682 <b>Example usage</b>
2686 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);
2687 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);
2689 @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.
2691 #define MSR_NEHALEM_M0_PMON_TIMESTAMP 0x00000CA4
2695 Package. Uncore M-box 0 perfmon DSP unit select MSR.
2697 @param ECX MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)
2698 @param EAX Lower 32-bits of MSR value.
2699 @param EDX Upper 32-bits of MSR value.
2701 <b>Example usage</b>
2705 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);
2706 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);
2708 @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.
2710 #define MSR_NEHALEM_M0_PMON_DSP 0x00000CA5
2714 Package. Uncore M-box 0 perfmon ISS unit select MSR.
2716 @param ECX MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)
2717 @param EAX Lower 32-bits of MSR value.
2718 @param EDX Upper 32-bits of MSR value.
2720 <b>Example usage</b>
2724 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);
2725 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);
2727 @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.
2729 #define MSR_NEHALEM_M0_PMON_ISS 0x00000CA6
2733 Package. Uncore M-box 0 perfmon MAP unit select MSR.
2735 @param ECX MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)
2736 @param EAX Lower 32-bits of MSR value.
2737 @param EDX Upper 32-bits of MSR value.
2739 <b>Example usage</b>
2743 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);
2744 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);
2746 @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.
2748 #define MSR_NEHALEM_M0_PMON_MAP 0x00000CA7
2752 Package. Uncore M-box 0 perfmon MIC THR select MSR.
2754 @param ECX MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)
2755 @param EAX Lower 32-bits of MSR value.
2756 @param EDX Upper 32-bits of MSR value.
2758 <b>Example usage</b>
2762 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);
2763 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);
2765 @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.
2767 #define MSR_NEHALEM_M0_PMON_MSC_THR 0x00000CA8
2771 Package. Uncore M-box 0 perfmon PGT unit select MSR.
2773 @param ECX MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)
2774 @param EAX Lower 32-bits of MSR value.
2775 @param EDX Upper 32-bits of MSR value.
2777 <b>Example usage</b>
2781 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);
2782 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);
2784 @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.
2786 #define MSR_NEHALEM_M0_PMON_PGT 0x00000CA9
2790 Package. Uncore M-box 0 perfmon PLD unit select MSR.
2792 @param ECX MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)
2793 @param EAX Lower 32-bits of MSR value.
2794 @param EDX Upper 32-bits of MSR value.
2796 <b>Example usage</b>
2800 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);
2801 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);
2803 @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.
2805 #define MSR_NEHALEM_M0_PMON_PLD 0x00000CAA
2809 Package. Uncore M-box 0 perfmon ZDP unit select MSR.
2811 @param ECX MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)
2812 @param EAX Lower 32-bits of MSR value.
2813 @param EDX Upper 32-bits of MSR value.
2815 <b>Example usage</b>
2819 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);
2820 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);
2822 @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.
2824 #define MSR_NEHALEM_M0_PMON_ZDP 0x00000CAB
2828 Package. Uncore M-box 0 perfmon event select MSR.
2830 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)
2831 @param EAX Lower 32-bits of MSR value.
2832 @param EDX Upper 32-bits of MSR value.
2834 <b>Example usage</b>
2838 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);
2839 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);
2841 @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.
2843 #define MSR_NEHALEM_M0_PMON_EVNT_SEL0 0x00000CB0
2847 Package. Uncore M-box 0 perfmon counter MSR.
2849 @param ECX MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)
2850 @param EAX Lower 32-bits of MSR value.
2851 @param EDX Upper 32-bits of MSR value.
2853 <b>Example usage</b>
2857 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);
2858 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);
2860 @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.
2862 #define MSR_NEHALEM_M0_PMON_CTR0 0x00000CB1
2866 Package. Uncore M-box 0 perfmon event select MSR.
2868 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)
2869 @param EAX Lower 32-bits of MSR value.
2870 @param EDX Upper 32-bits of MSR value.
2872 <b>Example usage</b>
2876 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);
2877 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);
2879 @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.
2881 #define MSR_NEHALEM_M0_PMON_EVNT_SEL1 0x00000CB2
2885 Package. Uncore M-box 0 perfmon counter MSR.
2887 @param ECX MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)
2888 @param EAX Lower 32-bits of MSR value.
2889 @param EDX Upper 32-bits of MSR value.
2891 <b>Example usage</b>
2895 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);
2896 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);
2898 @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.
2900 #define MSR_NEHALEM_M0_PMON_CTR1 0x00000CB3
2904 Package. Uncore M-box 0 perfmon event select MSR.
2906 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)
2907 @param EAX Lower 32-bits of MSR value.
2908 @param EDX Upper 32-bits of MSR value.
2910 <b>Example usage</b>
2914 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);
2915 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);
2917 @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.
2919 #define MSR_NEHALEM_M0_PMON_EVNT_SEL2 0x00000CB4
2923 Package. Uncore M-box 0 perfmon counter MSR.
2925 @param ECX MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)
2926 @param EAX Lower 32-bits of MSR value.
2927 @param EDX Upper 32-bits of MSR value.
2929 <b>Example usage</b>
2933 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);
2934 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);
2936 @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.
2938 #define MSR_NEHALEM_M0_PMON_CTR2 0x00000CB5
2942 Package. Uncore M-box 0 perfmon event select MSR.
2944 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)
2945 @param EAX Lower 32-bits of MSR value.
2946 @param EDX Upper 32-bits of MSR value.
2948 <b>Example usage</b>
2952 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);
2953 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);
2955 @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.
2957 #define MSR_NEHALEM_M0_PMON_EVNT_SEL3 0x00000CB6
2961 Package. Uncore M-box 0 perfmon counter MSR.
2963 @param ECX MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)
2964 @param EAX Lower 32-bits of MSR value.
2965 @param EDX Upper 32-bits of MSR value.
2967 <b>Example usage</b>
2971 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);
2972 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);
2974 @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.
2976 #define MSR_NEHALEM_M0_PMON_CTR3 0x00000CB7
2980 Package. Uncore M-box 0 perfmon event select MSR.
2982 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)
2983 @param EAX Lower 32-bits of MSR value.
2984 @param EDX Upper 32-bits of MSR value.
2986 <b>Example usage</b>
2990 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);
2991 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);
2993 @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.
2995 #define MSR_NEHALEM_M0_PMON_EVNT_SEL4 0x00000CB8
2999 Package. Uncore M-box 0 perfmon counter MSR.
3001 @param ECX MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)
3002 @param EAX Lower 32-bits of MSR value.
3003 @param EDX Upper 32-bits of MSR value.
3005 <b>Example usage</b>
3009 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);
3010 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);
3012 @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.
3014 #define MSR_NEHALEM_M0_PMON_CTR4 0x00000CB9
3018 Package. Uncore M-box 0 perfmon event select MSR.
3020 @param ECX MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)
3021 @param EAX Lower 32-bits of MSR value.
3022 @param EDX Upper 32-bits of MSR value.
3024 <b>Example usage</b>
3028 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);
3029 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);
3031 @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.
3033 #define MSR_NEHALEM_M0_PMON_EVNT_SEL5 0x00000CBA
3037 Package. Uncore M-box 0 perfmon counter MSR.
3039 @param ECX MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)
3040 @param EAX Lower 32-bits of MSR value.
3041 @param EDX Upper 32-bits of MSR value.
3043 <b>Example usage</b>
3047 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);
3048 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);
3050 @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.
3052 #define MSR_NEHALEM_M0_PMON_CTR5 0x00000CBB
3056 Package. Uncore S-box 1 perfmon local box control MSR.
3058 @param ECX MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)
3059 @param EAX Lower 32-bits of MSR value.
3060 @param EDX Upper 32-bits of MSR value.
3062 <b>Example usage</b>
3066 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);
3067 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);
3069 @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.
3071 #define MSR_NEHALEM_S1_PMON_BOX_CTRL 0x00000CC0
3075 Package. Uncore S-box 1 perfmon local box status MSR.
3077 @param ECX MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)
3078 @param EAX Lower 32-bits of MSR value.
3079 @param EDX Upper 32-bits of MSR value.
3081 <b>Example usage</b>
3085 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);
3086 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);
3088 @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.
3090 #define MSR_NEHALEM_S1_PMON_BOX_STATUS 0x00000CC1
3094 Package. Uncore S-box 1 perfmon local box overflow control MSR.
3096 @param ECX MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)
3097 @param EAX Lower 32-bits of MSR value.
3098 @param EDX Upper 32-bits of MSR value.
3100 <b>Example usage</b>
3104 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);
3105 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);
3107 @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.
3109 #define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL 0x00000CC2
3113 Package. Uncore S-box 1 perfmon event select MSR.
3115 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)
3116 @param EAX Lower 32-bits of MSR value.
3117 @param EDX Upper 32-bits of MSR value.
3119 <b>Example usage</b>
3123 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);
3124 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);
3126 @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.
3128 #define MSR_NEHALEM_S1_PMON_EVNT_SEL0 0x00000CD0
3132 Package. Uncore S-box 1 perfmon counter MSR.
3134 @param ECX MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)
3135 @param EAX Lower 32-bits of MSR value.
3136 @param EDX Upper 32-bits of MSR value.
3138 <b>Example usage</b>
3142 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);
3143 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);
3145 @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
3147 #define MSR_NEHALEM_S1_PMON_CTR0 0x00000CD1
3151 Package. Uncore S-box 1 perfmon event select MSR.
3153 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)
3154 @param EAX Lower 32-bits of MSR value.
3155 @param EDX Upper 32-bits of MSR value.
3157 <b>Example usage</b>
3161 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);
3162 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);
3164 @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.
3166 #define MSR_NEHALEM_S1_PMON_EVNT_SEL1 0x00000CD2
3170 Package. Uncore S-box 1 perfmon counter MSR.
3172 @param ECX MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)
3173 @param EAX Lower 32-bits of MSR value.
3174 @param EDX Upper 32-bits of MSR value.
3176 <b>Example usage</b>
3180 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);
3181 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);
3183 @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
3185 #define MSR_NEHALEM_S1_PMON_CTR1 0x00000CD3
3189 Package. Uncore S-box 1 perfmon event select MSR.
3191 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)
3192 @param EAX Lower 32-bits of MSR value.
3193 @param EDX Upper 32-bits of MSR value.
3195 <b>Example usage</b>
3199 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);
3200 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);
3202 @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.
3204 #define MSR_NEHALEM_S1_PMON_EVNT_SEL2 0x00000CD4
3208 Package. Uncore S-box 1 perfmon counter MSR.
3210 @param ECX MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)
3211 @param EAX Lower 32-bits of MSR value.
3212 @param EDX Upper 32-bits of MSR value.
3214 <b>Example usage</b>
3218 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);
3219 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);
3221 @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
3223 #define MSR_NEHALEM_S1_PMON_CTR2 0x00000CD5
3227 Package. Uncore S-box 1 perfmon event select MSR.
3229 @param ECX MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)
3230 @param EAX Lower 32-bits of MSR value.
3231 @param EDX Upper 32-bits of MSR value.
3233 <b>Example usage</b>
3237 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);
3238 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);
3240 @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.
3242 #define MSR_NEHALEM_S1_PMON_EVNT_SEL3 0x00000CD6
3246 Package. Uncore S-box 1 perfmon counter MSR.
3248 @param ECX MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)
3249 @param EAX Lower 32-bits of MSR value.
3250 @param EDX Upper 32-bits of MSR value.
3252 <b>Example usage</b>
3256 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);
3257 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);
3259 @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
3261 #define MSR_NEHALEM_S1_PMON_CTR3 0x00000CD7
3265 Package. Uncore M-box 1 perfmon local box control MSR.
3267 @param ECX MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)
3268 @param EAX Lower 32-bits of MSR value.
3269 @param EDX Upper 32-bits of MSR value.
3271 <b>Example usage</b>
3275 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);
3276 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);
3278 @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.
3280 #define MSR_NEHALEM_M1_PMON_BOX_CTRL 0x00000CE0
3284 Package. Uncore M-box 1 perfmon local box status MSR.
3286 @param ECX MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)
3287 @param EAX Lower 32-bits of MSR value.
3288 @param EDX Upper 32-bits of MSR value.
3290 <b>Example usage</b>
3294 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);
3295 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);
3297 @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.
3299 #define MSR_NEHALEM_M1_PMON_BOX_STATUS 0x00000CE1
3303 Package. Uncore M-box 1 perfmon local box overflow control MSR.
3305 @param ECX MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)
3306 @param EAX Lower 32-bits of MSR value.
3307 @param EDX Upper 32-bits of MSR value.
3309 <b>Example usage</b>
3313 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);
3314 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);
3316 @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.
3318 #define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL 0x00000CE2
3322 Package. Uncore M-box 1 perfmon time stamp unit select MSR.
3324 @param ECX MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)
3325 @param EAX Lower 32-bits of MSR value.
3326 @param EDX Upper 32-bits of MSR value.
3328 <b>Example usage</b>
3332 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);
3333 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);
3335 @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.
3337 #define MSR_NEHALEM_M1_PMON_TIMESTAMP 0x00000CE4
3341 Package. Uncore M-box 1 perfmon DSP unit select MSR.
3343 @param ECX MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)
3344 @param EAX Lower 32-bits of MSR value.
3345 @param EDX Upper 32-bits of MSR value.
3347 <b>Example usage</b>
3351 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);
3352 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);
3354 @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.
3356 #define MSR_NEHALEM_M1_PMON_DSP 0x00000CE5
3360 Package. Uncore M-box 1 perfmon ISS unit select MSR.
3362 @param ECX MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)
3363 @param EAX Lower 32-bits of MSR value.
3364 @param EDX Upper 32-bits of MSR value.
3366 <b>Example usage</b>
3370 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);
3371 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);
3373 @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.
3375 #define MSR_NEHALEM_M1_PMON_ISS 0x00000CE6
3379 Package. Uncore M-box 1 perfmon MAP unit select MSR.
3381 @param ECX MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)
3382 @param EAX Lower 32-bits of MSR value.
3383 @param EDX Upper 32-bits of MSR value.
3385 <b>Example usage</b>
3389 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);
3390 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);
3392 @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.
3394 #define MSR_NEHALEM_M1_PMON_MAP 0x00000CE7
3398 Package. Uncore M-box 1 perfmon MIC THR select MSR.
3400 @param ECX MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)
3401 @param EAX Lower 32-bits of MSR value.
3402 @param EDX Upper 32-bits of MSR value.
3404 <b>Example usage</b>
3408 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);
3409 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);
3411 @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.
3413 #define MSR_NEHALEM_M1_PMON_MSC_THR 0x00000CE8
3417 Package. Uncore M-box 1 perfmon PGT unit select MSR.
3419 @param ECX MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)
3420 @param EAX Lower 32-bits of MSR value.
3421 @param EDX Upper 32-bits of MSR value.
3423 <b>Example usage</b>
3427 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);
3428 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);
3430 @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.
3432 #define MSR_NEHALEM_M1_PMON_PGT 0x00000CE9
3436 Package. Uncore M-box 1 perfmon PLD unit select MSR.
3438 @param ECX MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)
3439 @param EAX Lower 32-bits of MSR value.
3440 @param EDX Upper 32-bits of MSR value.
3442 <b>Example usage</b>
3446 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);
3447 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);
3449 @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.
3451 #define MSR_NEHALEM_M1_PMON_PLD 0x00000CEA
3455 Package. Uncore M-box 1 perfmon ZDP unit select MSR.
3457 @param ECX MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)
3458 @param EAX Lower 32-bits of MSR value.
3459 @param EDX Upper 32-bits of MSR value.
3461 <b>Example usage</b>
3465 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);
3466 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);
3468 @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.
3470 #define MSR_NEHALEM_M1_PMON_ZDP 0x00000CEB
3474 Package. Uncore M-box 1 perfmon event select MSR.
3476 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)
3477 @param EAX Lower 32-bits of MSR value.
3478 @param EDX Upper 32-bits of MSR value.
3480 <b>Example usage</b>
3484 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);
3485 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);
3487 @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.
3489 #define MSR_NEHALEM_M1_PMON_EVNT_SEL0 0x00000CF0
3493 Package. Uncore M-box 1 perfmon counter MSR.
3495 @param ECX MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)
3496 @param EAX Lower 32-bits of MSR value.
3497 @param EDX Upper 32-bits of MSR value.
3499 <b>Example usage</b>
3503 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);
3504 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);
3506 @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.
3508 #define MSR_NEHALEM_M1_PMON_CTR0 0x00000CF1
3512 Package. Uncore M-box 1 perfmon event select MSR.
3514 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)
3515 @param EAX Lower 32-bits of MSR value.
3516 @param EDX Upper 32-bits of MSR value.
3518 <b>Example usage</b>
3522 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);
3523 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);
3525 @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.
3527 #define MSR_NEHALEM_M1_PMON_EVNT_SEL1 0x00000CF2
3531 Package. Uncore M-box 1 perfmon counter MSR.
3533 @param ECX MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)
3534 @param EAX Lower 32-bits of MSR value.
3535 @param EDX Upper 32-bits of MSR value.
3537 <b>Example usage</b>
3541 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);
3542 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);
3544 @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.
3546 #define MSR_NEHALEM_M1_PMON_CTR1 0x00000CF3
3550 Package. Uncore M-box 1 perfmon event select MSR.
3552 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)
3553 @param EAX Lower 32-bits of MSR value.
3554 @param EDX Upper 32-bits of MSR value.
3556 <b>Example usage</b>
3560 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);
3561 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);
3563 @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.
3565 #define MSR_NEHALEM_M1_PMON_EVNT_SEL2 0x00000CF4
3569 Package. Uncore M-box 1 perfmon counter MSR.
3571 @param ECX MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)
3572 @param EAX Lower 32-bits of MSR value.
3573 @param EDX Upper 32-bits of MSR value.
3575 <b>Example usage</b>
3579 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);
3580 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);
3582 @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.
3584 #define MSR_NEHALEM_M1_PMON_CTR2 0x00000CF5
3588 Package. Uncore M-box 1 perfmon event select MSR.
3590 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)
3591 @param EAX Lower 32-bits of MSR value.
3592 @param EDX Upper 32-bits of MSR value.
3594 <b>Example usage</b>
3598 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);
3599 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);
3601 @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.
3603 #define MSR_NEHALEM_M1_PMON_EVNT_SEL3 0x00000CF6
3607 Package. Uncore M-box 1 perfmon counter MSR.
3609 @param ECX MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)
3610 @param EAX Lower 32-bits of MSR value.
3611 @param EDX Upper 32-bits of MSR value.
3613 <b>Example usage</b>
3617 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);
3618 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);
3620 @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.
3622 #define MSR_NEHALEM_M1_PMON_CTR3 0x00000CF7
3626 Package. Uncore M-box 1 perfmon event select MSR.
3628 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)
3629 @param EAX Lower 32-bits of MSR value.
3630 @param EDX Upper 32-bits of MSR value.
3632 <b>Example usage</b>
3636 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);
3637 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);
3639 @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.
3641 #define MSR_NEHALEM_M1_PMON_EVNT_SEL4 0x00000CF8
3645 Package. Uncore M-box 1 perfmon counter MSR.
3647 @param ECX MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)
3648 @param EAX Lower 32-bits of MSR value.
3649 @param EDX Upper 32-bits of MSR value.
3651 <b>Example usage</b>
3655 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);
3656 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);
3658 @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.
3660 #define MSR_NEHALEM_M1_PMON_CTR4 0x00000CF9
3664 Package. Uncore M-box 1 perfmon event select MSR.
3666 @param ECX MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)
3667 @param EAX Lower 32-bits of MSR value.
3668 @param EDX Upper 32-bits of MSR value.
3670 <b>Example usage</b>
3674 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);
3675 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);
3677 @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.
3679 #define MSR_NEHALEM_M1_PMON_EVNT_SEL5 0x00000CFA
3683 Package. Uncore M-box 1 perfmon counter MSR.
3685 @param ECX MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)
3686 @param EAX Lower 32-bits of MSR value.
3687 @param EDX Upper 32-bits of MSR value.
3689 <b>Example usage</b>
3693 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);
3694 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);
3696 @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.
3698 #define MSR_NEHALEM_M1_PMON_CTR5 0x00000CFB
3702 Package. Uncore C-box 0 perfmon local box control MSR.
3704 @param ECX MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)
3705 @param EAX Lower 32-bits of MSR value.
3706 @param EDX Upper 32-bits of MSR value.
3708 <b>Example usage</b>
3712 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);
3713 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);
3715 @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.
3717 #define MSR_NEHALEM_C0_PMON_BOX_CTRL 0x00000D00
3721 Package. Uncore C-box 0 perfmon local box status MSR.
3723 @param ECX MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)
3724 @param EAX Lower 32-bits of MSR value.
3725 @param EDX Upper 32-bits of MSR value.
3727 <b>Example usage</b>
3731 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);
3732 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);
3734 @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
3736 #define MSR_NEHALEM_C0_PMON_BOX_STATUS 0x00000D01
3740 Package. Uncore C-box 0 perfmon local box overflow control MSR.
3742 @param ECX MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)
3743 @param EAX Lower 32-bits of MSR value.
3744 @param EDX Upper 32-bits of MSR value.
3746 <b>Example usage</b>
3750 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);
3751 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);
3753 @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.
3755 #define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL 0x00000D02
3759 Package. Uncore C-box 0 perfmon event select MSR.
3761 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)
3762 @param EAX Lower 32-bits of MSR value.
3763 @param EDX Upper 32-bits of MSR value.
3765 <b>Example usage</b>
3769 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);
3770 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);
3772 @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.
3774 #define MSR_NEHALEM_C0_PMON_EVNT_SEL0 0x00000D10
3778 Package. Uncore C-box 0 perfmon counter MSR.
3780 @param ECX MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)
3781 @param EAX Lower 32-bits of MSR value.
3782 @param EDX Upper 32-bits of MSR value.
3784 <b>Example usage</b>
3788 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);
3789 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);
3791 @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
3793 #define MSR_NEHALEM_C0_PMON_CTR0 0x00000D11
3797 Package. Uncore C-box 0 perfmon event select MSR.
3799 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)
3800 @param EAX Lower 32-bits of MSR value.
3801 @param EDX Upper 32-bits of MSR value.
3803 <b>Example usage</b>
3807 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);
3808 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);
3810 @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.
3812 #define MSR_NEHALEM_C0_PMON_EVNT_SEL1 0x00000D12
3816 Package. Uncore C-box 0 perfmon counter MSR.
3818 @param ECX MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)
3819 @param EAX Lower 32-bits of MSR value.
3820 @param EDX Upper 32-bits of MSR value.
3822 <b>Example usage</b>
3826 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);
3827 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);
3829 @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
3831 #define MSR_NEHALEM_C0_PMON_CTR1 0x00000D13
3835 Package. Uncore C-box 0 perfmon event select MSR.
3837 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)
3838 @param EAX Lower 32-bits of MSR value.
3839 @param EDX Upper 32-bits of MSR value.
3841 <b>Example usage</b>
3845 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);
3846 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);
3848 @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.
3850 #define MSR_NEHALEM_C0_PMON_EVNT_SEL2 0x00000D14
3854 Package. Uncore C-box 0 perfmon counter MSR.
3856 @param ECX MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)
3857 @param EAX Lower 32-bits of MSR value.
3858 @param EDX Upper 32-bits of MSR value.
3860 <b>Example usage</b>
3864 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);
3865 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);
3867 @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
3869 #define MSR_NEHALEM_C0_PMON_CTR2 0x00000D15
3873 Package. Uncore C-box 0 perfmon event select MSR.
3875 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)
3876 @param EAX Lower 32-bits of MSR value.
3877 @param EDX Upper 32-bits of MSR value.
3879 <b>Example usage</b>
3883 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);
3884 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);
3886 @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.
3888 #define MSR_NEHALEM_C0_PMON_EVNT_SEL3 0x00000D16
3892 Package. Uncore C-box 0 perfmon counter MSR.
3894 @param ECX MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)
3895 @param EAX Lower 32-bits of MSR value.
3896 @param EDX Upper 32-bits of MSR value.
3898 <b>Example usage</b>
3902 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);
3903 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);
3905 @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
3907 #define MSR_NEHALEM_C0_PMON_CTR3 0x00000D17
3911 Package. Uncore C-box 0 perfmon event select MSR.
3913 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)
3914 @param EAX Lower 32-bits of MSR value.
3915 @param EDX Upper 32-bits of MSR value.
3917 <b>Example usage</b>
3921 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);
3922 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);
3924 @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.
3926 #define MSR_NEHALEM_C0_PMON_EVNT_SEL4 0x00000D18
3930 Package. Uncore C-box 0 perfmon counter MSR.
3932 @param ECX MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)
3933 @param EAX Lower 32-bits of MSR value.
3934 @param EDX Upper 32-bits of MSR value.
3936 <b>Example usage</b>
3940 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);
3941 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);
3943 @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.
3945 #define MSR_NEHALEM_C0_PMON_CTR4 0x00000D19
3949 Package. Uncore C-box 0 perfmon event select MSR.
3951 @param ECX MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)
3952 @param EAX Lower 32-bits of MSR value.
3953 @param EDX Upper 32-bits of MSR value.
3955 <b>Example usage</b>
3959 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);
3960 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);
3962 @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.
3964 #define MSR_NEHALEM_C0_PMON_EVNT_SEL5 0x00000D1A
3968 Package. Uncore C-box 0 perfmon counter MSR.
3970 @param ECX MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)
3971 @param EAX Lower 32-bits of MSR value.
3972 @param EDX Upper 32-bits of MSR value.
3974 <b>Example usage</b>
3978 Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);
3979 AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);
3981 @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.
3983 #define MSR_NEHALEM_C0_PMON_CTR5 0x00000D1B
3987 Package. Uncore C-box 4 perfmon local box control MSR.
3989 @param ECX MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)
3990 @param EAX Lower 32-bits of MSR value.
3991 @param EDX Upper 32-bits of MSR value.
3993 <b>Example usage</b>
3997 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);
3998 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);
4000 @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.
4002 #define MSR_NEHALEM_C4_PMON_BOX_CTRL 0x00000D20
4006 Package. Uncore C-box 4 perfmon local box status MSR.
4008 @param ECX MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)
4009 @param EAX Lower 32-bits of MSR value.
4010 @param EDX Upper 32-bits of MSR value.
4012 <b>Example usage</b>
4016 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);
4017 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);
4019 @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
4021 #define MSR_NEHALEM_C4_PMON_BOX_STATUS 0x00000D21
4025 Package. Uncore C-box 4 perfmon local box overflow control MSR.
4027 @param ECX MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)
4028 @param EAX Lower 32-bits of MSR value.
4029 @param EDX Upper 32-bits of MSR value.
4031 <b>Example usage</b>
4035 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);
4036 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);
4038 @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.
4040 #define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL 0x00000D22
4044 Package. Uncore C-box 4 perfmon event select MSR.
4046 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)
4047 @param EAX Lower 32-bits of MSR value.
4048 @param EDX Upper 32-bits of MSR value.
4050 <b>Example usage</b>
4054 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);
4055 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);
4057 @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.
4059 #define MSR_NEHALEM_C4_PMON_EVNT_SEL0 0x00000D30
4063 Package. Uncore C-box 4 perfmon counter MSR.
4065 @param ECX MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)
4066 @param EAX Lower 32-bits of MSR value.
4067 @param EDX Upper 32-bits of MSR value.
4069 <b>Example usage</b>
4073 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);
4074 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);
4076 @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
4078 #define MSR_NEHALEM_C4_PMON_CTR0 0x00000D31
4082 Package. Uncore C-box 4 perfmon event select MSR.
4084 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)
4085 @param EAX Lower 32-bits of MSR value.
4086 @param EDX Upper 32-bits of MSR value.
4088 <b>Example usage</b>
4092 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);
4093 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);
4095 @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.
4097 #define MSR_NEHALEM_C4_PMON_EVNT_SEL1 0x00000D32
4101 Package. Uncore C-box 4 perfmon counter MSR.
4103 @param ECX MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)
4104 @param EAX Lower 32-bits of MSR value.
4105 @param EDX Upper 32-bits of MSR value.
4107 <b>Example usage</b>
4111 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);
4112 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);
4114 @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
4116 #define MSR_NEHALEM_C4_PMON_CTR1 0x00000D33
4120 Package. Uncore C-box 4 perfmon event select MSR.
4122 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)
4123 @param EAX Lower 32-bits of MSR value.
4124 @param EDX Upper 32-bits of MSR value.
4126 <b>Example usage</b>
4130 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);
4131 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);
4133 @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.
4135 #define MSR_NEHALEM_C4_PMON_EVNT_SEL2 0x00000D34
4139 Package. Uncore C-box 4 perfmon counter MSR.
4141 @param ECX MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)
4142 @param EAX Lower 32-bits of MSR value.
4143 @param EDX Upper 32-bits of MSR value.
4145 <b>Example usage</b>
4149 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);
4150 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);
4152 @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
4154 #define MSR_NEHALEM_C4_PMON_CTR2 0x00000D35
4158 Package. Uncore C-box 4 perfmon event select MSR.
4160 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)
4161 @param EAX Lower 32-bits of MSR value.
4162 @param EDX Upper 32-bits of MSR value.
4164 <b>Example usage</b>
4168 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);
4169 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);
4171 @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.
4173 #define MSR_NEHALEM_C4_PMON_EVNT_SEL3 0x00000D36
4177 Package. Uncore C-box 4 perfmon counter MSR.
4179 @param ECX MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)
4180 @param EAX Lower 32-bits of MSR value.
4181 @param EDX Upper 32-bits of MSR value.
4183 <b>Example usage</b>
4187 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);
4188 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);
4190 @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
4192 #define MSR_NEHALEM_C4_PMON_CTR3 0x00000D37
4196 Package. Uncore C-box 4 perfmon event select MSR.
4198 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)
4199 @param EAX Lower 32-bits of MSR value.
4200 @param EDX Upper 32-bits of MSR value.
4202 <b>Example usage</b>
4206 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);
4207 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);
4209 @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.
4211 #define MSR_NEHALEM_C4_PMON_EVNT_SEL4 0x00000D38
4215 Package. Uncore C-box 4 perfmon counter MSR.
4217 @param ECX MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)
4218 @param EAX Lower 32-bits of MSR value.
4219 @param EDX Upper 32-bits of MSR value.
4221 <b>Example usage</b>
4225 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);
4226 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);
4228 @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.
4230 #define MSR_NEHALEM_C4_PMON_CTR4 0x00000D39
4234 Package. Uncore C-box 4 perfmon event select MSR.
4236 @param ECX MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)
4237 @param EAX Lower 32-bits of MSR value.
4238 @param EDX Upper 32-bits of MSR value.
4240 <b>Example usage</b>
4244 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);
4245 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);
4247 @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.
4249 #define MSR_NEHALEM_C4_PMON_EVNT_SEL5 0x00000D3A
4253 Package. Uncore C-box 4 perfmon counter MSR.
4255 @param ECX MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)
4256 @param EAX Lower 32-bits of MSR value.
4257 @param EDX Upper 32-bits of MSR value.
4259 <b>Example usage</b>
4263 Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);
4264 AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);
4266 @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.
4268 #define MSR_NEHALEM_C4_PMON_CTR5 0x00000D3B
4272 Package. Uncore C-box 2 perfmon local box control MSR.
4274 @param ECX MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)
4275 @param EAX Lower 32-bits of MSR value.
4276 @param EDX Upper 32-bits of MSR value.
4278 <b>Example usage</b>
4282 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);
4283 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);
4285 @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.
4287 #define MSR_NEHALEM_C2_PMON_BOX_CTRL 0x00000D40
4291 Package. Uncore C-box 2 perfmon local box status MSR.
4293 @param ECX MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)
4294 @param EAX Lower 32-bits of MSR value.
4295 @param EDX Upper 32-bits of MSR value.
4297 <b>Example usage</b>
4301 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);
4302 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);
4304 @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
4306 #define MSR_NEHALEM_C2_PMON_BOX_STATUS 0x00000D41
4310 Package. Uncore C-box 2 perfmon local box overflow control MSR.
4312 @param ECX MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)
4313 @param EAX Lower 32-bits of MSR value.
4314 @param EDX Upper 32-bits of MSR value.
4316 <b>Example usage</b>
4320 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);
4321 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);
4323 @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.
4325 #define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL 0x00000D42
4329 Package. Uncore C-box 2 perfmon event select MSR.
4331 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)
4332 @param EAX Lower 32-bits of MSR value.
4333 @param EDX Upper 32-bits of MSR value.
4335 <b>Example usage</b>
4339 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);
4340 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);
4342 @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.
4344 #define MSR_NEHALEM_C2_PMON_EVNT_SEL0 0x00000D50
4348 Package. Uncore C-box 2 perfmon counter MSR.
4350 @param ECX MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)
4351 @param EAX Lower 32-bits of MSR value.
4352 @param EDX Upper 32-bits of MSR value.
4354 <b>Example usage</b>
4358 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);
4359 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);
4361 @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
4363 #define MSR_NEHALEM_C2_PMON_CTR0 0x00000D51
4367 Package. Uncore C-box 2 perfmon event select MSR.
4369 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)
4370 @param EAX Lower 32-bits of MSR value.
4371 @param EDX Upper 32-bits of MSR value.
4373 <b>Example usage</b>
4377 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);
4378 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);
4380 @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.
4382 #define MSR_NEHALEM_C2_PMON_EVNT_SEL1 0x00000D52
4386 Package. Uncore C-box 2 perfmon counter MSR.
4388 @param ECX MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)
4389 @param EAX Lower 32-bits of MSR value.
4390 @param EDX Upper 32-bits of MSR value.
4392 <b>Example usage</b>
4396 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);
4397 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);
4399 @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
4401 #define MSR_NEHALEM_C2_PMON_CTR1 0x00000D53
4405 Package. Uncore C-box 2 perfmon event select MSR.
4407 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)
4408 @param EAX Lower 32-bits of MSR value.
4409 @param EDX Upper 32-bits of MSR value.
4411 <b>Example usage</b>
4415 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);
4416 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);
4418 @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.
4420 #define MSR_NEHALEM_C2_PMON_EVNT_SEL2 0x00000D54
4424 Package. Uncore C-box 2 perfmon counter MSR.
4426 @param ECX MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)
4427 @param EAX Lower 32-bits of MSR value.
4428 @param EDX Upper 32-bits of MSR value.
4430 <b>Example usage</b>
4434 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);
4435 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);
4437 @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
4439 #define MSR_NEHALEM_C2_PMON_CTR2 0x00000D55
4443 Package. Uncore C-box 2 perfmon event select MSR.
4445 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)
4446 @param EAX Lower 32-bits of MSR value.
4447 @param EDX Upper 32-bits of MSR value.
4449 <b>Example usage</b>
4453 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);
4454 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);
4456 @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.
4458 #define MSR_NEHALEM_C2_PMON_EVNT_SEL3 0x00000D56
4462 Package. Uncore C-box 2 perfmon counter MSR.
4464 @param ECX MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)
4465 @param EAX Lower 32-bits of MSR value.
4466 @param EDX Upper 32-bits of MSR value.
4468 <b>Example usage</b>
4472 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);
4473 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);
4475 @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
4477 #define MSR_NEHALEM_C2_PMON_CTR3 0x00000D57
4481 Package. Uncore C-box 2 perfmon event select MSR.
4483 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)
4484 @param EAX Lower 32-bits of MSR value.
4485 @param EDX Upper 32-bits of MSR value.
4487 <b>Example usage</b>
4491 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);
4492 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);
4494 @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.
4496 #define MSR_NEHALEM_C2_PMON_EVNT_SEL4 0x00000D58
4500 Package. Uncore C-box 2 perfmon counter MSR.
4502 @param ECX MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)
4503 @param EAX Lower 32-bits of MSR value.
4504 @param EDX Upper 32-bits of MSR value.
4506 <b>Example usage</b>
4510 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);
4511 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);
4513 @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.
4515 #define MSR_NEHALEM_C2_PMON_CTR4 0x00000D59
4519 Package. Uncore C-box 2 perfmon event select MSR.
4521 @param ECX MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)
4522 @param EAX Lower 32-bits of MSR value.
4523 @param EDX Upper 32-bits of MSR value.
4525 <b>Example usage</b>
4529 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);
4530 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);
4532 @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.
4534 #define MSR_NEHALEM_C2_PMON_EVNT_SEL5 0x00000D5A
4538 Package. Uncore C-box 2 perfmon counter MSR.
4540 @param ECX MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)
4541 @param EAX Lower 32-bits of MSR value.
4542 @param EDX Upper 32-bits of MSR value.
4544 <b>Example usage</b>
4548 Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);
4549 AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);
4551 @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.
4553 #define MSR_NEHALEM_C2_PMON_CTR5 0x00000D5B
4557 Package. Uncore C-box 6 perfmon local box control MSR.
4559 @param ECX MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)
4560 @param EAX Lower 32-bits of MSR value.
4561 @param EDX Upper 32-bits of MSR value.
4563 <b>Example usage</b>
4567 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);
4568 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);
4570 @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.
4572 #define MSR_NEHALEM_C6_PMON_BOX_CTRL 0x00000D60
4576 Package. Uncore C-box 6 perfmon local box status MSR.
4578 @param ECX MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)
4579 @param EAX Lower 32-bits of MSR value.
4580 @param EDX Upper 32-bits of MSR value.
4582 <b>Example usage</b>
4586 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);
4587 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);
4589 @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
4591 #define MSR_NEHALEM_C6_PMON_BOX_STATUS 0x00000D61
4595 Package. Uncore C-box 6 perfmon local box overflow control MSR.
4597 @param ECX MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)
4598 @param EAX Lower 32-bits of MSR value.
4599 @param EDX Upper 32-bits of MSR value.
4601 <b>Example usage</b>
4605 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);
4606 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);
4608 @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.
4610 #define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL 0x00000D62
4614 Package. Uncore C-box 6 perfmon event select MSR.
4616 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)
4617 @param EAX Lower 32-bits of MSR value.
4618 @param EDX Upper 32-bits of MSR value.
4620 <b>Example usage</b>
4624 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);
4625 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);
4627 @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.
4629 #define MSR_NEHALEM_C6_PMON_EVNT_SEL0 0x00000D70
4633 Package. Uncore C-box 6 perfmon counter MSR.
4635 @param ECX MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)
4636 @param EAX Lower 32-bits of MSR value.
4637 @param EDX Upper 32-bits of MSR value.
4639 <b>Example usage</b>
4643 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);
4644 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);
4646 @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
4648 #define MSR_NEHALEM_C6_PMON_CTR0 0x00000D71
4652 Package. Uncore C-box 6 perfmon event select MSR.
4654 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)
4655 @param EAX Lower 32-bits of MSR value.
4656 @param EDX Upper 32-bits of MSR value.
4658 <b>Example usage</b>
4662 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);
4663 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);
4665 @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.
4667 #define MSR_NEHALEM_C6_PMON_EVNT_SEL1 0x00000D72
4671 Package. Uncore C-box 6 perfmon counter MSR.
4673 @param ECX MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)
4674 @param EAX Lower 32-bits of MSR value.
4675 @param EDX Upper 32-bits of MSR value.
4677 <b>Example usage</b>
4681 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);
4682 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);
4684 @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
4686 #define MSR_NEHALEM_C6_PMON_CTR1 0x00000D73
4690 Package. Uncore C-box 6 perfmon event select MSR.
4692 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)
4693 @param EAX Lower 32-bits of MSR value.
4694 @param EDX Upper 32-bits of MSR value.
4696 <b>Example usage</b>
4700 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);
4701 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);
4703 @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.
4705 #define MSR_NEHALEM_C6_PMON_EVNT_SEL2 0x00000D74
4709 Package. Uncore C-box 6 perfmon counter MSR.
4711 @param ECX MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)
4712 @param EAX Lower 32-bits of MSR value.
4713 @param EDX Upper 32-bits of MSR value.
4715 <b>Example usage</b>
4719 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);
4720 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);
4722 @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
4724 #define MSR_NEHALEM_C6_PMON_CTR2 0x00000D75
4728 Package. Uncore C-box 6 perfmon event select MSR.
4730 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)
4731 @param EAX Lower 32-bits of MSR value.
4732 @param EDX Upper 32-bits of MSR value.
4734 <b>Example usage</b>
4738 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);
4739 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);
4741 @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.
4743 #define MSR_NEHALEM_C6_PMON_EVNT_SEL3 0x00000D76
4747 Package. Uncore C-box 6 perfmon counter MSR.
4749 @param ECX MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)
4750 @param EAX Lower 32-bits of MSR value.
4751 @param EDX Upper 32-bits of MSR value.
4753 <b>Example usage</b>
4757 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);
4758 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);
4760 @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
4762 #define MSR_NEHALEM_C6_PMON_CTR3 0x00000D77
4766 Package. Uncore C-box 6 perfmon event select MSR.
4768 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)
4769 @param EAX Lower 32-bits of MSR value.
4770 @param EDX Upper 32-bits of MSR value.
4772 <b>Example usage</b>
4776 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);
4777 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);
4779 @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.
4781 #define MSR_NEHALEM_C6_PMON_EVNT_SEL4 0x00000D78
4785 Package. Uncore C-box 6 perfmon counter MSR.
4787 @param ECX MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)
4788 @param EAX Lower 32-bits of MSR value.
4789 @param EDX Upper 32-bits of MSR value.
4791 <b>Example usage</b>
4795 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);
4796 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);
4798 @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.
4800 #define MSR_NEHALEM_C6_PMON_CTR4 0x00000D79
4804 Package. Uncore C-box 6 perfmon event select MSR.
4806 @param ECX MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)
4807 @param EAX Lower 32-bits of MSR value.
4808 @param EDX Upper 32-bits of MSR value.
4810 <b>Example usage</b>
4814 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);
4815 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);
4817 @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.
4819 #define MSR_NEHALEM_C6_PMON_EVNT_SEL5 0x00000D7A
4823 Package. Uncore C-box 6 perfmon counter MSR.
4825 @param ECX MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)
4826 @param EAX Lower 32-bits of MSR value.
4827 @param EDX Upper 32-bits of MSR value.
4829 <b>Example usage</b>
4833 Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);
4834 AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);
4836 @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.
4838 #define MSR_NEHALEM_C6_PMON_CTR5 0x00000D7B
4842 Package. Uncore C-box 1 perfmon local box control MSR.
4844 @param ECX MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)
4845 @param EAX Lower 32-bits of MSR value.
4846 @param EDX Upper 32-bits of MSR value.
4848 <b>Example usage</b>
4852 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);
4853 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);
4855 @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.
4857 #define MSR_NEHALEM_C1_PMON_BOX_CTRL 0x00000D80
4861 Package. Uncore C-box 1 perfmon local box status MSR.
4863 @param ECX MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)
4864 @param EAX Lower 32-bits of MSR value.
4865 @param EDX Upper 32-bits of MSR value.
4867 <b>Example usage</b>
4871 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);
4872 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);
4874 @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
4876 #define MSR_NEHALEM_C1_PMON_BOX_STATUS 0x00000D81
4880 Package. Uncore C-box 1 perfmon local box overflow control MSR.
4882 @param ECX MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)
4883 @param EAX Lower 32-bits of MSR value.
4884 @param EDX Upper 32-bits of MSR value.
4886 <b>Example usage</b>
4890 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);
4891 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);
4893 @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.
4895 #define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL 0x00000D82
4899 Package. Uncore C-box 1 perfmon event select MSR.
4901 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)
4902 @param EAX Lower 32-bits of MSR value.
4903 @param EDX Upper 32-bits of MSR value.
4905 <b>Example usage</b>
4909 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);
4910 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);
4912 @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.
4914 #define MSR_NEHALEM_C1_PMON_EVNT_SEL0 0x00000D90
4918 Package. Uncore C-box 1 perfmon counter MSR.
4920 @param ECX MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)
4921 @param EAX Lower 32-bits of MSR value.
4922 @param EDX Upper 32-bits of MSR value.
4924 <b>Example usage</b>
4928 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);
4929 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);
4931 @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
4933 #define MSR_NEHALEM_C1_PMON_CTR0 0x00000D91
4937 Package. Uncore C-box 1 perfmon event select MSR.
4939 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)
4940 @param EAX Lower 32-bits of MSR value.
4941 @param EDX Upper 32-bits of MSR value.
4943 <b>Example usage</b>
4947 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);
4948 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);
4950 @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.
4952 #define MSR_NEHALEM_C1_PMON_EVNT_SEL1 0x00000D92
4956 Package. Uncore C-box 1 perfmon counter MSR.
4958 @param ECX MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)
4959 @param EAX Lower 32-bits of MSR value.
4960 @param EDX Upper 32-bits of MSR value.
4962 <b>Example usage</b>
4966 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);
4967 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);
4969 @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
4971 #define MSR_NEHALEM_C1_PMON_CTR1 0x00000D93
4975 Package. Uncore C-box 1 perfmon event select MSR.
4977 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)
4978 @param EAX Lower 32-bits of MSR value.
4979 @param EDX Upper 32-bits of MSR value.
4981 <b>Example usage</b>
4985 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);
4986 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);
4988 @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.
4990 #define MSR_NEHALEM_C1_PMON_EVNT_SEL2 0x00000D94
4994 Package. Uncore C-box 1 perfmon counter MSR.
4996 @param ECX MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)
4997 @param EAX Lower 32-bits of MSR value.
4998 @param EDX Upper 32-bits of MSR value.
5000 <b>Example usage</b>
5004 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);
5005 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);
5007 @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
5009 #define MSR_NEHALEM_C1_PMON_CTR2 0x00000D95
5013 Package. Uncore C-box 1 perfmon event select MSR.
5015 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)
5016 @param EAX Lower 32-bits of MSR value.
5017 @param EDX Upper 32-bits of MSR value.
5019 <b>Example usage</b>
5023 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);
5024 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);
5026 @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.
5028 #define MSR_NEHALEM_C1_PMON_EVNT_SEL3 0x00000D96
5032 Package. Uncore C-box 1 perfmon counter MSR.
5034 @param ECX MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)
5035 @param EAX Lower 32-bits of MSR value.
5036 @param EDX Upper 32-bits of MSR value.
5038 <b>Example usage</b>
5042 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);
5043 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);
5045 @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
5047 #define MSR_NEHALEM_C1_PMON_CTR3 0x00000D97
5051 Package. Uncore C-box 1 perfmon event select MSR.
5053 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)
5054 @param EAX Lower 32-bits of MSR value.
5055 @param EDX Upper 32-bits of MSR value.
5057 <b>Example usage</b>
5061 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);
5062 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);
5064 @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.
5066 #define MSR_NEHALEM_C1_PMON_EVNT_SEL4 0x00000D98
5070 Package. Uncore C-box 1 perfmon counter MSR.
5072 @param ECX MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)
5073 @param EAX Lower 32-bits of MSR value.
5074 @param EDX Upper 32-bits of MSR value.
5076 <b>Example usage</b>
5080 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);
5081 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);
5083 @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.
5085 #define MSR_NEHALEM_C1_PMON_CTR4 0x00000D99
5089 Package. Uncore C-box 1 perfmon event select MSR.
5091 @param ECX MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)
5092 @param EAX Lower 32-bits of MSR value.
5093 @param EDX Upper 32-bits of MSR value.
5095 <b>Example usage</b>
5099 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);
5100 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);
5102 @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.
5104 #define MSR_NEHALEM_C1_PMON_EVNT_SEL5 0x00000D9A
5108 Package. Uncore C-box 1 perfmon counter MSR.
5110 @param ECX MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)
5111 @param EAX Lower 32-bits of MSR value.
5112 @param EDX Upper 32-bits of MSR value.
5114 <b>Example usage</b>
5118 Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);
5119 AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);
5121 @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.
5123 #define MSR_NEHALEM_C1_PMON_CTR5 0x00000D9B
5127 Package. Uncore C-box 5 perfmon local box control MSR.
5129 @param ECX MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)
5130 @param EAX Lower 32-bits of MSR value.
5131 @param EDX Upper 32-bits of MSR value.
5133 <b>Example usage</b>
5137 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);
5138 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);
5140 @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.
5142 #define MSR_NEHALEM_C5_PMON_BOX_CTRL 0x00000DA0
5146 Package. Uncore C-box 5 perfmon local box status MSR.
5148 @param ECX MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)
5149 @param EAX Lower 32-bits of MSR value.
5150 @param EDX Upper 32-bits of MSR value.
5152 <b>Example usage</b>
5156 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);
5157 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);
5159 @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
5161 #define MSR_NEHALEM_C5_PMON_BOX_STATUS 0x00000DA1
5165 Package. Uncore C-box 5 perfmon local box overflow control MSR.
5167 @param ECX MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)
5168 @param EAX Lower 32-bits of MSR value.
5169 @param EDX Upper 32-bits of MSR value.
5171 <b>Example usage</b>
5175 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);
5176 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);
5178 @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.
5180 #define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL 0x00000DA2
5184 Package. Uncore C-box 5 perfmon event select MSR.
5186 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)
5187 @param EAX Lower 32-bits of MSR value.
5188 @param EDX Upper 32-bits of MSR value.
5190 <b>Example usage</b>
5194 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);
5195 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);
5197 @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.
5199 #define MSR_NEHALEM_C5_PMON_EVNT_SEL0 0x00000DB0
5203 Package. Uncore C-box 5 perfmon counter MSR.
5205 @param ECX MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)
5206 @param EAX Lower 32-bits of MSR value.
5207 @param EDX Upper 32-bits of MSR value.
5209 <b>Example usage</b>
5213 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);
5214 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);
5216 @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
5218 #define MSR_NEHALEM_C5_PMON_CTR0 0x00000DB1
5222 Package. Uncore C-box 5 perfmon event select MSR.
5224 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)
5225 @param EAX Lower 32-bits of MSR value.
5226 @param EDX Upper 32-bits of MSR value.
5228 <b>Example usage</b>
5232 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);
5233 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);
5235 @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.
5237 #define MSR_NEHALEM_C5_PMON_EVNT_SEL1 0x00000DB2
5241 Package. Uncore C-box 5 perfmon counter MSR.
5243 @param ECX MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)
5244 @param EAX Lower 32-bits of MSR value.
5245 @param EDX Upper 32-bits of MSR value.
5247 <b>Example usage</b>
5251 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);
5252 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);
5254 @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
5256 #define MSR_NEHALEM_C5_PMON_CTR1 0x00000DB3
5260 Package. Uncore C-box 5 perfmon event select MSR.
5262 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)
5263 @param EAX Lower 32-bits of MSR value.
5264 @param EDX Upper 32-bits of MSR value.
5266 <b>Example usage</b>
5270 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);
5271 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);
5273 @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.
5275 #define MSR_NEHALEM_C5_PMON_EVNT_SEL2 0x00000DB4
5279 Package. Uncore C-box 5 perfmon counter MSR.
5281 @param ECX MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)
5282 @param EAX Lower 32-bits of MSR value.
5283 @param EDX Upper 32-bits of MSR value.
5285 <b>Example usage</b>
5289 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);
5290 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);
5292 @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
5294 #define MSR_NEHALEM_C5_PMON_CTR2 0x00000DB5
5298 Package. Uncore C-box 5 perfmon event select MSR.
5300 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)
5301 @param EAX Lower 32-bits of MSR value.
5302 @param EDX Upper 32-bits of MSR value.
5304 <b>Example usage</b>
5308 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);
5309 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);
5311 @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.
5313 #define MSR_NEHALEM_C5_PMON_EVNT_SEL3 0x00000DB6
5317 Package. Uncore C-box 5 perfmon counter MSR.
5319 @param ECX MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)
5320 @param EAX Lower 32-bits of MSR value.
5321 @param EDX Upper 32-bits of MSR value.
5323 <b>Example usage</b>
5327 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);
5328 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);
5330 @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
5332 #define MSR_NEHALEM_C5_PMON_CTR3 0x00000DB7
5336 Package. Uncore C-box 5 perfmon event select MSR.
5338 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)
5339 @param EAX Lower 32-bits of MSR value.
5340 @param EDX Upper 32-bits of MSR value.
5342 <b>Example usage</b>
5346 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);
5347 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);
5349 @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.
5351 #define MSR_NEHALEM_C5_PMON_EVNT_SEL4 0x00000DB8
5355 Package. Uncore C-box 5 perfmon counter MSR.
5357 @param ECX MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)
5358 @param EAX Lower 32-bits of MSR value.
5359 @param EDX Upper 32-bits of MSR value.
5361 <b>Example usage</b>
5365 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);
5366 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);
5368 @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.
5370 #define MSR_NEHALEM_C5_PMON_CTR4 0x00000DB9
5374 Package. Uncore C-box 5 perfmon event select MSR.
5376 @param ECX MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)
5377 @param EAX Lower 32-bits of MSR value.
5378 @param EDX Upper 32-bits of MSR value.
5380 <b>Example usage</b>
5384 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);
5385 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);
5387 @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.
5389 #define MSR_NEHALEM_C5_PMON_EVNT_SEL5 0x00000DBA
5393 Package. Uncore C-box 5 perfmon counter MSR.
5395 @param ECX MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)
5396 @param EAX Lower 32-bits of MSR value.
5397 @param EDX Upper 32-bits of MSR value.
5399 <b>Example usage</b>
5403 Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);
5404 AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);
5406 @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.
5408 #define MSR_NEHALEM_C5_PMON_CTR5 0x00000DBB
5412 Package. Uncore C-box 3 perfmon local box control MSR.
5414 @param ECX MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)
5415 @param EAX Lower 32-bits of MSR value.
5416 @param EDX Upper 32-bits of MSR value.
5418 <b>Example usage</b>
5422 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);
5423 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);
5425 @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.
5427 #define MSR_NEHALEM_C3_PMON_BOX_CTRL 0x00000DC0
5431 Package. Uncore C-box 3 perfmon local box status MSR.
5433 @param ECX MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)
5434 @param EAX Lower 32-bits of MSR value.
5435 @param EDX Upper 32-bits of MSR value.
5437 <b>Example usage</b>
5441 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);
5442 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);
5444 @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
5446 #define MSR_NEHALEM_C3_PMON_BOX_STATUS 0x00000DC1
5450 Package. Uncore C-box 3 perfmon local box overflow control MSR.
5452 @param ECX MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)
5453 @param EAX Lower 32-bits of MSR value.
5454 @param EDX Upper 32-bits of MSR value.
5456 <b>Example usage</b>
5460 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);
5461 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);
5463 @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.
5465 #define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL 0x00000DC2
5469 Package. Uncore C-box 3 perfmon event select MSR.
5471 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)
5472 @param EAX Lower 32-bits of MSR value.
5473 @param EDX Upper 32-bits of MSR value.
5475 <b>Example usage</b>
5479 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);
5480 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);
5482 @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.
5484 #define MSR_NEHALEM_C3_PMON_EVNT_SEL0 0x00000DD0
5488 Package. Uncore C-box 3 perfmon counter MSR.
5490 @param ECX MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)
5491 @param EAX Lower 32-bits of MSR value.
5492 @param EDX Upper 32-bits of MSR value.
5494 <b>Example usage</b>
5498 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);
5499 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);
5501 @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
5503 #define MSR_NEHALEM_C3_PMON_CTR0 0x00000DD1
5507 Package. Uncore C-box 3 perfmon event select MSR.
5509 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)
5510 @param EAX Lower 32-bits of MSR value.
5511 @param EDX Upper 32-bits of MSR value.
5513 <b>Example usage</b>
5517 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);
5518 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);
5520 @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.
5522 #define MSR_NEHALEM_C3_PMON_EVNT_SEL1 0x00000DD2
5526 Package. Uncore C-box 3 perfmon counter MSR.
5528 @param ECX MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)
5529 @param EAX Lower 32-bits of MSR value.
5530 @param EDX Upper 32-bits of MSR value.
5532 <b>Example usage</b>
5536 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);
5537 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);
5539 @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
5541 #define MSR_NEHALEM_C3_PMON_CTR1 0x00000DD3
5545 Package. Uncore C-box 3 perfmon event select MSR.
5547 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)
5548 @param EAX Lower 32-bits of MSR value.
5549 @param EDX Upper 32-bits of MSR value.
5551 <b>Example usage</b>
5555 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);
5556 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);
5558 @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.
5560 #define MSR_NEHALEM_C3_PMON_EVNT_SEL2 0x00000DD4
5564 Package. Uncore C-box 3 perfmon counter MSR.
5566 @param ECX MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)
5567 @param EAX Lower 32-bits of MSR value.
5568 @param EDX Upper 32-bits of MSR value.
5570 <b>Example usage</b>
5574 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);
5575 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);
5577 @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
5579 #define MSR_NEHALEM_C3_PMON_CTR2 0x00000DD5
5583 Package. Uncore C-box 3 perfmon event select MSR.
5585 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)
5586 @param EAX Lower 32-bits of MSR value.
5587 @param EDX Upper 32-bits of MSR value.
5589 <b>Example usage</b>
5593 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);
5594 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);
5596 @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.
5598 #define MSR_NEHALEM_C3_PMON_EVNT_SEL3 0x00000DD6
5602 Package. Uncore C-box 3 perfmon counter MSR.
5604 @param ECX MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)
5605 @param EAX Lower 32-bits of MSR value.
5606 @param EDX Upper 32-bits of MSR value.
5608 <b>Example usage</b>
5612 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);
5613 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);
5615 @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
5617 #define MSR_NEHALEM_C3_PMON_CTR3 0x00000DD7
5621 Package. Uncore C-box 3 perfmon event select MSR.
5623 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)
5624 @param EAX Lower 32-bits of MSR value.
5625 @param EDX Upper 32-bits of MSR value.
5627 <b>Example usage</b>
5631 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);
5632 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);
5634 @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.
5636 #define MSR_NEHALEM_C3_PMON_EVNT_SEL4 0x00000DD8
5640 Package. Uncore C-box 3 perfmon counter MSR.
5642 @param ECX MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)
5643 @param EAX Lower 32-bits of MSR value.
5644 @param EDX Upper 32-bits of MSR value.
5646 <b>Example usage</b>
5650 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);
5651 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);
5653 @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.
5655 #define MSR_NEHALEM_C3_PMON_CTR4 0x00000DD9
5659 Package. Uncore C-box 3 perfmon event select MSR.
5661 @param ECX MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)
5662 @param EAX Lower 32-bits of MSR value.
5663 @param EDX Upper 32-bits of MSR value.
5665 <b>Example usage</b>
5669 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);
5670 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);
5672 @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.
5674 #define MSR_NEHALEM_C3_PMON_EVNT_SEL5 0x00000DDA
5678 Package. Uncore C-box 3 perfmon counter MSR.
5680 @param ECX MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)
5681 @param EAX Lower 32-bits of MSR value.
5682 @param EDX Upper 32-bits of MSR value.
5684 <b>Example usage</b>
5688 Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);
5689 AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);
5691 @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.
5693 #define MSR_NEHALEM_C3_PMON_CTR5 0x00000DDB
5697 Package. Uncore C-box 7 perfmon local box control MSR.
5699 @param ECX MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)
5700 @param EAX Lower 32-bits of MSR value.
5701 @param EDX Upper 32-bits of MSR value.
5703 <b>Example usage</b>
5707 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);
5708 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);
5710 @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.
5712 #define MSR_NEHALEM_C7_PMON_BOX_CTRL 0x00000DE0
5716 Package. Uncore C-box 7 perfmon local box status MSR.
5718 @param ECX MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)
5719 @param EAX Lower 32-bits of MSR value.
5720 @param EDX Upper 32-bits of MSR value.
5722 <b>Example usage</b>
5726 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);
5727 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);
5729 @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
5731 #define MSR_NEHALEM_C7_PMON_BOX_STATUS 0x00000DE1
5735 Package. Uncore C-box 7 perfmon local box overflow control MSR.
5737 @param ECX MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)
5738 @param EAX Lower 32-bits of MSR value.
5739 @param EDX Upper 32-bits of MSR value.
5741 <b>Example usage</b>
5745 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);
5746 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);
5748 @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.
5750 #define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL 0x00000DE2
5754 Package. Uncore C-box 7 perfmon event select MSR.
5756 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)
5757 @param EAX Lower 32-bits of MSR value.
5758 @param EDX Upper 32-bits of MSR value.
5760 <b>Example usage</b>
5764 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);
5765 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);
5767 @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.
5769 #define MSR_NEHALEM_C7_PMON_EVNT_SEL0 0x00000DF0
5773 Package. Uncore C-box 7 perfmon counter MSR.
5775 @param ECX MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)
5776 @param EAX Lower 32-bits of MSR value.
5777 @param EDX Upper 32-bits of MSR value.
5779 <b>Example usage</b>
5783 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);
5784 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);
5786 @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
5788 #define MSR_NEHALEM_C7_PMON_CTR0 0x00000DF1
5792 Package. Uncore C-box 7 perfmon event select MSR.
5794 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)
5795 @param EAX Lower 32-bits of MSR value.
5796 @param EDX Upper 32-bits of MSR value.
5798 <b>Example usage</b>
5802 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);
5803 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);
5805 @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.
5807 #define MSR_NEHALEM_C7_PMON_EVNT_SEL1 0x00000DF2
5811 Package. Uncore C-box 7 perfmon counter MSR.
5813 @param ECX MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)
5814 @param EAX Lower 32-bits of MSR value.
5815 @param EDX Upper 32-bits of MSR value.
5817 <b>Example usage</b>
5821 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);
5822 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);
5824 @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
5826 #define MSR_NEHALEM_C7_PMON_CTR1 0x00000DF3
5830 Package. Uncore C-box 7 perfmon event select MSR.
5832 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)
5833 @param EAX Lower 32-bits of MSR value.
5834 @param EDX Upper 32-bits of MSR value.
5836 <b>Example usage</b>
5840 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);
5841 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);
5843 @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.
5845 #define MSR_NEHALEM_C7_PMON_EVNT_SEL2 0x00000DF4
5849 Package. Uncore C-box 7 perfmon counter MSR.
5851 @param ECX MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)
5852 @param EAX Lower 32-bits of MSR value.
5853 @param EDX Upper 32-bits of MSR value.
5855 <b>Example usage</b>
5859 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);
5860 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);
5862 @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
5864 #define MSR_NEHALEM_C7_PMON_CTR2 0x00000DF5
5868 Package. Uncore C-box 7 perfmon event select MSR.
5870 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)
5871 @param EAX Lower 32-bits of MSR value.
5872 @param EDX Upper 32-bits of MSR value.
5874 <b>Example usage</b>
5878 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);
5879 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);
5881 @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.
5883 #define MSR_NEHALEM_C7_PMON_EVNT_SEL3 0x00000DF6
5887 Package. Uncore C-box 7 perfmon counter MSR.
5889 @param ECX MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)
5890 @param EAX Lower 32-bits of MSR value.
5891 @param EDX Upper 32-bits of MSR value.
5893 <b>Example usage</b>
5897 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);
5898 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);
5900 @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
5902 #define MSR_NEHALEM_C7_PMON_CTR3 0x00000DF7
5906 Package. Uncore C-box 7 perfmon event select MSR.
5908 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)
5909 @param EAX Lower 32-bits of MSR value.
5910 @param EDX Upper 32-bits of MSR value.
5912 <b>Example usage</b>
5916 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);
5917 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);
5919 @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.
5921 #define MSR_NEHALEM_C7_PMON_EVNT_SEL4 0x00000DF8
5925 Package. Uncore C-box 7 perfmon counter MSR.
5927 @param ECX MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)
5928 @param EAX Lower 32-bits of MSR value.
5929 @param EDX Upper 32-bits of MSR value.
5931 <b>Example usage</b>
5935 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);
5936 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);
5938 @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.
5940 #define MSR_NEHALEM_C7_PMON_CTR4 0x00000DF9
5944 Package. Uncore C-box 7 perfmon event select MSR.
5946 @param ECX MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)
5947 @param EAX Lower 32-bits of MSR value.
5948 @param EDX Upper 32-bits of MSR value.
5950 <b>Example usage</b>
5954 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);
5955 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);
5957 @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.
5959 #define MSR_NEHALEM_C7_PMON_EVNT_SEL5 0x00000DFA
5963 Package. Uncore C-box 7 perfmon counter MSR.
5965 @param ECX MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)
5966 @param EAX Lower 32-bits of MSR value.
5967 @param EDX Upper 32-bits of MSR value.
5969 <b>Example usage</b>
5973 Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);
5974 AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);
5976 @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.
5978 #define MSR_NEHALEM_C7_PMON_CTR5 0x00000DFB
5982 Package. Uncore R-box 0 perfmon local box control MSR.
5984 @param ECX MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)
5985 @param EAX Lower 32-bits of MSR value.
5986 @param EDX Upper 32-bits of MSR value.
5988 <b>Example usage</b>
5992 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);
5993 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);
5995 @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.
5997 #define MSR_NEHALEM_R0_PMON_BOX_CTRL 0x00000E00
6001 Package. Uncore R-box 0 perfmon local box status MSR.
6003 @param ECX MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)
6004 @param EAX Lower 32-bits of MSR value.
6005 @param EDX Upper 32-bits of MSR value.
6007 <b>Example usage</b>
6011 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);
6012 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);
6014 @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.
6016 #define MSR_NEHALEM_R0_PMON_BOX_STATUS 0x00000E01
6020 Package. Uncore R-box 0 perfmon local box overflow control MSR.
6022 @param ECX MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)
6023 @param EAX Lower 32-bits of MSR value.
6024 @param EDX Upper 32-bits of MSR value.
6026 <b>Example usage</b>
6030 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);
6031 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);
6033 @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.
6035 #define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL 0x00000E02
6039 Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.
6041 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)
6042 @param EAX Lower 32-bits of MSR value.
6043 @param EDX Upper 32-bits of MSR value.
6045 <b>Example usage</b>
6049 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);
6050 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);
6052 @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.
6054 #define MSR_NEHALEM_R0_PMON_IPERF0_P0 0x00000E04
6058 Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.
6060 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)
6061 @param EAX Lower 32-bits of MSR value.
6062 @param EDX Upper 32-bits of MSR value.
6064 <b>Example usage</b>
6068 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);
6069 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);
6071 @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.
6073 #define MSR_NEHALEM_R0_PMON_IPERF0_P1 0x00000E05
6077 Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.
6079 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)
6080 @param EAX Lower 32-bits of MSR value.
6081 @param EDX Upper 32-bits of MSR value.
6083 <b>Example usage</b>
6087 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);
6088 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);
6090 @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.
6092 #define MSR_NEHALEM_R0_PMON_IPERF0_P2 0x00000E06
6096 Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.
6098 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)
6099 @param EAX Lower 32-bits of MSR value.
6100 @param EDX Upper 32-bits of MSR value.
6102 <b>Example usage</b>
6106 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);
6107 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);
6109 @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.
6111 #define MSR_NEHALEM_R0_PMON_IPERF0_P3 0x00000E07
6115 Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.
6117 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)
6118 @param EAX Lower 32-bits of MSR value.
6119 @param EDX Upper 32-bits of MSR value.
6121 <b>Example usage</b>
6125 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);
6126 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);
6128 @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.
6130 #define MSR_NEHALEM_R0_PMON_IPERF0_P4 0x00000E08
6134 Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.
6136 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)
6137 @param EAX Lower 32-bits of MSR value.
6138 @param EDX Upper 32-bits of MSR value.
6140 <b>Example usage</b>
6144 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);
6145 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);
6147 @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.
6149 #define MSR_NEHALEM_R0_PMON_IPERF0_P5 0x00000E09
6153 Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.
6155 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)
6156 @param EAX Lower 32-bits of MSR value.
6157 @param EDX Upper 32-bits of MSR value.
6159 <b>Example usage</b>
6163 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);
6164 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);
6166 @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.
6168 #define MSR_NEHALEM_R0_PMON_IPERF0_P6 0x00000E0A
6172 Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.
6174 @param ECX MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)
6175 @param EAX Lower 32-bits of MSR value.
6176 @param EDX Upper 32-bits of MSR value.
6178 <b>Example usage</b>
6182 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);
6183 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);
6185 @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.
6187 #define MSR_NEHALEM_R0_PMON_IPERF0_P7 0x00000E0B
6191 Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.
6193 @param ECX MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)
6194 @param EAX Lower 32-bits of MSR value.
6195 @param EDX Upper 32-bits of MSR value.
6197 <b>Example usage</b>
6201 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);
6202 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);
6204 @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.
6206 #define MSR_NEHALEM_R0_PMON_QLX_P0 0x00000E0C
6210 Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.
6212 @param ECX MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)
6213 @param EAX Lower 32-bits of MSR value.
6214 @param EDX Upper 32-bits of MSR value.
6216 <b>Example usage</b>
6220 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);
6221 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);
6223 @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.
6225 #define MSR_NEHALEM_R0_PMON_QLX_P1 0x00000E0D
6229 Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.
6231 @param ECX MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)
6232 @param EAX Lower 32-bits of MSR value.
6233 @param EDX Upper 32-bits of MSR value.
6235 <b>Example usage</b>
6239 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);
6240 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);
6242 @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.
6244 #define MSR_NEHALEM_R0_PMON_QLX_P2 0x00000E0E
6248 Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.
6250 @param ECX MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)
6251 @param EAX Lower 32-bits of MSR value.
6252 @param EDX Upper 32-bits of MSR value.
6254 <b>Example usage</b>
6258 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);
6259 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);
6261 @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.
6263 #define MSR_NEHALEM_R0_PMON_QLX_P3 0x00000E0F
6267 Package. Uncore R-box 0 perfmon event select MSR.
6269 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)
6270 @param EAX Lower 32-bits of MSR value.
6271 @param EDX Upper 32-bits of MSR value.
6273 <b>Example usage</b>
6277 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);
6278 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);
6280 @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.
6282 #define MSR_NEHALEM_R0_PMON_EVNT_SEL0 0x00000E10
6286 Package. Uncore R-box 0 perfmon counter MSR.
6288 @param ECX MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)
6289 @param EAX Lower 32-bits of MSR value.
6290 @param EDX Upper 32-bits of MSR value.
6292 <b>Example usage</b>
6296 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);
6297 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);
6299 @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.
6301 #define MSR_NEHALEM_R0_PMON_CTR0 0x00000E11
6305 Package. Uncore R-box 0 perfmon event select MSR.
6307 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)
6308 @param EAX Lower 32-bits of MSR value.
6309 @param EDX Upper 32-bits of MSR value.
6311 <b>Example usage</b>
6315 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);
6316 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);
6318 @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.
6320 #define MSR_NEHALEM_R0_PMON_EVNT_SEL1 0x00000E12
6324 Package. Uncore R-box 0 perfmon counter MSR.
6326 @param ECX MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)
6327 @param EAX Lower 32-bits of MSR value.
6328 @param EDX Upper 32-bits of MSR value.
6330 <b>Example usage</b>
6334 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);
6335 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);
6337 @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.
6339 #define MSR_NEHALEM_R0_PMON_CTR1 0x00000E13
6343 Package. Uncore R-box 0 perfmon event select MSR.
6345 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)
6346 @param EAX Lower 32-bits of MSR value.
6347 @param EDX Upper 32-bits of MSR value.
6349 <b>Example usage</b>
6353 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);
6354 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);
6356 @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.
6358 #define MSR_NEHALEM_R0_PMON_EVNT_SEL2 0x00000E14
6362 Package. Uncore R-box 0 perfmon counter MSR.
6364 @param ECX MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)
6365 @param EAX Lower 32-bits of MSR value.
6366 @param EDX Upper 32-bits of MSR value.
6368 <b>Example usage</b>
6372 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);
6373 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);
6375 @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.
6377 #define MSR_NEHALEM_R0_PMON_CTR2 0x00000E15
6381 Package. Uncore R-box 0 perfmon event select MSR.
6383 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)
6384 @param EAX Lower 32-bits of MSR value.
6385 @param EDX Upper 32-bits of MSR value.
6387 <b>Example usage</b>
6391 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);
6392 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);
6394 @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.
6396 #define MSR_NEHALEM_R0_PMON_EVNT_SEL3 0x00000E16
6400 Package. Uncore R-box 0 perfmon counter MSR.
6402 @param ECX MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)
6403 @param EAX Lower 32-bits of MSR value.
6404 @param EDX Upper 32-bits of MSR value.
6406 <b>Example usage</b>
6410 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);
6411 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);
6413 @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.
6415 #define MSR_NEHALEM_R0_PMON_CTR3 0x00000E17
6419 Package. Uncore R-box 0 perfmon event select MSR.
6421 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)
6422 @param EAX Lower 32-bits of MSR value.
6423 @param EDX Upper 32-bits of MSR value.
6425 <b>Example usage</b>
6429 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);
6430 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);
6432 @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.
6434 #define MSR_NEHALEM_R0_PMON_EVNT_SEL4 0x00000E18
6438 Package. Uncore R-box 0 perfmon counter MSR.
6440 @param ECX MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)
6441 @param EAX Lower 32-bits of MSR value.
6442 @param EDX Upper 32-bits of MSR value.
6444 <b>Example usage</b>
6448 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);
6449 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);
6451 @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.
6453 #define MSR_NEHALEM_R0_PMON_CTR4 0x00000E19
6457 Package. Uncore R-box 0 perfmon event select MSR.
6459 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)
6460 @param EAX Lower 32-bits of MSR value.
6461 @param EDX Upper 32-bits of MSR value.
6463 <b>Example usage</b>
6467 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);
6468 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);
6470 @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.
6472 #define MSR_NEHALEM_R0_PMON_EVNT_SEL5 0x00000E1A
6476 Package. Uncore R-box 0 perfmon counter MSR.
6478 @param ECX MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)
6479 @param EAX Lower 32-bits of MSR value.
6480 @param EDX Upper 32-bits of MSR value.
6482 <b>Example usage</b>
6486 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);
6487 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);
6489 @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.
6491 #define MSR_NEHALEM_R0_PMON_CTR5 0x00000E1B
6495 Package. Uncore R-box 0 perfmon event select MSR.
6497 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)
6498 @param EAX Lower 32-bits of MSR value.
6499 @param EDX Upper 32-bits of MSR value.
6501 <b>Example usage</b>
6505 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);
6506 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);
6508 @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.
6510 #define MSR_NEHALEM_R0_PMON_EVNT_SEL6 0x00000E1C
6514 Package. Uncore R-box 0 perfmon counter MSR.
6516 @param ECX MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)
6517 @param EAX Lower 32-bits of MSR value.
6518 @param EDX Upper 32-bits of MSR value.
6520 <b>Example usage</b>
6524 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);
6525 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);
6527 @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.
6529 #define MSR_NEHALEM_R0_PMON_CTR6 0x00000E1D
6533 Package. Uncore R-box 0 perfmon event select MSR.
6535 @param ECX MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)
6536 @param EAX Lower 32-bits of MSR value.
6537 @param EDX Upper 32-bits of MSR value.
6539 <b>Example usage</b>
6543 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);
6544 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);
6546 @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.
6548 #define MSR_NEHALEM_R0_PMON_EVNT_SEL7 0x00000E1E
6552 Package. Uncore R-box 0 perfmon counter MSR.
6554 @param ECX MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)
6555 @param EAX Lower 32-bits of MSR value.
6556 @param EDX Upper 32-bits of MSR value.
6558 <b>Example usage</b>
6562 Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);
6563 AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);
6565 @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.
6567 #define MSR_NEHALEM_R0_PMON_CTR7 0x00000E1F
6571 Package. Uncore R-box 1 perfmon local box control MSR.
6573 @param ECX MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)
6574 @param EAX Lower 32-bits of MSR value.
6575 @param EDX Upper 32-bits of MSR value.
6577 <b>Example usage</b>
6581 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);
6582 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);
6584 @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.
6586 #define MSR_NEHALEM_R1_PMON_BOX_CTRL 0x00000E20
6590 Package. Uncore R-box 1 perfmon local box status MSR.
6592 @param ECX MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)
6593 @param EAX Lower 32-bits of MSR value.
6594 @param EDX Upper 32-bits of MSR value.
6596 <b>Example usage</b>
6600 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);
6601 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);
6603 @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.
6605 #define MSR_NEHALEM_R1_PMON_BOX_STATUS 0x00000E21
6609 Package. Uncore R-box 1 perfmon local box overflow control MSR.
6611 @param ECX MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)
6612 @param EAX Lower 32-bits of MSR value.
6613 @param EDX Upper 32-bits of MSR value.
6615 <b>Example usage</b>
6619 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);
6620 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);
6622 @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.
6624 #define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL 0x00000E22
6628 Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.
6630 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)
6631 @param EAX Lower 32-bits of MSR value.
6632 @param EDX Upper 32-bits of MSR value.
6634 <b>Example usage</b>
6638 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);
6639 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);
6641 @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.
6643 #define MSR_NEHALEM_R1_PMON_IPERF1_P8 0x00000E24
6647 Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.
6649 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)
6650 @param EAX Lower 32-bits of MSR value.
6651 @param EDX Upper 32-bits of MSR value.
6653 <b>Example usage</b>
6657 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);
6658 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);
6660 @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.
6662 #define MSR_NEHALEM_R1_PMON_IPERF1_P9 0x00000E25
6666 Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.
6668 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)
6669 @param EAX Lower 32-bits of MSR value.
6670 @param EDX Upper 32-bits of MSR value.
6672 <b>Example usage</b>
6676 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);
6677 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);
6679 @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.
6681 #define MSR_NEHALEM_R1_PMON_IPERF1_P10 0x00000E26
6685 Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.
6687 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)
6688 @param EAX Lower 32-bits of MSR value.
6689 @param EDX Upper 32-bits of MSR value.
6691 <b>Example usage</b>
6695 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);
6696 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);
6698 @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.
6700 #define MSR_NEHALEM_R1_PMON_IPERF1_P11 0x00000E27
6704 Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.
6706 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)
6707 @param EAX Lower 32-bits of MSR value.
6708 @param EDX Upper 32-bits of MSR value.
6710 <b>Example usage</b>
6714 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);
6715 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);
6717 @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.
6719 #define MSR_NEHALEM_R1_PMON_IPERF1_P12 0x00000E28
6723 Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.
6725 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)
6726 @param EAX Lower 32-bits of MSR value.
6727 @param EDX Upper 32-bits of MSR value.
6729 <b>Example usage</b>
6733 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);
6734 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);
6736 @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.
6738 #define MSR_NEHALEM_R1_PMON_IPERF1_P13 0x00000E29
6742 Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.
6744 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)
6745 @param EAX Lower 32-bits of MSR value.
6746 @param EDX Upper 32-bits of MSR value.
6748 <b>Example usage</b>
6752 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);
6753 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);
6755 @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.
6757 #define MSR_NEHALEM_R1_PMON_IPERF1_P14 0x00000E2A
6761 Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.
6763 @param ECX MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)
6764 @param EAX Lower 32-bits of MSR value.
6765 @param EDX Upper 32-bits of MSR value.
6767 <b>Example usage</b>
6771 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);
6772 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);
6774 @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.
6776 #define MSR_NEHALEM_R1_PMON_IPERF1_P15 0x00000E2B
6780 Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.
6782 @param ECX MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)
6783 @param EAX Lower 32-bits of MSR value.
6784 @param EDX Upper 32-bits of MSR value.
6786 <b>Example usage</b>
6790 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);
6791 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);
6793 @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.
6795 #define MSR_NEHALEM_R1_PMON_QLX_P4 0x00000E2C
6799 Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.
6801 @param ECX MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)
6802 @param EAX Lower 32-bits of MSR value.
6803 @param EDX Upper 32-bits of MSR value.
6805 <b>Example usage</b>
6809 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);
6810 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);
6812 @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.
6814 #define MSR_NEHALEM_R1_PMON_QLX_P5 0x00000E2D
6818 Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.
6820 @param ECX MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)
6821 @param EAX Lower 32-bits of MSR value.
6822 @param EDX Upper 32-bits of MSR value.
6824 <b>Example usage</b>
6828 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);
6829 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);
6831 @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.
6833 #define MSR_NEHALEM_R1_PMON_QLX_P6 0x00000E2E
6837 Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.
6839 @param ECX MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)
6840 @param EAX Lower 32-bits of MSR value.
6841 @param EDX Upper 32-bits of MSR value.
6843 <b>Example usage</b>
6847 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);
6848 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);
6850 @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.
6852 #define MSR_NEHALEM_R1_PMON_QLX_P7 0x00000E2F
6856 Package. Uncore R-box 1 perfmon event select MSR.
6858 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)
6859 @param EAX Lower 32-bits of MSR value.
6860 @param EDX Upper 32-bits of MSR value.
6862 <b>Example usage</b>
6866 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);
6867 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);
6869 @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.
6871 #define MSR_NEHALEM_R1_PMON_EVNT_SEL8 0x00000E30
6875 Package. Uncore R-box 1 perfmon counter MSR.
6877 @param ECX MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)
6878 @param EAX Lower 32-bits of MSR value.
6879 @param EDX Upper 32-bits of MSR value.
6881 <b>Example usage</b>
6885 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);
6886 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);
6888 @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.
6890 #define MSR_NEHALEM_R1_PMON_CTR8 0x00000E31
6894 Package. Uncore R-box 1 perfmon event select MSR.
6896 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)
6897 @param EAX Lower 32-bits of MSR value.
6898 @param EDX Upper 32-bits of MSR value.
6900 <b>Example usage</b>
6904 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);
6905 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);
6907 @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.
6909 #define MSR_NEHALEM_R1_PMON_EVNT_SEL9 0x00000E32
6913 Package. Uncore R-box 1 perfmon counter MSR.
6915 @param ECX MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)
6916 @param EAX Lower 32-bits of MSR value.
6917 @param EDX Upper 32-bits of MSR value.
6919 <b>Example usage</b>
6923 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);
6924 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);
6926 @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.
6928 #define MSR_NEHALEM_R1_PMON_CTR9 0x00000E33
6932 Package. Uncore R-box 1 perfmon event select MSR.
6934 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)
6935 @param EAX Lower 32-bits of MSR value.
6936 @param EDX Upper 32-bits of MSR value.
6938 <b>Example usage</b>
6942 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);
6943 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);
6945 @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.
6947 #define MSR_NEHALEM_R1_PMON_EVNT_SEL10 0x00000E34
6951 Package. Uncore R-box 1 perfmon counter MSR.
6953 @param ECX MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)
6954 @param EAX Lower 32-bits of MSR value.
6955 @param EDX Upper 32-bits of MSR value.
6957 <b>Example usage</b>
6961 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);
6962 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);
6964 @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.
6966 #define MSR_NEHALEM_R1_PMON_CTR10 0x00000E35
6970 Package. Uncore R-box 1 perfmon event select MSR.
6972 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)
6973 @param EAX Lower 32-bits of MSR value.
6974 @param EDX Upper 32-bits of MSR value.
6976 <b>Example usage</b>
6980 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);
6981 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);
6983 @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.
6985 #define MSR_NEHALEM_R1_PMON_EVNT_SEL11 0x00000E36
6989 Package. Uncore R-box 1 perfmon counter MSR.
6991 @param ECX MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)
6992 @param EAX Lower 32-bits of MSR value.
6993 @param EDX Upper 32-bits of MSR value.
6995 <b>Example usage</b>
6999 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);
7000 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);
7002 @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.
7004 #define MSR_NEHALEM_R1_PMON_CTR11 0x00000E37
7008 Package. Uncore R-box 1 perfmon event select MSR.
7010 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)
7011 @param EAX Lower 32-bits of MSR value.
7012 @param EDX Upper 32-bits of MSR value.
7014 <b>Example usage</b>
7018 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);
7019 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);
7021 @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.
7023 #define MSR_NEHALEM_R1_PMON_EVNT_SEL12 0x00000E38
7027 Package. Uncore R-box 1 perfmon counter MSR.
7029 @param ECX MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)
7030 @param EAX Lower 32-bits of MSR value.
7031 @param EDX Upper 32-bits of MSR value.
7033 <b>Example usage</b>
7037 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);
7038 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);
7040 @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.
7042 #define MSR_NEHALEM_R1_PMON_CTR12 0x00000E39
7046 Package. Uncore R-box 1 perfmon event select MSR.
7048 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)
7049 @param EAX Lower 32-bits of MSR value.
7050 @param EDX Upper 32-bits of MSR value.
7052 <b>Example usage</b>
7056 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);
7057 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);
7059 @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.
7061 #define MSR_NEHALEM_R1_PMON_EVNT_SEL13 0x00000E3A
7065 Package. Uncore R-box 1perfmon counter MSR.
7067 @param ECX MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)
7068 @param EAX Lower 32-bits of MSR value.
7069 @param EDX Upper 32-bits of MSR value.
7071 <b>Example usage</b>
7075 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);
7076 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);
7078 @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.
7080 #define MSR_NEHALEM_R1_PMON_CTR13 0x00000E3B
7084 Package. Uncore R-box 1 perfmon event select MSR.
7086 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)
7087 @param EAX Lower 32-bits of MSR value.
7088 @param EDX Upper 32-bits of MSR value.
7090 <b>Example usage</b>
7094 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);
7095 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);
7097 @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.
7099 #define MSR_NEHALEM_R1_PMON_EVNT_SEL14 0x00000E3C
7103 Package. Uncore R-box 1 perfmon counter MSR.
7105 @param ECX MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)
7106 @param EAX Lower 32-bits of MSR value.
7107 @param EDX Upper 32-bits of MSR value.
7109 <b>Example usage</b>
7113 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);
7114 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);
7116 @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.
7118 #define MSR_NEHALEM_R1_PMON_CTR14 0x00000E3D
7122 Package. Uncore R-box 1 perfmon event select MSR.
7124 @param ECX MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)
7125 @param EAX Lower 32-bits of MSR value.
7126 @param EDX Upper 32-bits of MSR value.
7128 <b>Example usage</b>
7132 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);
7133 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);
7135 @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.
7137 #define MSR_NEHALEM_R1_PMON_EVNT_SEL15 0x00000E3E
7141 Package. Uncore R-box 1 perfmon counter MSR.
7143 @param ECX MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)
7144 @param EAX Lower 32-bits of MSR value.
7145 @param EDX Upper 32-bits of MSR value.
7147 <b>Example usage</b>
7151 Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);
7152 AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);
7154 @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.
7156 #define MSR_NEHALEM_R1_PMON_CTR15 0x00000E3F
7160 Package. Uncore B-box 0 perfmon local box match MSR.
7162 @param ECX MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)
7163 @param EAX Lower 32-bits of MSR value.
7164 @param EDX Upper 32-bits of MSR value.
7166 <b>Example usage</b>
7170 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);
7171 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);
7173 @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.
7175 #define MSR_NEHALEM_B0_PMON_MATCH 0x00000E45
7179 Package. Uncore B-box 0 perfmon local box mask MSR.
7181 @param ECX MSR_NEHALEM_B0_PMON_MASK (0x00000E46)
7182 @param EAX Lower 32-bits of MSR value.
7183 @param EDX Upper 32-bits of MSR value.
7185 <b>Example usage</b>
7189 Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);
7190 AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);
7192 @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.
7194 #define MSR_NEHALEM_B0_PMON_MASK 0x00000E46
7198 Package. Uncore S-box 0 perfmon local box match MSR.
7200 @param ECX MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)
7201 @param EAX Lower 32-bits of MSR value.
7202 @param EDX Upper 32-bits of MSR value.
7204 <b>Example usage</b>
7208 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);
7209 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);
7211 @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.
7213 #define MSR_NEHALEM_S0_PMON_MATCH 0x00000E49
7217 Package. Uncore S-box 0 perfmon local box mask MSR.
7219 @param ECX MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)
7220 @param EAX Lower 32-bits of MSR value.
7221 @param EDX Upper 32-bits of MSR value.
7223 <b>Example usage</b>
7227 Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);
7228 AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);
7230 @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.
7232 #define MSR_NEHALEM_S0_PMON_MASK 0x00000E4A
7236 Package. Uncore B-box 1 perfmon local box match MSR.
7238 @param ECX MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)
7239 @param EAX Lower 32-bits of MSR value.
7240 @param EDX Upper 32-bits of MSR value.
7242 <b>Example usage</b>
7246 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);
7247 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);
7249 @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.
7251 #define MSR_NEHALEM_B1_PMON_MATCH 0x00000E4D
7255 Package. Uncore B-box 1 perfmon local box mask MSR.
7257 @param ECX MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)
7258 @param EAX Lower 32-bits of MSR value.
7259 @param EDX Upper 32-bits of MSR value.
7261 <b>Example usage</b>
7265 Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);
7266 AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);
7268 @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.
7270 #define MSR_NEHALEM_B1_PMON_MASK 0x00000E4E
7274 Package. Uncore M-box 0 perfmon local box address match/mask config MSR.
7276 @param ECX MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)
7277 @param EAX Lower 32-bits of MSR value.
7278 @param EDX Upper 32-bits of MSR value.
7280 <b>Example usage</b>
7284 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);
7285 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);
7287 @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.
7289 #define MSR_NEHALEM_M0_PMON_MM_CONFIG 0x00000E54
7293 Package. Uncore M-box 0 perfmon local box address match MSR.
7295 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)
7296 @param EAX Lower 32-bits of MSR value.
7297 @param EDX Upper 32-bits of MSR value.
7299 <b>Example usage</b>
7303 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);
7304 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);
7306 @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.
7308 #define MSR_NEHALEM_M0_PMON_ADDR_MATCH 0x00000E55
7312 Package. Uncore M-box 0 perfmon local box address mask MSR.
7314 @param ECX MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)
7315 @param EAX Lower 32-bits of MSR value.
7316 @param EDX Upper 32-bits of MSR value.
7318 <b>Example usage</b>
7322 Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);
7323 AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);
7325 @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.
7327 #define MSR_NEHALEM_M0_PMON_ADDR_MASK 0x00000E56
7331 Package. Uncore S-box 1 perfmon local box match MSR.
7333 @param ECX MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)
7334 @param EAX Lower 32-bits of MSR value.
7335 @param EDX Upper 32-bits of MSR value.
7337 <b>Example usage</b>
7341 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);
7342 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);
7344 @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.
7346 #define MSR_NEHALEM_S1_PMON_MATCH 0x00000E59
7350 Package. Uncore S-box 1 perfmon local box mask MSR.
7352 @param ECX MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)
7353 @param EAX Lower 32-bits of MSR value.
7354 @param EDX Upper 32-bits of MSR value.
7356 <b>Example usage</b>
7360 Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);
7361 AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);
7363 @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.
7365 #define MSR_NEHALEM_S1_PMON_MASK 0x00000E5A
7369 Package. Uncore M-box 1 perfmon local box address match/mask config MSR.
7371 @param ECX MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)
7372 @param EAX Lower 32-bits of MSR value.
7373 @param EDX Upper 32-bits of MSR value.
7375 <b>Example usage</b>
7379 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);
7380 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);
7382 @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.
7384 #define MSR_NEHALEM_M1_PMON_MM_CONFIG 0x00000E5C
7388 Package. Uncore M-box 1 perfmon local box address match MSR.
7390 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)
7391 @param EAX Lower 32-bits of MSR value.
7392 @param EDX Upper 32-bits of MSR value.
7394 <b>Example usage</b>
7398 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);
7399 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);
7401 @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.
7403 #define MSR_NEHALEM_M1_PMON_ADDR_MATCH 0x00000E5D
7407 Package. Uncore M-box 1 perfmon local box address mask MSR.
7409 @param ECX MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)
7410 @param EAX Lower 32-bits of MSR value.
7411 @param EDX Upper 32-bits of MSR value.
7413 <b>Example usage</b>
7417 Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);
7418 AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);
7420 @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.
7422 #define MSR_NEHALEM_M1_PMON_ADDR_MASK 0x00000E5E