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1 /** @file
2 MSR Definitions for P6 Family Processors.
3
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
7 provided for that MSR.
8
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
11
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
15
16 **/
17
18 #ifndef __P6_MSR_H__
19 #define __P6_MSR_H__
20
21 #include <Register/Intel/ArchitecturalMsr.h>
22
23 /**
24 Is P6 Family Processors?
25
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
28
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
31 **/
32 #define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x03 || \
36 DisplayModel == 0x05 || \
37 DisplayModel == 0x07 || \
38 DisplayModel == 0x08 || \
39 DisplayModel == 0x0A || \
40 DisplayModel == 0x0B \
41 ) \
42 )
43
44 /**
45 See Section 2.22, "MSRs in Pentium Processors.".
46
47 @param ECX MSR_P6_P5_MC_ADDR (0x00000000)
48 @param EAX Lower 32-bits of MSR value.
49 @param EDX Upper 32-bits of MSR value.
50
51 <b>Example usage</b>
52 @code
53 UINT64 Msr;
54
55 Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);
56 AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);
57 @endcode
58 @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
59 **/
60 #define MSR_P6_P5_MC_ADDR 0x00000000
61
62 /**
63 See Section 2.22, "MSRs in Pentium Processors.".
64
65 @param ECX MSR_P6_P5_MC_TYPE (0x00000001)
66 @param EAX Lower 32-bits of MSR value.
67 @param EDX Upper 32-bits of MSR value.
68
69 <b>Example usage</b>
70 @code
71 UINT64 Msr;
72
73 Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);
74 AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);
75 @endcode
76 @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
77 **/
78 #define MSR_P6_P5_MC_TYPE 0x00000001
79
80 /**
81 See Section 17.17, "Time-Stamp Counter.".
82
83 @param ECX MSR_P6_TSC (0x00000010)
84 @param EAX Lower 32-bits of MSR value.
85 @param EDX Upper 32-bits of MSR value.
86
87 <b>Example usage</b>
88 @code
89 UINT64 Msr;
90
91 Msr = AsmReadMsr64 (MSR_P6_TSC);
92 AsmWriteMsr64 (MSR_P6_TSC, Msr);
93 @endcode
94 @note MSR_P6_TSC is defined as TSC in SDM.
95 **/
96 #define MSR_P6_TSC 0x00000010
97
98 /**
99 Platform ID (R) The operating system can use this MSR to determine "slot"
100 information for the processor and the proper microcode update to load.
101
102 @param ECX MSR_P6_IA32_PLATFORM_ID (0x00000017)
103 @param EAX Lower 32-bits of MSR value.
104 Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
105 @param EDX Upper 32-bits of MSR value.
106 Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
107
108 <b>Example usage</b>
109 @code
110 MSR_P6_IA32_PLATFORM_ID_REGISTER Msr;
111
112 Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);
113 @endcode
114 @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
115 **/
116 #define MSR_P6_IA32_PLATFORM_ID 0x00000017
117
118 /**
119 MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID
120 **/
121 typedef union {
122 ///
123 /// Individual bit fields
124 ///
125 struct {
126 UINT32 Reserved1 : 32;
127 UINT32 Reserved2 : 18;
128 ///
129 /// [Bits 52:50] Platform Id (R) Contains information concerning the
130 /// intended platform for the processor.
131 ///
132 /// 52 51 50
133 /// 0 0 0 Processor Flag 0.
134 /// 0 0 1 Processor Flag 1
135 /// 0 1 0 Processor Flag 2
136 /// 0 1 1 Processor Flag 3
137 /// 1 0 0 Processor Flag 4
138 /// 1 0 1 Processor Flag 5
139 /// 1 1 0 Processor Flag 6
140 /// 1 1 1 Processor Flag 7
141 ///
142 UINT32 PlatformId : 3;
143 ///
144 /// [Bits 56:53] L2 Cache Latency Read.
145 ///
146 UINT32 L2CacheLatencyRead : 4;
147 UINT32 Reserved3 : 3;
148 ///
149 /// [Bit 60] Clock Frequency Ratio Read.
150 ///
151 UINT32 ClockFrequencyRatioRead : 1;
152 UINT32 Reserved4 : 3;
153 } Bits;
154 ///
155 /// All bit fields as a 64-bit value
156 ///
157 UINT64 Uint64;
158 } MSR_P6_IA32_PLATFORM_ID_REGISTER;
159
160 /**
161 Section 10.4.4, "Local APIC Status and Location.".
162
163 @param ECX MSR_P6_APIC_BASE (0x0000001B)
164 @param EAX Lower 32-bits of MSR value.
165 Described by the type MSR_P6_APIC_BASE_REGISTER.
166 @param EDX Upper 32-bits of MSR value.
167 Described by the type MSR_P6_APIC_BASE_REGISTER.
168
169 <b>Example usage</b>
170 @code
171 MSR_P6_APIC_BASE_REGISTER Msr;
172
173 Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);
174 AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);
175 @endcode
176 @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.
177 **/
178 #define MSR_P6_APIC_BASE 0x0000001B
179
180 /**
181 MSR information returned for MSR index #MSR_P6_APIC_BASE
182 **/
183 typedef union {
184 ///
185 /// Individual bit fields
186 ///
187 struct {
188 UINT32 Reserved1 : 8;
189 ///
190 /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP.
191 ///
192 UINT32 BSP : 1;
193 UINT32 Reserved2 : 2;
194 ///
195 /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 =
196 /// Disabled.
197 ///
198 UINT32 EN : 1;
199 ///
200 /// [Bits 31:12] APIC Base Address.
201 ///
202 UINT32 ApicBase : 20;
203 UINT32 Reserved3 : 32;
204 } Bits;
205 ///
206 /// All bit fields as a 32-bit value
207 ///
208 UINT32 Uint32;
209 ///
210 /// All bit fields as a 64-bit value
211 ///
212 UINT64 Uint64;
213 } MSR_P6_APIC_BASE_REGISTER;
214
215 /**
216 Processor Hard Power-On Configuration (R/W) Enables and disables processor
217 features; (R) indicates current processor configuration.
218
219 @param ECX MSR_P6_EBL_CR_POWERON (0x0000002A)
220 @param EAX Lower 32-bits of MSR value.
221 Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
222 @param EDX Upper 32-bits of MSR value.
223 Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
224
225 <b>Example usage</b>
226 @code
227 MSR_P6_EBL_CR_POWERON_REGISTER Msr;
228
229 Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);
230 AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);
231 @endcode
232 @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.
233 **/
234 #define MSR_P6_EBL_CR_POWERON 0x0000002A
235
236 /**
237 MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON
238 **/
239 typedef union {
240 ///
241 /// Individual bit fields
242 ///
243 struct {
244 UINT32 Reserved1 : 1;
245 ///
246 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.
247 ///
248 UINT32 DataErrorCheckingEnable : 1;
249 ///
250 /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W)
251 /// 1 = Enabled 0 = Disabled.
252 ///
253 UINT32 ResponseErrorCheckingEnable : 1;
254 ///
255 /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.
256 ///
257 UINT32 AERR_DriveEnable : 1;
258 ///
259 /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 =
260 /// Disabled.
261 ///
262 UINT32 BERR_Enable : 1;
263 UINT32 Reserved2 : 1;
264 ///
265 /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 =
266 /// Enabled 0 = Disabled.
267 ///
268 UINT32 BERR_DriverEnable : 1;
269 ///
270 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.
271 ///
272 UINT32 BINIT_DriverEnable : 1;
273 ///
274 /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.
275 ///
276 UINT32 OutputTriStateEnable : 1;
277 ///
278 /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.
279 ///
280 UINT32 ExecuteBIST : 1;
281 ///
282 /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.
283 ///
284 UINT32 AERR_ObservationEnabled : 1;
285 UINT32 Reserved3 : 1;
286 ///
287 /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.
288 ///
289 UINT32 BINIT_ObservationEnabled : 1;
290 ///
291 /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.
292 ///
293 UINT32 InOrderQueueDepth : 1;
294 ///
295 /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.
296 ///
297 UINT32 ResetVector : 1;
298 ///
299 /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.
300 ///
301 UINT32 FRCModeEnable : 1;
302 ///
303 /// [Bits 17:16] APIC Cluster ID (R).
304 ///
305 UINT32 APICClusterID : 2;
306 ///
307 /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 =
308 /// 133MHz 11 = Reserved.
309 ///
310 UINT32 SystemBusFrequency : 2;
311 ///
312 /// [Bits 21:20] Symmetric Arbitration ID (R).
313 ///
314 UINT32 SymmetricArbitrationID : 2;
315 ///
316 /// [Bits 25:22] Clock Frequency Ratio (R).
317 ///
318 UINT32 ClockFrequencyRatio : 4;
319 ///
320 /// [Bit 26] Low Power Mode Enable (R/W).
321 ///
322 UINT32 LowPowerModeEnable : 1;
323 ///
324 /// [Bit 27] Clock Frequency Ratio.
325 ///
326 UINT32 ClockFrequencyRatio1 : 1;
327 UINT32 Reserved4 : 4;
328 UINT32 Reserved5 : 32;
329 } Bits;
330 ///
331 /// All bit fields as a 32-bit value
332 ///
333 UINT32 Uint32;
334 ///
335 /// All bit fields as a 64-bit value
336 ///
337 UINT64 Uint64;
338 } MSR_P6_EBL_CR_POWERON_REGISTER;
339
340 /**
341 Test Control Register.
342
343 @param ECX MSR_P6_TEST_CTL (0x00000033)
344 @param EAX Lower 32-bits of MSR value.
345 Described by the type MSR_P6_TEST_CTL_REGISTER.
346 @param EDX Upper 32-bits of MSR value.
347 Described by the type MSR_P6_TEST_CTL_REGISTER.
348
349 <b>Example usage</b>
350 @code
351 MSR_P6_TEST_CTL_REGISTER Msr;
352
353 Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);
354 AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);
355 @endcode
356 @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.
357 **/
358 #define MSR_P6_TEST_CTL 0x00000033
359
360 /**
361 MSR information returned for MSR index #MSR_P6_TEST_CTL
362 **/
363 typedef union {
364 ///
365 /// Individual bit fields
366 ///
367 struct {
368 UINT32 Reserved1 : 30;
369 ///
370 /// [Bit 30] Streaming Buffer Disable.
371 ///
372 UINT32 StreamingBufferDisable : 1;
373 ///
374 /// [Bit 31] Disable LOCK# Assertion for split locked access.
375 ///
376 UINT32 Disable_LOCK : 1;
377 UINT32 Reserved2 : 32;
378 } Bits;
379 ///
380 /// All bit fields as a 32-bit value
381 ///
382 UINT32 Uint32;
383 ///
384 /// All bit fields as a 64-bit value
385 ///
386 UINT64 Uint64;
387 } MSR_P6_TEST_CTL_REGISTER;
388
389 /**
390 BIOS Update Trigger Register.
391
392 @param ECX MSR_P6_BIOS_UPDT_TRIG (0x00000079)
393 @param EAX Lower 32-bits of MSR value.
394 @param EDX Upper 32-bits of MSR value.
395
396 <b>Example usage</b>
397 @code
398 UINT64 Msr;
399
400 Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);
401 AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);
402 @endcode
403 @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.
404 **/
405 #define MSR_P6_BIOS_UPDT_TRIG 0x00000079
406
407 /**
408 Chunk n data register D[63:0]: used to write to and read from the L2.
409
410 @param ECX MSR_P6_BBL_CR_Dn
411 @param EAX Lower 32-bits of MSR value.
412 @param EDX Upper 32-bits of MSR value.
413
414 <b>Example usage</b>
415 @code
416 UINT64 Msr;
417
418 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);
419 AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);
420 @endcode
421 @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM.
422 MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM.
423 MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.
424 @{
425 **/
426 #define MSR_P6_BBL_CR_D0 0x00000088
427 #define MSR_P6_BBL_CR_D1 0x00000089
428 #define MSR_P6_BBL_CR_D2 0x0000008A
429 /// @}
430
431 /**
432 BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to
433 write to and read from the L2 depending on the usage model.
434
435 @param ECX MSR_P6_BIOS_SIGN (0x0000008B)
436 @param EAX Lower 32-bits of MSR value.
437 @param EDX Upper 32-bits of MSR value.
438
439 <b>Example usage</b>
440 @code
441 UINT64 Msr;
442
443 Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);
444 AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);
445 @endcode
446 @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.
447 **/
448 #define MSR_P6_BIOS_SIGN 0x0000008B
449
450 /**
451
452
453 @param ECX MSR_P6_PERFCTR0 (0x000000C1)
454 @param EAX Lower 32-bits of MSR value.
455 @param EDX Upper 32-bits of MSR value.
456
457 <b>Example usage</b>
458 @code
459 UINT64 Msr;
460
461 Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);
462 AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);
463 @endcode
464 @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM.
465 MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.
466 @{
467 **/
468 #define MSR_P6_PERFCTR0 0x000000C1
469 #define MSR_P6_PERFCTR1 0x000000C2
470 /// @}
471
472 /**
473
474
475 @param ECX MSR_P6_MTRRCAP (0x000000FE)
476 @param EAX Lower 32-bits of MSR value.
477 @param EDX Upper 32-bits of MSR value.
478
479 <b>Example usage</b>
480 @code
481 UINT64 Msr;
482
483 Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);
484 AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);
485 @endcode
486 @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.
487 **/
488 #define MSR_P6_MTRRCAP 0x000000FE
489
490 /**
491 Address register: used to send specified address (A31-A3) to L2 during cache
492 initialization accesses.
493
494 @param ECX MSR_P6_BBL_CR_ADDR (0x00000116)
495 @param EAX Lower 32-bits of MSR value.
496 Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
497 @param EDX Upper 32-bits of MSR value.
498 Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
499
500 <b>Example usage</b>
501 @code
502 MSR_P6_BBL_CR_ADDR_REGISTER Msr;
503
504 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);
505 AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);
506 @endcode
507 @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.
508 **/
509 #define MSR_P6_BBL_CR_ADDR 0x00000116
510
511 /**
512 MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR
513 **/
514 typedef union {
515 ///
516 /// Individual bit fields
517 ///
518 struct {
519 UINT32 Reserved1 : 3;
520 ///
521 /// [Bits 31:3] Address bits
522 ///
523 UINT32 Address : 29;
524 UINT32 Reserved2 : 32;
525 } Bits;
526 ///
527 /// All bit fields as a 32-bit value
528 ///
529 UINT32 Uint32;
530 ///
531 /// All bit fields as a 64-bit value
532 ///
533 UINT64 Uint64;
534 } MSR_P6_BBL_CR_ADDR_REGISTER;
535
536 /**
537 Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.
538
539 @param ECX MSR_P6_BBL_CR_DECC (0x00000118)
540 @param EAX Lower 32-bits of MSR value.
541 @param EDX Upper 32-bits of MSR value.
542
543 <b>Example usage</b>
544 @code
545 UINT64 Msr;
546
547 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);
548 AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);
549 @endcode
550 @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.
551 **/
552 #define MSR_P6_BBL_CR_DECC 0x00000118
553
554 /**
555 Control register: used to program L2 commands to be issued via cache
556 configuration accesses mechanism. Also receives L2 lookup response.
557
558 @param ECX MSR_P6_BBL_CR_CTL (0x00000119)
559 @param EAX Lower 32-bits of MSR value.
560 Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
561 @param EDX Upper 32-bits of MSR value.
562 Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
563
564 <b>Example usage</b>
565 @code
566 MSR_P6_BBL_CR_CTL_REGISTER Msr;
567
568 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);
569 AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);
570 @endcode
571 @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.
572 **/
573 #define MSR_P6_BBL_CR_CTL 0x00000119
574
575 /**
576 MSR information returned for MSR index #MSR_P6_BBL_CR_CTL
577 **/
578 typedef union {
579 ///
580 /// Individual bit fields
581 ///
582 struct {
583 ///
584 /// [Bits 4:0] L2 Command
585 /// Data Read w/ LRU update (RLU)
586 /// Tag Read w/ Data Read (TRR)
587 /// Tag Inquire (TI)
588 /// L2 Control Register Read (CR)
589 /// L2 Control Register Write (CW)
590 /// Tag Write w/ Data Read (TWR)
591 /// Tag Write w/ Data Write (TWW)
592 /// Tag Write (TW).
593 ///
594 UINT32 L2Command : 5;
595 ///
596 /// [Bits 6:5] State to L2
597 ///
598 UINT32 StateToL2 : 2;
599 UINT32 Reserved : 1;
600 ///
601 /// [Bits 9:8] Way to L2.
602 ///
603 UINT32 WayToL2 : 2;
604 ///
605 /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.
606 ///
607 UINT32 Way : 2;
608 ///
609 /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.
610 ///
611 UINT32 MESI : 2;
612 ///
613 /// [Bits 15:14] State from L2.
614 ///
615 UINT32 StateFromL2 : 2;
616 UINT32 Reserved2 : 1;
617 ///
618 /// [Bit 17] L2 Hit.
619 ///
620 UINT32 L2Hit : 1;
621 UINT32 Reserved3 : 1;
622 ///
623 /// [Bits 20:19] User supplied ECC.
624 ///
625 UINT32 UserEcc : 2;
626 ///
627 /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved.
628 ///
629 UINT32 ProcessorNumber : 1;
630 UINT32 Reserved4 : 10;
631 UINT32 Reserved5 : 32;
632 } Bits;
633 ///
634 /// All bit fields as a 32-bit value
635 ///
636 UINT32 Uint32;
637 ///
638 /// All bit fields as a 64-bit value
639 ///
640 UINT64 Uint64;
641 } MSR_P6_BBL_CR_CTL_REGISTER;
642
643 /**
644 Trigger register: used to initiate a cache configuration accesses access,
645 Write only with Data = 0.
646
647 @param ECX MSR_P6_BBL_CR_TRIG (0x0000011A)
648 @param EAX Lower 32-bits of MSR value.
649 @param EDX Upper 32-bits of MSR value.
650
651 <b>Example usage</b>
652 @code
653 UINT64 Msr;
654
655 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);
656 AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);
657 @endcode
658 @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.
659 **/
660 #define MSR_P6_BBL_CR_TRIG 0x0000011A
661
662 /**
663 Busy register: indicates when a cache configuration accesses L2 command is
664 in progress. D[0] = 1 = BUSY.
665
666 @param ECX MSR_P6_BBL_CR_BUSY (0x0000011B)
667 @param EAX Lower 32-bits of MSR value.
668 @param EDX Upper 32-bits of MSR value.
669
670 <b>Example usage</b>
671 @code
672 UINT64 Msr;
673
674 Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);
675 AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);
676 @endcode
677 @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM.
678 **/
679 #define MSR_P6_BBL_CR_BUSY 0x0000011B
680
681 /**
682 Control register 3: used to configure the L2 Cache.
683
684 @param ECX MSR_P6_BBL_CR_CTL3 (0x0000011E)
685 @param EAX Lower 32-bits of MSR value.
686 Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
687 @param EDX Upper 32-bits of MSR value.
688 Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
689
690 <b>Example usage</b>
691 @code
692 MSR_P6_BBL_CR_CTL3_REGISTER Msr;
693
694 Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);
695 AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);
696 @endcode
697 @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM.
698 **/
699 #define MSR_P6_BBL_CR_CTL3 0x0000011E
700
701 /**
702 MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3
703 **/
704 typedef union {
705 ///
706 /// Individual bit fields
707 ///
708 struct {
709 ///
710 /// [Bit 0] L2 Configured (read/write ).
711 ///
712 UINT32 L2Configured : 1;
713 ///
714 /// [Bits 4:1] L2 Cache Latency (read/write).
715 ///
716 UINT32 L2CacheLatency : 4;
717 ///
718 /// [Bit 5] ECC Check Enable (read/write).
719 ///
720 UINT32 ECCCheckEnable : 1;
721 ///
722 /// [Bit 6] Address Parity Check Enable (read/write).
723 ///
724 UINT32 AddressParityCheckEnable : 1;
725 ///
726 /// [Bit 7] CRTN Parity Check Enable (read/write).
727 ///
728 UINT32 CRTNParityCheckEnable : 1;
729 ///
730 /// [Bit 8] L2 Enabled (read/write).
731 ///
732 UINT32 L2Enabled : 1;
733 ///
734 /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way
735 /// Reserved.
736 ///
737 UINT32 L2Associativity : 2;
738 ///
739 /// [Bits 12:11] Number of L2 banks (read only).
740 ///
741 UINT32 L2Banks : 2;
742 ///
743 /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes
744 /// 1MByte 2MByte 4MBytes.
745 ///
746 UINT32 CacheSizePerBank : 5;
747 ///
748 /// [Bit 18] Cache State error checking enable (read/write).
749 ///
750 UINT32 CacheStateErrorEnable : 1;
751 UINT32 Reserved1 : 1;
752 ///
753 /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes
754 /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.
755 ///
756 UINT32 L2AddressRange : 3;
757 ///
758 /// [Bit 23] L2 Hardware Disable (read only).
759 ///
760 UINT32 L2HardwareDisable : 1;
761 UINT32 Reserved2 : 1;
762 ///
763 /// [Bit 25] Cache bus fraction (read only).
764 ///
765 UINT32 CacheBusFraction : 1;
766 UINT32 Reserved3 : 6;
767 UINT32 Reserved4 : 32;
768 } Bits;
769 ///
770 /// All bit fields as a 32-bit value
771 ///
772 UINT32 Uint32;
773 ///
774 /// All bit fields as a 64-bit value
775 ///
776 UINT64 Uint64;
777 } MSR_P6_BBL_CR_CTL3_REGISTER;
778
779 /**
780 CS register target for CPL 0 code.
781
782 @param ECX MSR_P6_SYSENTER_CS_MSR (0x00000174)
783 @param EAX Lower 32-bits of MSR value.
784 @param EDX Upper 32-bits of MSR value.
785
786 <b>Example usage</b>
787 @code
788 UINT64 Msr;
789
790 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);
791 AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);
792 @endcode
793 @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM.
794 **/
795 #define MSR_P6_SYSENTER_CS_MSR 0x00000174
796
797 /**
798 Stack pointer for CPL 0 stack.
799
800 @param ECX MSR_P6_SYSENTER_ESP_MSR (0x00000175)
801 @param EAX Lower 32-bits of MSR value.
802 @param EDX Upper 32-bits of MSR value.
803
804 <b>Example usage</b>
805 @code
806 UINT64 Msr;
807
808 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);
809 AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);
810 @endcode
811 @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM.
812 **/
813 #define MSR_P6_SYSENTER_ESP_MSR 0x00000175
814
815 /**
816 CPL 0 code entry point.
817
818 @param ECX MSR_P6_SYSENTER_EIP_MSR (0x00000176)
819 @param EAX Lower 32-bits of MSR value.
820 @param EDX Upper 32-bits of MSR value.
821
822 <b>Example usage</b>
823 @code
824 UINT64 Msr;
825
826 Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);
827 AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);
828 @endcode
829 @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM.
830 **/
831 #define MSR_P6_SYSENTER_EIP_MSR 0x00000176
832
833 /**
834
835
836 @param ECX MSR_P6_MCG_CAP (0x00000179)
837 @param EAX Lower 32-bits of MSR value.
838 @param EDX Upper 32-bits of MSR value.
839
840 <b>Example usage</b>
841 @code
842 UINT64 Msr;
843
844 Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);
845 AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);
846 @endcode
847 @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM.
848 **/
849 #define MSR_P6_MCG_CAP 0x00000179
850
851 /**
852
853
854 @param ECX MSR_P6_MCG_STATUS (0x0000017A)
855 @param EAX Lower 32-bits of MSR value.
856 @param EDX Upper 32-bits of MSR value.
857
858 <b>Example usage</b>
859 @code
860 UINT64 Msr;
861
862 Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);
863 AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);
864 @endcode
865 @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM.
866 **/
867 #define MSR_P6_MCG_STATUS 0x0000017A
868
869 /**
870
871
872 @param ECX MSR_P6_MCG_CTL (0x0000017B)
873 @param EAX Lower 32-bits of MSR value.
874 @param EDX Upper 32-bits of MSR value.
875
876 <b>Example usage</b>
877 @code
878 UINT64 Msr;
879
880 Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);
881 AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);
882 @endcode
883 @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM.
884 **/
885 #define MSR_P6_MCG_CTL 0x0000017B
886
887 /**
888
889
890 @param ECX MSR_P6_PERFEVTSELn
891 @param EAX Lower 32-bits of MSR value.
892 Described by the type MSR_P6_PERFEVTSEL_REGISTER.
893 @param EDX Upper 32-bits of MSR value.
894 Described by the type MSR_P6_PERFEVTSEL_REGISTER.
895
896 <b>Example usage</b>
897 @code
898 MSR_P6_PERFEVTSEL_REGISTER Msr;
899
900 Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);
901 AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);
902 @endcode
903 @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM.
904 MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.
905 @{
906 **/
907 #define MSR_P6_PERFEVTSEL0 0x00000186
908 #define MSR_P6_PERFEVTSEL1 0x00000187
909 /// @}
910
911 /**
912 MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and
913 #MSR_P6_PERFEVTSEL1.
914 **/
915 typedef union {
916 ///
917 /// Individual bit fields
918 ///
919 struct {
920 ///
921 /// [Bits 7:0] Event Select Refer to Performance Counter section for a
922 /// list of event encodings.
923 ///
924 UINT32 EventSelect : 8;
925 ///
926 /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable
927 /// all count options.
928 ///
929 UINT32 UMASK : 8;
930 ///
931 /// [Bit 16] USER Controls the counting of events at Privilege levels of
932 /// 1, 2, and 3.
933 ///
934 UINT32 USR : 1;
935 ///
936 /// [Bit 17] OS Controls the counting of events at Privilege level of 0.
937 ///
938 UINT32 OS : 1;
939 ///
940 /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.
941 ///
942 UINT32 E : 1;
943 ///
944 /// [Bit 19] PC Enabled the signaling of performance counter overflow via
945 /// BP0 pin.
946 ///
947 UINT32 PC : 1;
948 ///
949 /// [Bit 20] INT Enables the signaling of counter overflow via input to
950 /// APIC 1 = Enable 0 = Disable.
951 ///
952 UINT32 INT : 1;
953 UINT32 Reserved1 : 1;
954 ///
955 /// [Bit 22] ENABLE Enables the counting of performance events in both
956 /// counters 1 = Enable 0 = Disable.
957 ///
958 UINT32 EN : 1;
959 ///
960 /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0
961 /// = Non-Inverted.
962 ///
963 UINT32 INV : 1;
964 ///
965 /// [Bits 31:24] CMASK (Counter Mask).
966 ///
967 UINT32 CMASK : 8;
968 UINT32 Reserved2 : 32;
969 } Bits;
970 ///
971 /// All bit fields as a 32-bit value
972 ///
973 UINT32 Uint32;
974 ///
975 /// All bit fields as a 64-bit value
976 ///
977 UINT64 Uint64;
978 } MSR_P6_PERFEVTSEL_REGISTER;
979
980 /**
981
982
983 @param ECX MSR_P6_DEBUGCTLMSR (0x000001D9)
984 @param EAX Lower 32-bits of MSR value.
985 Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
986 @param EDX Upper 32-bits of MSR value.
987 Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
988
989 <b>Example usage</b>
990 @code
991 MSR_P6_DEBUGCTLMSR_REGISTER Msr;
992
993 Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);
994 AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);
995 @endcode
996 @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM.
997 **/
998 #define MSR_P6_DEBUGCTLMSR 0x000001D9
999
1000 /**
1001 MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR
1002 **/
1003 typedef union {
1004 ///
1005 /// Individual bit fields
1006 ///
1007 struct {
1008 ///
1009 /// [Bit 0] Enable/Disable Last Branch Records.
1010 ///
1011 UINT32 LBR : 1;
1012 ///
1013 /// [Bit 1] Branch Trap Flag.
1014 ///
1015 UINT32 BTF : 1;
1016 ///
1017 /// [Bit 2] Performance Monitoring/Break Point Pins.
1018 ///
1019 UINT32 PB0 : 1;
1020 ///
1021 /// [Bit 3] Performance Monitoring/Break Point Pins.
1022 ///
1023 UINT32 PB1 : 1;
1024 ///
1025 /// [Bit 4] Performance Monitoring/Break Point Pins.
1026 ///
1027 UINT32 PB2 : 1;
1028 ///
1029 /// [Bit 5] Performance Monitoring/Break Point Pins.
1030 ///
1031 UINT32 PB3 : 1;
1032 ///
1033 /// [Bit 6] Enable/Disable Execution Trace Messages.
1034 ///
1035 UINT32 TR : 1;
1036 UINT32 Reserved1 : 25;
1037 UINT32 Reserved2 : 32;
1038 } Bits;
1039 ///
1040 /// All bit fields as a 32-bit value
1041 ///
1042 UINT32 Uint32;
1043 ///
1044 /// All bit fields as a 64-bit value
1045 ///
1046 UINT64 Uint64;
1047 } MSR_P6_DEBUGCTLMSR_REGISTER;
1048
1049 /**
1050
1051
1052 @param ECX MSR_P6_LASTBRANCHFROMIP (0x000001DB)
1053 @param EAX Lower 32-bits of MSR value.
1054 @param EDX Upper 32-bits of MSR value.
1055
1056 <b>Example usage</b>
1057 @code
1058 UINT64 Msr;
1059
1060 Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);
1061 AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);
1062 @endcode
1063 @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM.
1064 **/
1065 #define MSR_P6_LASTBRANCHFROMIP 0x000001DB
1066
1067 /**
1068
1069
1070 @param ECX MSR_P6_LASTBRANCHTOIP (0x000001DC)
1071 @param EAX Lower 32-bits of MSR value.
1072 @param EDX Upper 32-bits of MSR value.
1073
1074 <b>Example usage</b>
1075 @code
1076 UINT64 Msr;
1077
1078 Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);
1079 AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);
1080 @endcode
1081 @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM.
1082 **/
1083 #define MSR_P6_LASTBRANCHTOIP 0x000001DC
1084
1085 /**
1086
1087
1088 @param ECX MSR_P6_LASTINTFROMIP (0x000001DD)
1089 @param EAX Lower 32-bits of MSR value.
1090 @param EDX Upper 32-bits of MSR value.
1091
1092 <b>Example usage</b>
1093 @code
1094 UINT64 Msr;
1095
1096 Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);
1097 AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);
1098 @endcode
1099 @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM.
1100 **/
1101 #define MSR_P6_LASTINTFROMIP 0x000001DD
1102
1103 /**
1104
1105
1106 @param ECX MSR_P6_LASTINTTOIP (0x000001DE)
1107 @param EAX Lower 32-bits of MSR value.
1108 @param EDX Upper 32-bits of MSR value.
1109
1110 <b>Example usage</b>
1111 @code
1112 UINT64 Msr;
1113
1114 Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);
1115 AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);
1116 @endcode
1117 @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM.
1118 **/
1119 #define MSR_P6_LASTINTTOIP 0x000001DE
1120
1121 /**
1122
1123
1124 @param ECX MSR_P6_MTRRPHYSBASEn
1125 @param EAX Lower 32-bits of MSR value.
1126 @param EDX Upper 32-bits of MSR value.
1127
1128 <b>Example usage</b>
1129 @code
1130 UINT64 Msr;
1131
1132 Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
1133 AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);
1134 @endcode
1135 @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
1136 MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
1137 MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
1138 MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
1139 MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
1140 MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
1141 MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
1142 MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
1143 @{
1144 **/
1145 #define MSR_P6_MTRRPHYSBASE0 0x00000200
1146 #define MSR_P6_MTRRPHYSBASE1 0x00000202
1147 #define MSR_P6_MTRRPHYSBASE2 0x00000204
1148 #define MSR_P6_MTRRPHYSBASE3 0x00000206
1149 #define MSR_P6_MTRRPHYSBASE4 0x00000208
1150 #define MSR_P6_MTRRPHYSBASE5 0x0000020A
1151 #define MSR_P6_MTRRPHYSBASE6 0x0000020C
1152 #define MSR_P6_MTRRPHYSBASE7 0x0000020E
1153 /// @}
1154
1155 /**
1156
1157
1158 @param ECX MSR_P6_MTRRPHYSMASKn
1159 @param EAX Lower 32-bits of MSR value.
1160 @param EDX Upper 32-bits of MSR value.
1161
1162 <b>Example usage</b>
1163 @code
1164 UINT64 Msr;
1165
1166 Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
1167 AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);
1168 @endcode
1169 @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
1170 MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
1171 MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
1172 MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
1173 MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
1174 MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
1175 MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
1176 MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
1177 @{
1178 **/
1179 #define MSR_P6_MTRRPHYSMASK0 0x00000201
1180 #define MSR_P6_MTRRPHYSMASK1 0x00000203
1181 #define MSR_P6_MTRRPHYSMASK2 0x00000205
1182 #define MSR_P6_MTRRPHYSMASK3 0x00000207
1183 #define MSR_P6_MTRRPHYSMASK4 0x00000209
1184 #define MSR_P6_MTRRPHYSMASK5 0x0000020B
1185 #define MSR_P6_MTRRPHYSMASK6 0x0000020D
1186 #define MSR_P6_MTRRPHYSMASK7 0x0000020F
1187 /// @}
1188
1189 /**
1190
1191
1192 @param ECX MSR_P6_MTRRFIX64K_00000 (0x00000250)
1193 @param EAX Lower 32-bits of MSR value.
1194 @param EDX Upper 32-bits of MSR value.
1195
1196 <b>Example usage</b>
1197 @code
1198 UINT64 Msr;
1199
1200 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);
1201 AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);
1202 @endcode
1203 @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
1204 **/
1205 #define MSR_P6_MTRRFIX64K_00000 0x00000250
1206
1207 /**
1208
1209
1210 @param ECX MSR_P6_MTRRFIX16K_80000 (0x00000258)
1211 @param EAX Lower 32-bits of MSR value.
1212 @param EDX Upper 32-bits of MSR value.
1213
1214 <b>Example usage</b>
1215 @code
1216 UINT64 Msr;
1217
1218 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);
1219 AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);
1220 @endcode
1221 @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
1222 **/
1223 #define MSR_P6_MTRRFIX16K_80000 0x00000258
1224
1225 /**
1226
1227
1228 @param ECX MSR_P6_MTRRFIX16K_A0000 (0x00000259)
1229 @param EAX Lower 32-bits of MSR value.
1230 @param EDX Upper 32-bits of MSR value.
1231
1232 <b>Example usage</b>
1233 @code
1234 UINT64 Msr;
1235
1236 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);
1237 AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);
1238 @endcode
1239 @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
1240 **/
1241 #define MSR_P6_MTRRFIX16K_A0000 0x00000259
1242
1243 /**
1244
1245
1246 @param ECX MSR_P6_MTRRFIX4K_C0000 (0x00000268)
1247 @param EAX Lower 32-bits of MSR value.
1248 @param EDX Upper 32-bits of MSR value.
1249
1250 <b>Example usage</b>
1251 @code
1252 UINT64 Msr;
1253
1254 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);
1255 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);
1256 @endcode
1257 @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
1258 **/
1259 #define MSR_P6_MTRRFIX4K_C0000 0x00000268
1260
1261 /**
1262
1263
1264 @param ECX MSR_P6_MTRRFIX4K_C8000 (0x00000269)
1265 @param EAX Lower 32-bits of MSR value.
1266 @param EDX Upper 32-bits of MSR value.
1267
1268 <b>Example usage</b>
1269 @code
1270 UINT64 Msr;
1271
1272 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);
1273 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);
1274 @endcode
1275 @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
1276 **/
1277 #define MSR_P6_MTRRFIX4K_C8000 0x00000269
1278
1279 /**
1280
1281
1282 @param ECX MSR_P6_MTRRFIX4K_D0000 (0x0000026A)
1283 @param EAX Lower 32-bits of MSR value.
1284 @param EDX Upper 32-bits of MSR value.
1285
1286 <b>Example usage</b>
1287 @code
1288 UINT64 Msr;
1289
1290 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);
1291 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);
1292 @endcode
1293 @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
1294 **/
1295 #define MSR_P6_MTRRFIX4K_D0000 0x0000026A
1296
1297 /**
1298
1299
1300 @param ECX MSR_P6_MTRRFIX4K_D8000 (0x0000026B)
1301 @param EAX Lower 32-bits of MSR value.
1302 @param EDX Upper 32-bits of MSR value.
1303
1304 <b>Example usage</b>
1305 @code
1306 UINT64 Msr;
1307
1308 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);
1309 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);
1310 @endcode
1311 @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
1312 **/
1313 #define MSR_P6_MTRRFIX4K_D8000 0x0000026B
1314
1315 /**
1316
1317
1318 @param ECX MSR_P6_MTRRFIX4K_E0000 (0x0000026C)
1319 @param EAX Lower 32-bits of MSR value.
1320 @param EDX Upper 32-bits of MSR value.
1321
1322 <b>Example usage</b>
1323 @code
1324 UINT64 Msr;
1325
1326 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);
1327 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);
1328 @endcode
1329 @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
1330 **/
1331 #define MSR_P6_MTRRFIX4K_E0000 0x0000026C
1332
1333 /**
1334
1335
1336 @param ECX MSR_P6_MTRRFIX4K_E8000 (0x0000026D)
1337 @param EAX Lower 32-bits of MSR value.
1338 @param EDX Upper 32-bits of MSR value.
1339
1340 <b>Example usage</b>
1341 @code
1342 UINT64 Msr;
1343
1344 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);
1345 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);
1346 @endcode
1347 @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
1348 **/
1349 #define MSR_P6_MTRRFIX4K_E8000 0x0000026D
1350
1351 /**
1352
1353
1354 @param ECX MSR_P6_MTRRFIX4K_F0000 (0x0000026E)
1355 @param EAX Lower 32-bits of MSR value.
1356 @param EDX Upper 32-bits of MSR value.
1357
1358 <b>Example usage</b>
1359 @code
1360 UINT64 Msr;
1361
1362 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);
1363 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);
1364 @endcode
1365 @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
1366 **/
1367 #define MSR_P6_MTRRFIX4K_F0000 0x0000026E
1368
1369 /**
1370
1371
1372 @param ECX MSR_P6_MTRRFIX4K_F8000 (0x0000026F)
1373 @param EAX Lower 32-bits of MSR value.
1374 @param EDX Upper 32-bits of MSR value.
1375
1376 <b>Example usage</b>
1377 @code
1378 UINT64 Msr;
1379
1380 Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);
1381 AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);
1382 @endcode
1383 @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
1384 **/
1385 #define MSR_P6_MTRRFIX4K_F8000 0x0000026F
1386
1387 /**
1388
1389
1390 @param ECX MSR_P6_MTRRDEFTYPE (0x000002FF)
1391 @param EAX Lower 32-bits of MSR value.
1392 Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
1393 @param EDX Upper 32-bits of MSR value.
1394 Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
1395
1396 <b>Example usage</b>
1397 @code
1398 MSR_P6_MTRRDEFTYPE_REGISTER Msr;
1399
1400 Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);
1401 AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);
1402 @endcode
1403 @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM.
1404 **/
1405 #define MSR_P6_MTRRDEFTYPE 0x000002FF
1406
1407 /**
1408 MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE
1409 **/
1410 typedef union {
1411 ///
1412 /// Individual bit fields
1413 ///
1414 struct {
1415 ///
1416 /// [Bits 2:0] Default memory type.
1417 ///
1418 UINT32 Type : 3;
1419 UINT32 Reserved1 : 7;
1420 ///
1421 /// [Bit 10] Fixed MTRR enable.
1422 ///
1423 UINT32 FE : 1;
1424 ///
1425 /// [Bit 11] MTRR Enable.
1426 ///
1427 UINT32 E : 1;
1428 UINT32 Reserved2 : 20;
1429 UINT32 Reserved3 : 32;
1430 } Bits;
1431 ///
1432 /// All bit fields as a 32-bit value
1433 ///
1434 UINT32 Uint32;
1435 ///
1436 /// All bit fields as a 64-bit value
1437 ///
1438 UINT64 Uint64;
1439 } MSR_P6_MTRRDEFTYPE_REGISTER;
1440
1441 /**
1442
1443
1444 @param ECX MSR_P6_MC0_CTL (0x00000400)
1445 @param EAX Lower 32-bits of MSR value.
1446 @param EDX Upper 32-bits of MSR value.
1447
1448 <b>Example usage</b>
1449 @code
1450 UINT64 Msr;
1451
1452 Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
1453 AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);
1454 @endcode
1455 @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM.
1456 MSR_P6_MC1_CTL is defined as MC1_CTL in SDM.
1457 MSR_P6_MC2_CTL is defined as MC2_CTL in SDM.
1458 MSR_P6_MC3_CTL is defined as MC3_CTL in SDM.
1459 MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.
1460 @{
1461 **/
1462 #define MSR_P6_MC0_CTL 0x00000400
1463 #define MSR_P6_MC1_CTL 0x00000404
1464 #define MSR_P6_MC2_CTL 0x00000408
1465 #define MSR_P6_MC3_CTL 0x00000410
1466 #define MSR_P6_MC4_CTL 0x0000040C
1467 /// @}
1468
1469 /**
1470
1471 Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS,
1472 except bits 0, 4, 57, and 61 are hardcoded to 1.
1473
1474 @param ECX MSR_P6_MCn_STATUS
1475 @param EAX Lower 32-bits of MSR value.
1476 Described by the type MSR_P6_MC_STATUS_REGISTER.
1477 @param EDX Upper 32-bits of MSR value.
1478 Described by the type MSR_P6_MC_STATUS_REGISTER.
1479
1480 <b>Example usage</b>
1481 @code
1482 MSR_P6_MC_STATUS_REGISTER Msr;
1483
1484 Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
1485 AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);
1486 @endcode
1487 @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM.
1488 MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM.
1489 MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM.
1490 MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM.
1491 MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.
1492 @{
1493 **/
1494 #define MSR_P6_MC0_STATUS 0x00000401
1495 #define MSR_P6_MC1_STATUS 0x00000405
1496 #define MSR_P6_MC2_STATUS 0x00000409
1497 #define MSR_P6_MC3_STATUS 0x00000411
1498 #define MSR_P6_MC4_STATUS 0x0000040D
1499 /// @}
1500
1501 /**
1502 MSR information returned for MSR index #MSR_P6_MC0_STATUS to
1503 #MSR_P6_MC4_STATUS
1504 **/
1505 typedef union {
1506 ///
1507 /// Individual bit fields
1508 ///
1509 struct {
1510 ///
1511 /// [Bits 15:0] MC_STATUS_MCACOD.
1512 ///
1513 UINT32 MC_STATUS_MCACOD : 16;
1514 ///
1515 /// [Bits 31:16] MC_STATUS_MSCOD.
1516 ///
1517 UINT32 MC_STATUS_MSCOD : 16;
1518 UINT32 Reserved : 25;
1519 ///
1520 /// [Bit 57] MC_STATUS_DAM.
1521 ///
1522 UINT32 MC_STATUS_DAM : 1;
1523 ///
1524 /// [Bit 58] MC_STATUS_ADDRV.
1525 ///
1526 UINT32 MC_STATUS_ADDRV : 1;
1527 ///
1528 /// [Bit 59] MC_STATUS_MISCV.
1529 ///
1530 UINT32 MC_STATUS_MISCV : 1;
1531 ///
1532 /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is
1533 /// hardcoded to 1.).
1534 ///
1535 UINT32 MC_STATUS_EN : 1;
1536 ///
1537 /// [Bit 61] MC_STATUS_UC.
1538 ///
1539 UINT32 MC_STATUS_UC : 1;
1540 ///
1541 /// [Bit 62] MC_STATUS_O.
1542 ///
1543 UINT32 MC_STATUS_O : 1;
1544 ///
1545 /// [Bit 63] MC_STATUS_V.
1546 ///
1547 UINT32 MC_STATUS_V : 1;
1548 } Bits;
1549 ///
1550 /// All bit fields as a 64-bit value
1551 ///
1552 UINT64 Uint64;
1553 } MSR_P6_MC_STATUS_REGISTER;
1554
1555 /**
1556
1557 MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.
1558
1559 @param ECX MSR_P6_MC0_ADDR (0x00000402)
1560 @param EAX Lower 32-bits of MSR value.
1561 @param EDX Upper 32-bits of MSR value.
1562
1563 <b>Example usage</b>
1564 @code
1565 UINT64 Msr;
1566
1567 Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
1568 AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);
1569 @endcode
1570 @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM.
1571 MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM.
1572 MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM.
1573 MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM.
1574 MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.
1575 @{
1576 **/
1577 #define MSR_P6_MC0_ADDR 0x00000402
1578 #define MSR_P6_MC1_ADDR 0x00000406
1579 #define MSR_P6_MC2_ADDR 0x0000040A
1580 #define MSR_P6_MC3_ADDR 0x00000412
1581 #define MSR_P6_MC4_ADDR 0x0000040E
1582 /// @}
1583
1584 /**
1585 Defined in MCA architecture but not implemented in the P6 family processors.
1586
1587 @param ECX MSR_P6_MC0_MISC (0x00000403)
1588 @param EAX Lower 32-bits of MSR value.
1589 @param EDX Upper 32-bits of MSR value.
1590
1591 <b>Example usage</b>
1592 @code
1593 UINT64 Msr;
1594
1595 Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
1596 AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);
1597 @endcode
1598 @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM.
1599 MSR_P6_MC1_MISC is defined as MC1_MISC in SDM.
1600 MSR_P6_MC2_MISC is defined as MC2_MISC in SDM.
1601 MSR_P6_MC3_MISC is defined as MC3_MISC in SDM.
1602 MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.
1603 @{
1604 **/
1605 #define MSR_P6_MC0_MISC 0x00000403
1606 #define MSR_P6_MC1_MISC 0x00000407
1607 #define MSR_P6_MC2_MISC 0x0000040B
1608 #define MSR_P6_MC3_MISC 0x00000413
1609 #define MSR_P6_MC4_MISC 0x0000040F
1610 /// @}
1611
1612 #endif
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