2 MSR Definitions for Pentium(R) 4 Processors.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __PENTIUM_4_MSR_H__
19 #define __PENTIUM_4_MSR_H__
21 #include <Register/Intel/ArchitecturalMsr.h>
24 Is Pentium(R) 4 Processors?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x0F \
37 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range
40 @param ECX MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006)
41 @param EAX Lower 32-bits of MSR value.
42 @param EDX Upper 32-bits of MSR value.
48 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);
49 AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);
51 @note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM.
53 #define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006
57 0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)
58 Enables and disables processor features; (R) indicates current processor
61 @param ECX MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A)
62 @param EAX Lower 32-bits of MSR value.
63 Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
64 @param EDX Upper 32-bits of MSR value.
65 Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
69 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Msr;
71 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);
72 AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);
74 @note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM.
76 #define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A
79 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON
83 /// Individual bit fields
87 /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state
88 /// output is enabled (1) or disabled (0) as set by the strapping of SMI#.
89 /// The value in this bit is written on the deassertion of RESET#; the bit
90 /// is set to 1 when the address bus signal is asserted.
92 UINT32 OutputTriStateEnabled
:1;
94 /// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST
95 /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The
96 /// value in this bit is written on the deassertion of RESET#; the bit is
97 /// set to 1 when the address bus signal is asserted.
101 /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue
102 /// depth for the system bus is 1 (1) or up to 12 (0) as set by the
103 /// strapping of A7#. The value in this bit is written on the deassertion
104 /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
106 UINT32 InOrderQueueDepth
:1;
108 /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#
109 /// observation is enabled (0) or disabled (1) as determined by the
110 /// strapping of A9#. The value in this bit is written on the deassertion
111 /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
113 UINT32 MCERR_ObservationDisabled
:1;
115 /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#
116 /// observation is enabled (0) or disabled (1) as determined by the
117 /// strapping of A10#. The value in this bit is written on the deassertion
118 /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
120 UINT32 BINIT_ObservationEnabled
:1;
122 /// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID
123 /// value as set by the strapping of A12# and A11#. The logical cluster ID
124 /// value is written into the field on the deassertion of RESET#; the
125 /// field is set to 1 when the address bus signal is asserted.
127 UINT32 APICClusterID
:2;
129 /// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled
130 /// (0) or disabled (1) as set by the strapping of A15#. The value in this
131 /// bit is written on the deassertion of RESET#; the bit is set to 1 when
132 /// the address bus signal is asserted.
134 UINT32 BusParkDisable
:1;
137 /// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set
138 /// by the strapping of BR[3:0]. The logical ID value is written into the
139 /// field on the deassertion of RESET#; the field is set to 1 when the
140 /// address bus signal is asserted.
147 /// All bit fields as a 32-bit value
151 /// All bit fields as a 64-bit value
154 } MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
;
158 0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W)
159 Enables and disables processor features.
161 @param ECX MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B)
162 @param EAX Lower 32-bits of MSR value.
163 Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.
164 @param EDX Upper 32-bits of MSR value.
165 Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.
169 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Msr;
171 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);
172 AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);
174 @note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM.
176 #define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B
179 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON
183 /// Individual bit fields
187 /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W) Controls the
188 /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear
189 /// to disabled (0, default).
193 /// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data
194 /// bus parity checking; clear to enable parity checking.
196 UINT32 DataErrorCheckingDisable
:1;
198 /// [Bit 2] Response Error Checking Disable (R/W) Set to disable
199 /// (default); clear to enable.
201 UINT32 ResponseErrorCheckingDisable
:1;
203 /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable
204 /// (default); clear to enable.
206 UINT32 AddressRequestErrorCheckingDisable
:1;
208 /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving
209 /// for initiator bus requests (default); clear to enable.
211 UINT32 InitiatorMCERR_Disable
:1;
213 /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving
214 /// for initiator internal errors (default); clear to enable.
216 UINT32 InternalMCERR_Disable
:1;
218 /// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver
219 /// (default); clear to enable driver.
221 UINT32 BINIT_DriverDisable
:1;
226 /// All bit fields as a 32-bit value
230 /// All bit fields as a 64-bit value
233 } MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
;
237 2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of
238 this MSR varies according to the MODEL value in the CPUID version
239 information. The following bit field layout applies to Pentium 4 and Xeon
240 Processors with MODEL encoding equal or greater than 2. (R) The field
241 Indicates the current processor frequency configuration.
243 @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C)
244 @param EAX Lower 32-bits of MSR value.
245 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.
246 @param EDX Upper 32-bits of MSR value.
247 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.
251 MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Msr;
253 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);
255 @note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM.
257 #define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C
260 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID
264 /// Individual bit fields
269 /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable
270 /// bus speed: *EncodingScalable Bus Speed*
272 /// 000B 100 MHz (Model 2).
273 /// 000B 266 MHz (Model 3 or 4)
277 /// 100B 333 MHz (Model 6)
279 /// 133.33 MHz should be utilized if performing calculation with System
280 /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
281 /// performing calculation with System Bus Speed when encoding is 011B.
282 /// 266.67 MHz should be utilized if performing calculation with System
283 /// Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33
284 /// MHz should be utilized if performing calculation with System Bus
285 /// Speed when encoding is 100B and model encoding = 6. All other values
288 UINT32 ScalableBusSpeed
:3;
291 /// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R)
292 /// The processor core clock frequency to system bus frequency ratio
293 /// observed at the de-assertion of the reset pin.
299 /// All bit fields as a 32-bit value
303 /// All bit fields as a 64-bit value
306 } MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER
;
310 0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of
311 this MSR varies according to the MODEL value of the CPUID version
312 information. This bit field layout applies to Pentium 4 and Xeon Processors
313 with MODEL encoding less than 2. Indicates current processor frequency
316 @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C)
317 @param EAX Lower 32-bits of MSR value.
318 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.
319 @param EDX Upper 32-bits of MSR value.
320 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.
324 MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Msr;
326 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);
328 @note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM.
330 #define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C
333 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1
337 /// Individual bit fields
342 /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable
343 /// bus speed: *Encoding* *Scalable Bus Speed*
345 /// 000B 100 MHz All others values reserved.
347 UINT32 ScalableBusSpeed
:3;
352 /// All bit fields as a 32-bit value
356 /// All bit fields as a 64-bit value
359 } MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER
;
363 0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section
364 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
365 state at time of machine check error. When in non-64-bit modes at the time
366 of the error, bits 63-32 do not contain valid data.
368 @param ECX MSR_PENTIUM_4_MCG_RAX (0x00000180)
369 @param EAX Lower 32-bits of MSR value.
370 @param EDX Upper 32-bits of MSR value.
376 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);
377 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);
379 @note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM.
381 #define MSR_PENTIUM_4_MCG_RAX 0x00000180
385 0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section
386 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
387 state at time of machine check error. When in non-64-bit modes at the time
388 of the error, bits 63-32 do not contain valid data.
390 @param ECX MSR_PENTIUM_4_MCG_RBX (0x00000181)
391 @param EAX Lower 32-bits of MSR value.
392 @param EDX Upper 32-bits of MSR value.
398 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);
399 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);
401 @note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM.
403 #define MSR_PENTIUM_4_MCG_RBX 0x00000181
407 0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section
408 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
409 state at time of machine check error. When in non-64-bit modes at the time
410 of the error, bits 63-32 do not contain valid data.
412 @param ECX MSR_PENTIUM_4_MCG_RCX (0x00000182)
413 @param EAX Lower 32-bits of MSR value.
414 @param EDX Upper 32-bits of MSR value.
420 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);
421 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);
423 @note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM.
425 #define MSR_PENTIUM_4_MCG_RCX 0x00000182
429 0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section
430 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
431 state at time of machine check error. When in non-64-bit modes at the time
432 of the error, bits 63-32 do not contain valid data.
434 @param ECX MSR_PENTIUM_4_MCG_RDX (0x00000183)
435 @param EAX Lower 32-bits of MSR value.
436 @param EDX Upper 32-bits of MSR value.
442 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);
443 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);
445 @note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM.
447 #define MSR_PENTIUM_4_MCG_RDX 0x00000183
451 0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section
452 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
453 state at time of machine check error. When in non-64-bit modes at the time
454 of the error, bits 63-32 do not contain valid data.
456 @param ECX MSR_PENTIUM_4_MCG_RSI (0x00000184)
457 @param EAX Lower 32-bits of MSR value.
458 @param EDX Upper 32-bits of MSR value.
464 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);
465 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);
467 @note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM.
469 #define MSR_PENTIUM_4_MCG_RSI 0x00000184
473 0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section
474 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
475 state at time of machine check error. When in non-64-bit modes at the time
476 of the error, bits 63-32 do not contain valid data.
478 @param ECX MSR_PENTIUM_4_MCG_RDI (0x00000185)
479 @param EAX Lower 32-bits of MSR value.
480 @param EDX Upper 32-bits of MSR value.
486 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);
487 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);
489 @note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM.
491 #define MSR_PENTIUM_4_MCG_RDI 0x00000185
495 0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section
496 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
497 state at time of machine check error. When in non-64-bit modes at the time
498 of the error, bits 63-32 do not contain valid data.
500 @param ECX MSR_PENTIUM_4_MCG_RBP (0x00000186)
501 @param EAX Lower 32-bits of MSR value.
502 @param EDX Upper 32-bits of MSR value.
508 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);
509 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);
511 @note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM.
513 #define MSR_PENTIUM_4_MCG_RBP 0x00000186
517 0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section
518 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
519 state at time of machine check error. When in non-64-bit modes at the time
520 of the error, bits 63-32 do not contain valid data.
522 @param ECX MSR_PENTIUM_4_MCG_RSP (0x00000187)
523 @param EAX Lower 32-bits of MSR value.
524 @param EDX Upper 32-bits of MSR value.
530 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);
531 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);
533 @note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM.
535 #define MSR_PENTIUM_4_MCG_RSP 0x00000187
539 0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section
540 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
541 state at time of machine check error. When in non-64-bit modes at the time
542 of the error, bits 63-32 do not contain valid data.
544 @param ECX MSR_PENTIUM_4_MCG_RFLAGS (0x00000188)
545 @param EAX Lower 32-bits of MSR value.
546 @param EDX Upper 32-bits of MSR value.
552 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);
553 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);
555 @note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM.
557 #define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188
561 0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section
562 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
563 state at time of machine check error. When in non-64-bit modes at the time
564 of the error, bits 63-32 do not contain valid data.
566 @param ECX MSR_PENTIUM_4_MCG_RIP (0x00000189)
567 @param EAX Lower 32-bits of MSR value.
568 @param EDX Upper 32-bits of MSR value.
574 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);
575 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);
577 @note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM.
579 #define MSR_PENTIUM_4_MCG_RIP 0x00000189
583 0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6,
584 "IA32_MCG Extended Machine Check State MSRs.".
586 @param ECX MSR_PENTIUM_4_MCG_MISC (0x0000018A)
587 @param EAX Lower 32-bits of MSR value.
588 Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.
589 @param EDX Upper 32-bits of MSR value.
590 Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.
594 MSR_PENTIUM_4_MCG_MISC_REGISTER Msr;
596 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);
597 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);
599 @note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM.
601 #define MSR_PENTIUM_4_MCG_MISC 0x0000018A
604 MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC
608 /// Individual bit fields
612 /// [Bit 0] DS When set, the bit indicates that a page assist or page
613 /// fault occurred during DS normal operation. The processors response is
614 /// to shut down. The bit is used as an aid for debugging DS handling
615 /// code. It is the responsibility of the user (BIOS or operating system)
616 /// to clear this bit for normal operation.
623 /// All bit fields as a 32-bit value
627 /// All bit fields as a 64-bit value
630 } MSR_PENTIUM_4_MCG_MISC_REGISTER
;
634 0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG
635 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
636 state-save MSRs) exist only in Intel 64 processors. These registers contain
637 valid information only when the processor is operating in 64-bit mode at the
640 @param ECX MSR_PENTIUM_4_MCG_R8 (0x00000190)
641 @param EAX Lower 32-bits of MSR value.
642 @param EDX Upper 32-bits of MSR value.
648 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);
649 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);
651 @note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM.
653 #define MSR_PENTIUM_4_MCG_R8 0x00000190
657 0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6,
658 "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the
659 associated state-save MSRs) exist only in Intel 64 processors. These
660 registers contain valid information only when the processor is operating in
661 64-bit mode at the time of the error.
663 @param ECX MSR_PENTIUM_4_MCG_R9 (0x00000191)
664 @param EAX Lower 32-bits of MSR value.
665 @param EDX Upper 32-bits of MSR value.
671 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);
672 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);
674 @note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM.
676 #define MSR_PENTIUM_4_MCG_R9 0x00000191
680 0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG
681 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
682 state-save MSRs) exist only in Intel 64 processors. These registers contain
683 valid information only when the processor is operating in 64-bit mode at the
686 @param ECX MSR_PENTIUM_4_MCG_R10 (0x00000192)
687 @param EAX Lower 32-bits of MSR value.
688 @param EDX Upper 32-bits of MSR value.
694 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);
695 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);
697 @note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM.
699 #define MSR_PENTIUM_4_MCG_R10 0x00000192
703 0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG
704 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
705 state-save MSRs) exist only in Intel 64 processors. These registers contain
706 valid information only when the processor is operating in 64-bit mode at the
709 @param ECX MSR_PENTIUM_4_MCG_R11 (0x00000193)
710 @param EAX Lower 32-bits of MSR value.
711 @param EDX Upper 32-bits of MSR value.
717 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);
718 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);
720 @note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM.
722 #define MSR_PENTIUM_4_MCG_R11 0x00000193
726 0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG
727 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
728 state-save MSRs) exist only in Intel 64 processors. These registers contain
729 valid information only when the processor is operating in 64-bit mode at the
732 @param ECX MSR_PENTIUM_4_MCG_R12 (0x00000194)
733 @param EAX Lower 32-bits of MSR value.
734 @param EDX Upper 32-bits of MSR value.
740 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);
741 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);
743 @note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM.
745 #define MSR_PENTIUM_4_MCG_R12 0x00000194
749 0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG
750 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
751 state-save MSRs) exist only in Intel 64 processors. These registers contain
752 valid information only when the processor is operating in 64-bit mode at the
755 @param ECX MSR_PENTIUM_4_MCG_R13 (0x00000195)
756 @param EAX Lower 32-bits of MSR value.
757 @param EDX Upper 32-bits of MSR value.
763 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);
764 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);
766 @note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM.
768 #define MSR_PENTIUM_4_MCG_R13 0x00000195
772 0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG
773 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
774 state-save MSRs) exist only in Intel 64 processors. These registers contain
775 valid information only when the processor is operating in 64-bit mode at the
778 @param ECX MSR_PENTIUM_4_MCG_R14 (0x00000196)
779 @param EAX Lower 32-bits of MSR value.
780 @param EDX Upper 32-bits of MSR value.
786 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);
787 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);
789 @note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM.
791 #define MSR_PENTIUM_4_MCG_R14 0x00000196
795 0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG
796 Extended Machine Check State MSRs.". Registers R8-15 (and the associated
797 state-save MSRs) exist only in Intel 64 processors. These registers contain
798 valid information only when the processor is operating in 64-bit mode at the
801 @param ECX MSR_PENTIUM_4_MCG_R15 (0x00000197)
802 @param EAX Lower 32-bits of MSR value.
803 @param EDX Upper 32-bits of MSR value.
809 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);
810 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);
812 @note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM.
814 #define MSR_PENTIUM_4_MCG_R15 0x00000197
818 Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors:
819 When read, specifies the value of the target TM2 transition last written.
820 When set, it sets the next target value for TM2 transition. 4, 6. Shared.
821 For Family F, Model 4 and Model 6 processors: When read, specifies the value
822 of the target TM2 transition last written. Writes may cause #GP exceptions.
824 @param ECX MSR_PENTIUM_4_THERM2_CTL (0x0000019D)
825 @param EAX Lower 32-bits of MSR value.
826 @param EDX Upper 32-bits of MSR value.
832 Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);
833 AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);
835 @note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
837 #define MSR_PENTIUM_4_THERM2_CTL 0x0000019D
841 0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).
843 @param ECX MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0)
844 @param EAX Lower 32-bits of MSR value.
845 Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.
846 @param EDX Upper 32-bits of MSR value.
847 Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.
851 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Msr;
853 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);
854 AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);
856 @note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
858 #define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0
861 MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE
865 /// Individual bit fields
869 /// [Bit 0] Fast-Strings Enable. See Table 2-2.
871 UINT32 FastStrings
:1;
874 /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable.
878 /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal
879 /// Monitor," and see Table 2-2.
883 /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception
884 /// to be issued instead of a split-lock cycle. Operating systems that set
885 /// this bit must align system structures to avoid split-lock scenarios.
886 /// When the bit is clear (default), normal split-locks are issued to the
888 /// This debug feature is specific to the Pentium 4 processor.
890 UINT32 SplitLockDisable
:1;
893 /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level
894 /// cache is disabled; when clear (default) the third-level cache is
895 /// enabled. This flag is reserved for processors that do not have a
896 /// third-level cache. Note that the bit controls only the third-level
897 /// cache; and only if overall caching is enabled through the CD flag of
898 /// control register CR0, the page-level cache controls, and/or the MTRRs.
899 /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.".
901 UINT32 ThirdLevelCacheDisable
:1;
903 /// [Bit 7] Performance Monitoring Available (R) See Table 2-2.
905 UINT32 PerformanceMonitoring
:1;
907 /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is
908 /// suppressed during a Split Lock access. When clear (default), LOCK is
911 UINT32 SuppressLockEnable
:1;
913 /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue.
914 /// When clear (default), enables the prefetch queue.
916 UINT32 PrefetchQueueDisable
:1;
918 /// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt
919 /// reporting through the FERR# pin is enabled; when clear, this interrupt
920 /// reporting function is disabled.
921 /// When this flag is set and the processor is in the stop-clock state
922 /// (STPCLK# is asserted), asserting the FERR# pin signals to the
923 /// processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,
924 /// SMI#, or RESET#) is pending and that the processor should return to
925 /// normal operation to handle the interrupt. This flag does not affect
926 /// the normal operation of the FERR# pin (to indicate an unmasked
927 /// floatingpoint error) when the STPCLK# pin is not asserted.
931 /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See
932 /// Table 2-2. When set, the processor does not support branch trace
933 /// storage (BTS); when clear, BTS is supported.
937 /// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable
938 /// (R) See Table 2-2. When set, the processor does not support processor
939 /// event-based sampling (PEBS); when clear, PEBS is supported.
943 /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal
944 /// sensor indicates that the die temperature is at the predetermined
945 /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce
946 /// the bus to core ratio and voltage according to the value last written
947 /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the
948 /// processor does not change the VID signals or the bus to core ratio
949 /// when the processor enters a thermal managed state. If the TM2 feature
950 /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then
951 /// this feature is not supported and BIOS must not alter the contents of
952 /// this bit location. The processor is operating out of spec if both this
953 /// bit and the TM1 bit are set to disabled states.
958 /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.
962 /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1,
963 /// the processor fetches the cache line of the 128-byte sector containing
964 /// currently required data. When set to 0, the processor fetches both
965 /// cache lines in the sector.
966 /// Single processor platforms should not set this bit. Server platforms
967 /// should set or clear this bit based on platform performance observed
968 /// in validation and testing. BIOS may contain a setup option that
969 /// controls the setting of this bit.
971 UINT32 AdjacentCacheLinePrefetchDisable
:1;
974 /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this
975 /// can cause unexpected behavior to software that depends on the
976 /// availability of CPUID leaves greater than 3.
978 UINT32 LimitCpuidMaxval
:1;
980 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
982 UINT32 xTPR_Message_Disable
:1;
984 /// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache
985 /// is placed in shared mode; when clear (default), the cache is placed in
986 /// adaptive mode. This bit is only enabled for IA-32 processors that
987 /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data
988 /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are
989 /// identical, data in L1 is shared across logical processors. Otherwise,
990 /// L1 is not shared and cache use is competitive. If the Context ID
991 /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1,
992 /// the ability to switch modes is not supported. BIOS must not alter the
993 /// contents of IA32_MISC_ENABLE[24].
995 UINT32 L1DataCacheContextMode
:1;
999 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
1002 UINT32 Reserved7
:29;
1005 /// All bit fields as a 64-bit value
1008 } MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
;
1012 3, 4, 6. Shared. Platform Feature Requirements (R).
1014 @param ECX MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1)
1015 @param EAX Lower 32-bits of MSR value.
1016 Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.
1017 @param EDX Upper 32-bits of MSR value.
1018 Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.
1020 <b>Example usage</b>
1022 MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Msr;
1024 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);
1026 @note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM.
1028 #define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1
1031 MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV
1035 /// Individual bit fields
1038 UINT32 Reserved1
:18;
1040 /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor
1041 /// has specific platform requirements. The details of the platform
1042 /// requirements are listed in the respective data sheets of the processor.
1045 UINT32 Reserved2
:13;
1046 UINT32 Reserved3
:32;
1049 /// All bit fields as a 32-bit value
1053 /// All bit fields as a 64-bit value
1056 } MSR_PENTIUM_4_PLATFORM_BRV_REGISTER
;
1060 0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains
1061 a pointer to the last branch instruction that the processor executed prior
1062 to the last exception that was generated or the last interrupt that was
1063 handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear
1064 IP Linear address of the last branch instruction (If IA-32e mode is active).
1065 From Linear IP Linear address of the last branch instruction. Reserved.
1067 @param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)
1068 @param EAX Lower 32-bits of MSR value.
1069 @param EDX Upper 32-bits of MSR value.
1071 <b>Example usage</b>
1075 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);
1077 @note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
1079 #define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7
1083 0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area
1084 contains a pointer to the target of the last branch instruction that the
1085 processor executed prior to the last exception that was generated or the
1086 last interrupt that was handled. See Section 17.13.3, "Last Exception
1087 Records.". Unique. From Linear IP Linear address of the target of the last
1088 branch instruction (If IA-32e mode is active). From Linear IP Linear address
1089 of the target of the last branch instruction. Reserved.
1091 @param ECX MSR_PENTIUM_4_LER_TO_LIP (0x000001D8)
1092 @param EAX Lower 32-bits of MSR value.
1093 @param EDX Upper 32-bits of MSR value.
1095 <b>Example usage</b>
1099 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);
1101 @note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
1103 #define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8
1107 0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug
1108 features are used. Bit definitions are discussed in the referenced section.
1109 See Section 17.13.1, "MSR_DEBUGCTLA MSR.".
1111 @param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)
1112 @param EAX Lower 32-bits of MSR value.
1113 @param EDX Upper 32-bits of MSR value.
1115 <b>Example usage</b>
1119 Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);
1120 AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);
1122 @note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM.
1124 #define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9
1128 0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an
1129 index (0-3 or 0-15) that points to the top of the last branch record stack
1130 (that is, that points the index of the MSR containing the most recent branch
1131 record). See Section 17.13.2, "LBR Stack for Processors Based on Intel
1132 NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.
1134 @param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)
1135 @param EAX Lower 32-bits of MSR value.
1136 @param EDX Upper 32-bits of MSR value.
1138 <b>Example usage</b>
1142 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);
1143 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);
1145 @note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
1147 #define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA
1151 0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record
1152 registers on the last branch record stack. It contains pointers to the
1153 source and destination instruction for one of the last four branches,
1154 exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through
1155 MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models
1156 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See
1157 Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording
1158 for Processors based on Skylake Microarchitecture.".
1160 @param ECX MSR_PENTIUM_4_LASTBRANCH_n
1161 @param EAX Lower 32-bits of MSR value.
1162 @param EDX Upper 32-bits of MSR value.
1164 <b>Example usage</b>
1168 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);
1169 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);
1171 @note MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
1172 MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
1173 MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
1174 MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
1177 #define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB
1178 #define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC
1179 #define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD
1180 #define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE
1185 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
1187 @param ECX MSR_PENTIUM_4_BPU_COUNTERn
1188 @param EAX Lower 32-bits of MSR value.
1189 @param EDX Upper 32-bits of MSR value.
1191 <b>Example usage</b>
1195 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);
1196 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);
1198 @note MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM.
1199 MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM.
1200 MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM.
1201 MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.
1204 #define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300
1205 #define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301
1206 #define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302
1207 #define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303
1212 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
1214 @param ECX MSR_PENTIUM_4_MS_COUNTERn
1215 @param EAX Lower 32-bits of MSR value.
1216 @param EDX Upper 32-bits of MSR value.
1218 <b>Example usage</b>
1222 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);
1223 AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);
1225 @note MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM.
1226 MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM.
1227 MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM.
1228 MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.
1231 #define MSR_PENTIUM_4_MS_COUNTER0 0x00000304
1232 #define MSR_PENTIUM_4_MS_COUNTER1 0x00000305
1233 #define MSR_PENTIUM_4_MS_COUNTER2 0x00000306
1234 #define MSR_PENTIUM_4_MS_COUNTER3 0x00000307
1239 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
1241 @param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
1242 @param EAX Lower 32-bits of MSR value.
1243 @param EDX Upper 32-bits of MSR value.
1245 <b>Example usage</b>
1249 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);
1250 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);
1252 @note MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM.
1253 MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM.
1254 MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM.
1255 MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.
1258 #define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308
1259 #define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309
1260 #define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A
1261 #define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B
1266 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
1268 @param ECX MSR_PENTIUM_4_IQ_COUNTERn
1269 @param EAX Lower 32-bits of MSR value.
1270 @param EDX Upper 32-bits of MSR value.
1272 <b>Example usage</b>
1276 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);
1277 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);
1279 @note MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM.
1280 MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM.
1281 MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM.
1282 MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM.
1283 MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM.
1284 MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.
1287 #define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C
1288 #define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D
1289 #define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E
1290 #define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F
1291 #define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310
1292 #define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311
1297 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
1299 @param ECX MSR_PENTIUM_4_BPU_CCCRn
1300 @param EAX Lower 32-bits of MSR value.
1301 @param EDX Upper 32-bits of MSR value.
1303 <b>Example usage</b>
1307 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);
1308 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);
1310 @note MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM.
1311 MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM.
1312 MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM.
1313 MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.
1316 #define MSR_PENTIUM_4_BPU_CCCR0 0x00000360
1317 #define MSR_PENTIUM_4_BPU_CCCR1 0x00000361
1318 #define MSR_PENTIUM_4_BPU_CCCR2 0x00000362
1319 #define MSR_PENTIUM_4_BPU_CCCR3 0x00000363
1324 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
1326 @param ECX MSR_PENTIUM_4_MS_CCCRn
1327 @param EAX Lower 32-bits of MSR value.
1328 @param EDX Upper 32-bits of MSR value.
1330 <b>Example usage</b>
1334 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);
1335 AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);
1337 @note MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM.
1338 MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM.
1339 MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM.
1340 MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.
1343 #define MSR_PENTIUM_4_MS_CCCR0 0x00000364
1344 #define MSR_PENTIUM_4_MS_CCCR1 0x00000365
1345 #define MSR_PENTIUM_4_MS_CCCR2 0x00000366
1346 #define MSR_PENTIUM_4_MS_CCCR3 0x00000367
1351 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
1353 @param ECX MSR_PENTIUM_4_FLAME_CCCRn
1354 @param EAX Lower 32-bits of MSR value.
1355 @param EDX Upper 32-bits of MSR value.
1357 <b>Example usage</b>
1361 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);
1362 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);
1364 @note MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM.
1365 MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM.
1366 MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM.
1367 MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.
1370 #define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368
1371 #define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369
1372 #define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A
1373 #define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B
1378 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
1380 @param ECX MSR_PENTIUM_4_IQ_CCCRn
1381 @param EAX Lower 32-bits of MSR value.
1382 @param EDX Upper 32-bits of MSR value.
1384 <b>Example usage</b>
1388 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);
1389 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);
1391 @note MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM.
1392 MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM.
1393 MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM.
1394 MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM.
1395 MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM.
1396 MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.
1399 #define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C
1400 #define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D
1401 #define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E
1402 #define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F
1403 #define MSR_PENTIUM_4_IQ_CCCR4 0x00000370
1404 #define MSR_PENTIUM_4_IQ_CCCR5 0x00000371
1409 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1411 @param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)
1412 @param EAX Lower 32-bits of MSR value.
1413 @param EDX Upper 32-bits of MSR value.
1415 <b>Example usage</b>
1419 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);
1420 AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);
1422 @note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM.
1424 #define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0
1428 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1430 @param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)
1431 @param EAX Lower 32-bits of MSR value.
1432 @param EDX Upper 32-bits of MSR value.
1434 <b>Example usage</b>
1438 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);
1439 AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);
1441 @note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM.
1443 #define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1
1447 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1449 @param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)
1450 @param EAX Lower 32-bits of MSR value.
1451 @param EDX Upper 32-bits of MSR value.
1453 <b>Example usage</b>
1457 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);
1458 AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);
1460 @note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM.
1462 #define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2
1466 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1468 @param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)
1469 @param EAX Lower 32-bits of MSR value.
1470 @param EDX Upper 32-bits of MSR value.
1472 <b>Example usage</b>
1476 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);
1477 AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);
1479 @note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM.
1481 #define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3
1485 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1487 @param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)
1488 @param EAX Lower 32-bits of MSR value.
1489 @param EDX Upper 32-bits of MSR value.
1491 <b>Example usage</b>
1495 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);
1496 AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);
1498 @note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM.
1500 #define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4
1504 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1506 @param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)
1507 @param EAX Lower 32-bits of MSR value.
1508 @param EDX Upper 32-bits of MSR value.
1510 <b>Example usage</b>
1514 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);
1515 AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);
1517 @note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM.
1519 #define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5
1523 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1525 @param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)
1526 @param EAX Lower 32-bits of MSR value.
1527 @param EDX Upper 32-bits of MSR value.
1529 <b>Example usage</b>
1533 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);
1534 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);
1536 @note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM.
1538 #define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6
1542 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1544 @param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)
1545 @param EAX Lower 32-bits of MSR value.
1546 @param EDX Upper 32-bits of MSR value.
1548 <b>Example usage</b>
1552 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);
1553 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);
1555 @note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM.
1557 #define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7
1561 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1563 @param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)
1564 @param EAX Lower 32-bits of MSR value.
1565 @param EDX Upper 32-bits of MSR value.
1567 <b>Example usage</b>
1571 Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);
1572 AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);
1574 @note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM.
1576 #define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8
1580 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1582 @param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)
1583 @param EAX Lower 32-bits of MSR value.
1584 @param EDX Upper 32-bits of MSR value.
1586 <b>Example usage</b>
1590 Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);
1591 AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);
1593 @note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM.
1595 #define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9
1599 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1601 @param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)
1602 @param EAX Lower 32-bits of MSR value.
1603 @param EDX Upper 32-bits of MSR value.
1605 <b>Example usage</b>
1609 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);
1610 AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);
1612 @note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM.
1614 #define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA
1618 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1620 @param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)
1621 @param EAX Lower 32-bits of MSR value.
1622 @param EDX Upper 32-bits of MSR value.
1624 <b>Example usage</b>
1628 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);
1629 AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);
1631 @note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM.
1633 #define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB
1637 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1639 @param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)
1640 @param EAX Lower 32-bits of MSR value.
1641 @param EDX Upper 32-bits of MSR value.
1643 <b>Example usage</b>
1647 Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);
1648 AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);
1650 @note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM.
1652 #define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC
1656 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1658 @param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)
1659 @param EAX Lower 32-bits of MSR value.
1660 @param EDX Upper 32-bits of MSR value.
1662 <b>Example usage</b>
1666 Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);
1667 AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);
1669 @note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM.
1671 #define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD
1675 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1677 @param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)
1678 @param EAX Lower 32-bits of MSR value.
1679 @param EDX Upper 32-bits of MSR value.
1681 <b>Example usage</b>
1685 Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);
1686 AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);
1688 @note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM.
1690 #define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE
1694 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1696 @param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)
1697 @param EAX Lower 32-bits of MSR value.
1698 @param EDX Upper 32-bits of MSR value.
1700 <b>Example usage</b>
1704 Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);
1705 AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);
1707 @note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM.
1709 #define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF
1713 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1715 @param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)
1716 @param EAX Lower 32-bits of MSR value.
1717 @param EDX Upper 32-bits of MSR value.
1719 <b>Example usage</b>
1723 Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);
1724 AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);
1726 @note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM.
1728 #define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0
1732 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1734 @param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)
1735 @param EAX Lower 32-bits of MSR value.
1736 @param EDX Upper 32-bits of MSR value.
1738 <b>Example usage</b>
1742 Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);
1743 AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);
1745 @note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM.
1747 #define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1
1751 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1753 @param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)
1754 @param EAX Lower 32-bits of MSR value.
1755 @param EDX Upper 32-bits of MSR value.
1757 <b>Example usage</b>
1761 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);
1762 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);
1764 @note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM.
1766 #define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2
1770 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1772 @param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)
1773 @param EAX Lower 32-bits of MSR value.
1774 @param EDX Upper 32-bits of MSR value.
1776 <b>Example usage</b>
1780 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);
1781 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);
1783 @note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM.
1785 #define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3
1789 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1791 @param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)
1792 @param EAX Lower 32-bits of MSR value.
1793 @param EDX Upper 32-bits of MSR value.
1795 <b>Example usage</b>
1799 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);
1800 AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);
1802 @note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM.
1804 #define MSR_PENTIUM_4_IS_ESCR0 0x000003B4
1808 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1810 @param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)
1811 @param EAX Lower 32-bits of MSR value.
1812 @param EDX Upper 32-bits of MSR value.
1814 <b>Example usage</b>
1818 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);
1819 AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);
1821 @note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM.
1823 #define MSR_PENTIUM_4_IS_ESCR1 0x000003B5
1827 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1829 @param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)
1830 @param EAX Lower 32-bits of MSR value.
1831 @param EDX Upper 32-bits of MSR value.
1833 <b>Example usage</b>
1837 Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);
1838 AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);
1840 @note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM.
1842 #define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6
1846 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1848 @param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)
1849 @param EAX Lower 32-bits of MSR value.
1850 @param EDX Upper 32-bits of MSR value.
1852 <b>Example usage</b>
1856 Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);
1857 AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);
1859 @note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM.
1861 #define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7
1865 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1867 @param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)
1868 @param EAX Lower 32-bits of MSR value.
1869 @param EDX Upper 32-bits of MSR value.
1871 <b>Example usage</b>
1875 Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);
1876 AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);
1878 @note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM.
1880 #define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8
1884 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1886 @param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)
1887 @param EAX Lower 32-bits of MSR value.
1888 @param EDX Upper 32-bits of MSR value.
1890 <b>Example usage</b>
1894 Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);
1895 AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);
1897 @note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM.
1899 #define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9
1903 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not
1904 available on later processors. It is only available on processor family 0FH,
1907 @param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)
1908 @param EAX Lower 32-bits of MSR value.
1909 @param EDX Upper 32-bits of MSR value.
1911 <b>Example usage</b>
1915 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);
1916 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);
1918 @note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM.
1920 #define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA
1924 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not
1925 available on later processors. It is only available on processor family 0FH,
1928 @param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)
1929 @param EAX Lower 32-bits of MSR value.
1930 @param EDX Upper 32-bits of MSR value.
1932 <b>Example usage</b>
1936 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);
1937 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);
1939 @note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM.
1941 #define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB
1945 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1947 @param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)
1948 @param EAX Lower 32-bits of MSR value.
1949 @param EDX Upper 32-bits of MSR value.
1951 <b>Example usage</b>
1955 Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);
1956 AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);
1958 @note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM.
1960 #define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC
1964 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1966 @param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)
1967 @param EAX Lower 32-bits of MSR value.
1968 @param EDX Upper 32-bits of MSR value.
1970 <b>Example usage</b>
1974 Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);
1975 AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);
1977 @note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM.
1979 #define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD
1983 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
1985 @param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)
1986 @param EAX Lower 32-bits of MSR value.
1987 @param EDX Upper 32-bits of MSR value.
1989 <b>Example usage</b>
1993 Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);
1994 AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);
1996 @note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM.
1998 #define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE
2002 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2004 @param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)
2005 @param EAX Lower 32-bits of MSR value.
2006 @param EDX Upper 32-bits of MSR value.
2008 <b>Example usage</b>
2012 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);
2013 AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);
2015 @note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM.
2017 #define MSR_PENTIUM_4_MS_ESCR0 0x000003C0
2021 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2023 @param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)
2024 @param EAX Lower 32-bits of MSR value.
2025 @param EDX Upper 32-bits of MSR value.
2027 <b>Example usage</b>
2031 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);
2032 AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);
2034 @note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM.
2036 #define MSR_PENTIUM_4_MS_ESCR1 0x000003C1
2040 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2042 @param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)
2043 @param EAX Lower 32-bits of MSR value.
2044 @param EDX Upper 32-bits of MSR value.
2046 <b>Example usage</b>
2050 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);
2051 AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);
2053 @note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM.
2055 #define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2
2059 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2061 @param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)
2062 @param EAX Lower 32-bits of MSR value.
2063 @param EDX Upper 32-bits of MSR value.
2065 <b>Example usage</b>
2069 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);
2070 AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);
2072 @note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM.
2074 #define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3
2078 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2080 @param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)
2081 @param EAX Lower 32-bits of MSR value.
2082 @param EDX Upper 32-bits of MSR value.
2084 <b>Example usage</b>
2088 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);
2089 AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);
2091 @note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM.
2093 #define MSR_PENTIUM_4_TC_ESCR0 0x000003C4
2097 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2099 @param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)
2100 @param EAX Lower 32-bits of MSR value.
2101 @param EDX Upper 32-bits of MSR value.
2103 <b>Example usage</b>
2107 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);
2108 AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);
2110 @note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM.
2112 #define MSR_PENTIUM_4_TC_ESCR1 0x000003C5
2116 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2118 @param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)
2119 @param EAX Lower 32-bits of MSR value.
2120 @param EDX Upper 32-bits of MSR value.
2122 <b>Example usage</b>
2126 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);
2127 AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);
2129 @note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM.
2131 #define MSR_PENTIUM_4_IX_ESCR0 0x000003C8
2135 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2137 @param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)
2138 @param EAX Lower 32-bits of MSR value.
2139 @param EDX Upper 32-bits of MSR value.
2141 <b>Example usage</b>
2145 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);
2146 AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);
2148 @note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM.
2150 #define MSR_PENTIUM_4_IX_ESCR1 0x000003C9
2154 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2156 @param ECX MSR_PENTIUM_4_ALF_ESCRn
2157 @param EAX Lower 32-bits of MSR value.
2158 @param EDX Upper 32-bits of MSR value.
2160 <b>Example usage</b>
2164 Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);
2165 AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);
2167 @note MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM.
2168 MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM.
2169 MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM.
2170 MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM.
2171 MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM.
2172 MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.
2175 #define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA
2176 #define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB
2177 #define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC
2178 #define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD
2179 #define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0
2180 #define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1
2185 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
2187 @param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)
2188 @param EAX Lower 32-bits of MSR value.
2189 @param EDX Upper 32-bits of MSR value.
2191 <b>Example usage</b>
2195 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);
2196 AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);
2198 @note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM.
2200 #define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0
2204 0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W)
2205 Controls the enabling of processor event sampling and replay tagging.
2207 @param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)
2208 @param EAX Lower 32-bits of MSR value.
2209 Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.
2210 @param EDX Upper 32-bits of MSR value.
2211 Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.
2213 <b>Example usage</b>
2215 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Msr;
2217 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);
2218 AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);
2220 @note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
2222 #define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1
2225 MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE
2229 /// Individual bit fields
2233 /// [Bits 12:0] See Table 19-36.
2236 UINT32 Reserved1
:11;
2238 /// [Bit 24] UOP Tag Enables replay tagging when set.
2242 /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical
2243 /// processor when set; disables PEBS when clear (default). See Section
2244 /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
2245 /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors
2246 /// that do not support Intel HyperThreading Technology.
2248 UINT32 ENABLE_PEBS_MY_THR
:1;
2250 /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical
2251 /// processor when set; disables PEBS when clear (default). See Section
2252 /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
2253 /// logical processor. This bit is reserved for IA-32 processors that do
2254 /// not support Intel Hyper-Threading Technology.
2256 UINT32 ENABLE_PEBS_OTH_THR
:1;
2258 UINT32 Reserved3
:32;
2261 /// All bit fields as a 32-bit value
2265 /// All bit fields as a 64-bit value
2268 } MSR_PENTIUM_4_PEBS_ENABLE_REGISTER
;
2272 0, 1, 2, 3, 4, 6. Shared. See Table 19-36.
2274 @param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)
2275 @param EAX Lower 32-bits of MSR value.
2276 @param EDX Upper 32-bits of MSR value.
2278 <b>Example usage</b>
2282 Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);
2283 AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);
2285 @note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM.
2287 #define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2
2291 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch
2292 record registers on the last branch record stack (680H-68FH). This part of
2293 the stack contains pointers to the source instruction for one of the last 16
2294 branches, exceptions, or interrupts taken by the processor. The MSRs at
2295 680H-68FH, 6C0H-6CfH are not available in processor releases before family
2296 0FH, model 03H. These MSRs replace MSRs previously located at
2297 1DBH-1DEH.which performed the same function for early releases. See Section
2298 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for
2299 Processors based on Skylake Microarchitecture.".
2301 @param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
2302 @param EAX Lower 32-bits of MSR value.
2303 @param EDX Upper 32-bits of MSR value.
2305 <b>Example usage</b>
2309 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
2310 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);
2312 @note MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
2313 MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
2314 MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
2315 MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
2316 MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
2317 MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
2318 MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
2319 MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
2320 MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
2321 MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
2322 MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
2323 MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
2324 MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
2325 MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
2326 MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
2327 MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
2330 #define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680
2331 #define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681
2332 #define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682
2333 #define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683
2334 #define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684
2335 #define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685
2336 #define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686
2337 #define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687
2338 #define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688
2339 #define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689
2340 #define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A
2341 #define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B
2342 #define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C
2343 #define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D
2344 #define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E
2345 #define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F
2350 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch
2351 record registers on the last branch record stack (6C0H-6CFH). This part of
2352 the stack contains pointers to the destination instruction for one of the
2353 last 16 branches, exceptions, or interrupts that the processor took. See
2354 Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording
2355 for Processors based on Skylake Microarchitecture.".
2357 @param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
2358 @param EAX Lower 32-bits of MSR value.
2359 @param EDX Upper 32-bits of MSR value.
2361 <b>Example usage</b>
2365 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
2366 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);
2368 @note MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
2369 MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
2370 MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
2371 MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
2372 MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
2373 MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
2374 MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
2375 MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
2376 MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
2377 MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
2378 MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
2379 MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
2380 MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
2381 MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
2382 MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
2383 MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
2386 #define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0
2387 #define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1
2388 #define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2
2389 #define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3
2390 #define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4
2391 #define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5
2392 #define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6
2393 #define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7
2394 #define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8
2395 #define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9
2396 #define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA
2397 #define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB
2398 #define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC
2399 #define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD
2400 #define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE
2401 #define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF
2406 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section
2407 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
2410 @param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)
2411 @param EAX Lower 32-bits of MSR value.
2412 @param EDX Upper 32-bits of MSR value.
2414 <b>Example usage</b>
2418 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);
2419 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);
2421 @note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM.
2423 #define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC
2427 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).
2429 @param ECX MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD)
2430 @param EAX Lower 32-bits of MSR value.
2431 @param EDX Upper 32-bits of MSR value.
2433 <b>Example usage</b>
2437 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);
2438 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);
2440 @note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM.
2442 #define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD
2446 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section
2447 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
2450 @param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)
2451 @param EAX Lower 32-bits of MSR value.
2452 @param EDX Upper 32-bits of MSR value.
2454 <b>Example usage</b>
2458 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);
2459 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);
2461 @note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM.
2463 #define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE
2467 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).
2469 @param ECX MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF)
2470 @param EAX Lower 32-bits of MSR value.
2471 @param EDX Upper 32-bits of MSR value.
2473 <b>Example usage</b>
2477 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);
2478 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);
2480 @note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM.
2482 #define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF
2486 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section
2487 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
2490 @param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)
2491 @param EAX Lower 32-bits of MSR value.
2492 @param EDX Upper 32-bits of MSR value.
2494 <b>Example usage</b>
2498 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);
2499 AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);
2501 @note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM.
2503 #define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0
2507 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).
2509 @param ECX MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1)
2510 @param EAX Lower 32-bits of MSR value.
2511 @param EDX Upper 32-bits of MSR value.
2513 <b>Example usage</b>
2517 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);
2518 AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);
2520 @note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM.
2522 #define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1
2526 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6,
2527 "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte
2530 @param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)
2531 @param EAX Lower 32-bits of MSR value.
2532 @param EDX Upper 32-bits of MSR value.
2534 <b>Example usage</b>
2538 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);
2539 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);
2541 @note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM.
2543 #define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2
2547 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6,
2548 "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte
2551 @param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)
2552 @param EAX Lower 32-bits of MSR value.
2553 @param EDX Upper 32-bits of MSR value.
2555 <b>Example usage</b>
2559 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);
2560 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);
2562 @note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM.
2564 #define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3
2568 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section
2569 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
2572 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)
2573 @param EAX Lower 32-bits of MSR value.
2574 @param EDX Upper 32-bits of MSR value.
2576 <b>Example usage</b>
2580 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);
2581 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);
2583 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.
2585 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC
2589 6. Shared. GBUSQ Event Control and Counter Register (R/W).
2591 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD)
2592 @param EAX Lower 32-bits of MSR value.
2593 @param EDX Upper 32-bits of MSR value.
2595 <b>Example usage</b>
2599 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);
2600 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);
2602 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.
2604 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD
2608 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section
2609 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
2612 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)
2613 @param EAX Lower 32-bits of MSR value.
2614 @param EDX Upper 32-bits of MSR value.
2616 <b>Example usage</b>
2620 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);
2621 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);
2623 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.
2625 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE
2629 6. Shared. GSNPQ Event Control and Counter Register (R/W).
2631 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF)
2632 @param EAX Lower 32-bits of MSR value.
2633 @param EDX Upper 32-bits of MSR value.
2635 <b>Example usage</b>
2639 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);
2640 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);
2642 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.
2644 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF
2648 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6,
2649 "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte
2652 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)
2653 @param EAX Lower 32-bits of MSR value.
2654 @param EDX Upper 32-bits of MSR value.
2656 <b>Example usage</b>
2660 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);
2661 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);
2663 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.
2665 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0
2669 6. Shared. FSB Event Control and Counter Register (R/W).
2671 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1)
2672 @param EAX Lower 32-bits of MSR value.
2673 @param EDX Upper 32-bits of MSR value.
2675 <b>Example usage</b>
2679 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);
2680 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);
2682 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.
2684 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1
2688 6. Shared. FSB Event Control and Counter Register (R/W).
2690 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2)
2691 @param EAX Lower 32-bits of MSR value.
2692 @param EDX Upper 32-bits of MSR value.
2694 <b>Example usage</b>
2698 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);
2699 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);
2701 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.
2703 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2
2707 6. Shared. FSB Event Control and Counter Register (R/W).
2709 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3)
2710 @param EAX Lower 32-bits of MSR value.
2711 @param EDX Upper 32-bits of MSR value.
2713 <b>Example usage</b>
2717 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);
2718 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);
2720 @note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.
2722 #define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3