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1 /** @file
2 MSR Definitions for Pentium M Processors.
3
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
7 provided for that MSR.
8
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
11
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
15
16 **/
17
18 #ifndef __PENTIUM_M_MSR_H__
19 #define __PENTIUM_M_MSR_H__
20
21 #include <Register/Intel/ArchitecturalMsr.h>
22
23 /**
24 Is Pentium M Processors?
25
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
28
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
31 **/
32 #define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x0D \
36 ) \
37 )
38
39 /**
40 See Section 2.22, "MSRs in Pentium Processors.".
41
42 @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
43 @param EAX Lower 32-bits of MSR value.
44 @param EDX Upper 32-bits of MSR value.
45
46 <b>Example usage</b>
47 @code
48 UINT64 Msr;
49
50 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
51 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
52 @endcode
53 @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
54 **/
55 #define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000
56
57 /**
58 See Section 2.22, "MSRs in Pentium Processors.".
59
60 @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
61 @param EAX Lower 32-bits of MSR value.
62 @param EDX Upper 32-bits of MSR value.
63
64 <b>Example usage</b>
65 @code
66 UINT64 Msr;
67
68 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
69 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
70 @endcode
71 @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
72 **/
73 #define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001
74
75 /**
76 Processor Hard Power-On Configuration (R/W) Enables and disables processor
77 features. (R) Indicates current processor configuration.
78
79 @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
80 @param EAX Lower 32-bits of MSR value.
81 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
82 @param EDX Upper 32-bits of MSR value.
83 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
84
85 <b>Example usage</b>
86 @code
87 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;
88
89 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
90 AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
91 @endcode
92 @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
93 **/
94 #define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A
95
96 /**
97 MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
98 **/
99 typedef union {
100 ///
101 /// Individual bit fields
102 ///
103 struct {
104 UINT32 Reserved1 : 1;
105 ///
106 /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
107 /// Pentium M processor.
108 ///
109 UINT32 DataErrorCheckingEnable : 1;
110 ///
111 /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
112 /// the Pentium M processor.
113 ///
114 UINT32 ResponseErrorCheckingEnable : 1;
115 ///
116 /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium
117 /// M processor.
118 ///
119 UINT32 MCERR_DriveEnable : 1;
120 ///
121 /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
122 /// M processor.
123 ///
124 UINT32 AddressParityEnable : 1;
125 UINT32 Reserved2 : 2;
126 ///
127 /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
128 /// the Pentium M processor.
129 ///
130 UINT32 BINIT_DriverEnable : 1;
131 ///
132 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
133 ///
134 UINT32 OutputTriStateEnable : 1;
135 ///
136 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
137 ///
138 UINT32 ExecuteBIST : 1;
139 ///
140 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
141 /// Always 0 on the Pentium M processor.
142 ///
143 UINT32 MCERR_ObservationEnabled : 1;
144 UINT32 Reserved3 : 1;
145 ///
146 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
147 /// Always 0 on the Pentium M processor.
148 ///
149 UINT32 BINIT_ObservationEnabled : 1;
150 UINT32 Reserved4 : 1;
151 ///
152 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes
153 /// Always 0 on the Pentium M processor.
154 ///
155 UINT32 ResetVector : 1;
156 UINT32 Reserved5 : 1;
157 ///
158 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M
159 /// processor.
160 ///
161 UINT32 APICClusterID : 2;
162 ///
163 /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always
164 /// 0 on the Pentium M processor.
165 ///
166 UINT32 SystemBusFrequency : 1;
167 UINT32 Reserved6 : 1;
168 ///
169 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium
170 /// M processor.
171 ///
172 UINT32 SymmetricArbitrationID : 2;
173 ///
174 /// [Bits 26:22] Clock Frequency Ratio (R/O).
175 ///
176 UINT32 ClockFrequencyRatio : 5;
177 UINT32 Reserved7 : 5;
178 UINT32 Reserved8 : 32;
179 } Bits;
180 ///
181 /// All bit fields as a 32-bit value
182 ///
183 UINT32 Uint32;
184 ///
185 /// All bit fields as a 64-bit value
186 ///
187 UINT64 Uint64;
188 } MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;
189
190 /**
191 Last Branch Record n (R/W) One of 8 last branch record registers on the last
192 branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
193 the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section
194 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
195 Processors)".
196
197 @param ECX MSR_PENTIUM_M_LASTBRANCH_n
198 @param EAX Lower 32-bits of MSR value.
199 @param EDX Upper 32-bits of MSR value.
200
201 <b>Example usage</b>
202 @code
203 UINT64 Msr;
204
205 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
206 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
207 @endcode
208 @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
209 MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
210 MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
211 MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
212 MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
213 MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
214 MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
215 MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
216 @{
217 **/
218 #define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040
219 #define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041
220 #define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042
221 #define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043
222 #define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044
223 #define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045
224 #define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046
225 #define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047
226 /// @}
227
228 /**
229 Reserved.
230
231 @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
232 @param EAX Lower 32-bits of MSR value.
233 @param EDX Upper 32-bits of MSR value.
234
235 <b>Example usage</b>
236 @code
237 UINT64 Msr;
238
239 Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
240 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
241 @endcode
242 @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.
243 **/
244 #define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119
245
246 /**
247
248
249 @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
250 @param EAX Lower 32-bits of MSR value.
251 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
252 @param EDX Upper 32-bits of MSR value.
253 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
254
255 <b>Example usage</b>
256 @code
257 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;
258
259 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
260 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
261 @endcode
262 @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
263 **/
264 #define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E
265
266 /**
267 MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3
268 **/
269 typedef union {
270 ///
271 /// Individual bit fields
272 ///
273 struct {
274 ///
275 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
276 /// Indicates if the L2 is hardware-disabled.
277 ///
278 UINT32 L2HardwareEnabled : 1;
279 UINT32 Reserved1 : 4;
280 ///
281 /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the
282 /// cache data bus. ECC is always generated on write cycles. 1. = Disabled
283 /// (default) 2. = Enabled For the Pentium M processor, ECC checking on
284 /// the cache data bus is always enabled.
285 ///
286 UINT32 ECCCheckEnable : 1;
287 UINT32 Reserved2 : 2;
288 ///
289 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =
290 /// Disabled (default) Until this bit is set the processor will not
291 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
292 ///
293 UINT32 L2Enabled : 1;
294 UINT32 Reserved3 : 14;
295 ///
296 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
297 ///
298 UINT32 L2NotPresent : 1;
299 UINT32 Reserved4 : 8;
300 UINT32 Reserved5 : 32;
301 } Bits;
302 ///
303 /// All bit fields as a 32-bit value
304 ///
305 UINT32 Uint32;
306 ///
307 /// All bit fields as a 64-bit value
308 ///
309 UINT64 Uint64;
310 } MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;
311
312 /**
313
314
315 @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)
316 @param EAX Lower 32-bits of MSR value.
317 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
318 @param EDX Upper 32-bits of MSR value.
319 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
320
321 <b>Example usage</b>
322 @code
323 MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;
324
325 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
326 AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
327 @endcode
328 @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
329 **/
330 #define MSR_PENTIUM_M_THERM2_CTL 0x0000019D
331
332 /**
333 MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL
334 **/
335 typedef union {
336 ///
337 /// Individual bit fields
338 ///
339 struct {
340 UINT32 Reserved1 : 16;
341 ///
342 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
343 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
344 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
345 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
346 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
347 ///
348 UINT32 TM_SELECT : 1;
349 UINT32 Reserved2 : 15;
350 UINT32 Reserved3 : 32;
351 } Bits;
352 ///
353 /// All bit fields as a 32-bit value
354 ///
355 UINT32 Uint32;
356 ///
357 /// All bit fields as a 64-bit value
358 ///
359 UINT64 Uint64;
360 } MSR_PENTIUM_M_THERM2_CTL_REGISTER;
361
362 /**
363 Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
364 functions to be enabled and disabled.
365
366 @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
367 @param EAX Lower 32-bits of MSR value.
368 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
369 @param EDX Upper 32-bits of MSR value.
370 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
371
372 <b>Example usage</b>
373 @code
374 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;
375
376 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
377 AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
378 @endcode
379 @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
380 **/
381 #define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0
382
383 /**
384 MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE
385 **/
386 typedef union {
387 ///
388 /// Individual bit fields
389 ///
390 struct {
391 UINT32 Reserved1 : 3;
392 ///
393 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
394 /// this bit enables the thermal control circuit (TCC) portion of the
395 /// Intel Thermal Monitor feature. This allows processor clocks to be
396 /// automatically modulated based on the processor's thermal sensor
397 /// operation. 0 = Disabled (default). The automatic thermal control
398 /// circuit enable bit determines if the thermal control circuit (TCC)
399 /// will be activated when the processor's internal thermal sensor
400 /// determines the processor is about to exceed its maximum operating
401 /// temperature. When the TCC is activated and TM1 is enabled, the
402 /// processors clocks will be forced to a 50% duty cycle. BIOS must enable
403 /// this feature. The bit should not be confused with the on-demand
404 /// thermal control circuit enable bit.
405 ///
406 UINT32 AutomaticThermalControlCircuit : 1;
407 UINT32 Reserved2 : 3;
408 ///
409 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
410 /// monitoring enabled 0 = Performance monitoring disabled.
411 ///
412 UINT32 PerformanceMonitoring : 1;
413 UINT32 Reserved3 : 2;
414 ///
415 /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the
416 /// processor to indicate a pending break event within the processor 0 =
417 /// Indicates compatible FERR# signaling behavior This bit must be set to
418 /// 1 to support XAPIC interrupt model usage.
419 /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't
420 /// support branch trace storage (BTS) 0 = BTS is supported
421 ///
422 UINT32 FERR : 1;
423 ///
424 /// [Bit 11] Branch Trace Storage Unavailable (RO)
425 /// 1 = Processor doesn't support branch trace storage (BTS)
426 /// 0 = BTS is supported
427 ///
428 UINT32 BTS : 1;
429 ///
430 /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =
431 /// Processor does not support processor event based sampling (PEBS); 0 =
432 /// PEBS is supported. The Pentium M processor does not support PEBS.
433 ///
434 UINT32 PEBS : 1;
435 UINT32 Reserved5 : 3;
436 ///
437 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
438 /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M
439 /// processor, this bit may be configured to be read-only.
440 ///
441 UINT32 EIST : 1;
442 UINT32 Reserved6 : 6;
443 ///
444 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
445 /// disabled. xTPR messages are optional messages that allow the processor
446 /// to inform the chipset of its priority. The default is processor
447 /// specific.
448 ///
449 UINT32 xTPR_Message_Disable : 1;
450 UINT32 Reserved7 : 8;
451 UINT32 Reserved8 : 32;
452 } Bits;
453 ///
454 /// All bit fields as a 32-bit value
455 ///
456 UINT32 Uint32;
457 ///
458 /// All bit fields as a 64-bit value
459 ///
460 UINT64 Uint64;
461 } MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;
462
463 /**
464 Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points
465 to the MSR containing the most recent branch record. See also: -
466 MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,
467 and Exception Recording (Pentium M Processors)".
468
469 @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
470 @param EAX Lower 32-bits of MSR value.
471 @param EDX Upper 32-bits of MSR value.
472
473 <b>Example usage</b>
474 @code
475 UINT64 Msr;
476
477 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
478 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
479 @endcode
480 @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
481 **/
482 #define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9
483
484 /**
485 Debug Control (R/W) Controls how several debug features are used. Bit
486 definitions are discussed in the referenced section. See Section 17.15,
487 "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
488
489 @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
490 @param EAX Lower 32-bits of MSR value.
491 @param EDX Upper 32-bits of MSR value.
492
493 <b>Example usage</b>
494 @code
495 UINT64 Msr;
496
497 Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
498 AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
499 @endcode
500 @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.
501 **/
502 #define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9
503
504 /**
505 Last Exception Record To Linear IP (R) This area contains a pointer to the
506 target of the last branch instruction that the processor executed prior to
507 the last exception that was generated or the last interrupt that was
508 handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording
509 (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception
510 MSRs.".
511
512 @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
513 @param EAX Lower 32-bits of MSR value.
514 @param EDX Upper 32-bits of MSR value.
515
516 <b>Example usage</b>
517 @code
518 UINT64 Msr;
519
520 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
521 @endcode
522 @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
523 **/
524 #define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD
525
526 /**
527 Last Exception Record From Linear IP (R) Contains a pointer to the last
528 branch instruction that the processor executed prior to the last exception
529 that was generated or the last interrupt that was handled. See Section
530 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
531 Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".
532
533 @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
534 @param EAX Lower 32-bits of MSR value.
535 @param EDX Upper 32-bits of MSR value.
536
537 <b>Example usage</b>
538 @code
539 UINT64 Msr;
540
541 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
542 @endcode
543 @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
544 **/
545 #define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE
546
547 /**
548 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
549
550 @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)
551 @param EAX Lower 32-bits of MSR value.
552 @param EDX Upper 32-bits of MSR value.
553
554 <b>Example usage</b>
555 @code
556 UINT64 Msr;
557
558 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
559 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
560 @endcode
561 @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.
562 **/
563 #define MSR_PENTIUM_M_MC4_CTL 0x0000040C
564
565 /**
566 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
567
568 @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)
569 @param EAX Lower 32-bits of MSR value.
570 @param EDX Upper 32-bits of MSR value.
571
572 <b>Example usage</b>
573 @code
574 UINT64 Msr;
575
576 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
577 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
578 @endcode
579 @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
580 **/
581 #define MSR_PENTIUM_M_MC4_STATUS 0x0000040D
582
583 /**
584 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is
585 either not implemented or contains no address if the ADDRV flag in the
586 MSR_MC4_STATUS register is clear. When not implemented in the processor, all
587 reads and writes to this MSR will cause a general-protection exception.
588
589 @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)
590 @param EAX Lower 32-bits of MSR value.
591 @param EDX Upper 32-bits of MSR value.
592
593 <b>Example usage</b>
594 @code
595 UINT64 Msr;
596
597 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
598 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);
599 @endcode
600 @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
601 **/
602 #define MSR_PENTIUM_M_MC4_ADDR 0x0000040E
603
604 /**
605 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
606
607 @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)
608 @param EAX Lower 32-bits of MSR value.
609 @param EDX Upper 32-bits of MSR value.
610
611 <b>Example usage</b>
612 @code
613 UINT64 Msr;
614
615 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
616 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);
617 @endcode
618 @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.
619 **/
620 #define MSR_PENTIUM_M_MC3_CTL 0x00000410
621
622 /**
623 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
624
625 @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)
626 @param EAX Lower 32-bits of MSR value.
627 @param EDX Upper 32-bits of MSR value.
628
629 <b>Example usage</b>
630 @code
631 UINT64 Msr;
632
633 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
634 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);
635 @endcode
636 @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
637 **/
638 #define MSR_PENTIUM_M_MC3_STATUS 0x00000411
639
640 /**
641 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is
642 either not implemented or contains no address if the ADDRV flag in the
643 MSR_MC3_STATUS register is clear. When not implemented in the processor, all
644 reads and writes to this MSR will cause a general-protection exception.
645
646 @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)
647 @param EAX Lower 32-bits of MSR value.
648 @param EDX Upper 32-bits of MSR value.
649
650 <b>Example usage</b>
651 @code
652 UINT64 Msr;
653
654 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
655 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);
656 @endcode
657 @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
658 **/
659 #define MSR_PENTIUM_M_MC3_ADDR 0x00000412
660
661 #endif
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