MdePkg/Include/Register/Intel/Msr/PentiumMsr.h

   1 /** @file
   2   MSR Definitions for Pentium Processors.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __PENTIUM_MSR_H__
  19 #define __PENTIUM_MSR_H__
  20
  21 #include <Register/Intel/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Pentium Processors?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x05 && \
  34    (                        \
  35     DisplayModel == 0x01 || \
  36     DisplayModel == 0x02 || \
  37     DisplayModel == 0x04    \
  38     )                       \
  39    )
  40
  41 /**
  42   See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
  43
  44   @param  ECX  MSR_PENTIUM_P5_MC_ADDR (0x00000000)
  45   @param  EAX  Lower 32-bits of MSR value.
  46   @param  EDX  Upper 32-bits of MSR value.
  47
  48   <b>Example usage</b>
  49   @code
  50   UINT64  Msr;
  51
  52   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
  53   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
  54   @endcode
  55   @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
  56 **/
  57 #define MSR_PENTIUM_P5_MC_ADDR  0x00000000
  58
  59 /**
  60   See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
  61
  62   @param  ECX  MSR_PENTIUM_P5_MC_TYPE (0x00000001)
  63   @param  EAX  Lower 32-bits of MSR value.
  64   @param  EDX  Upper 32-bits of MSR value.
  65
  66   <b>Example usage</b>
  67   @code
  68   UINT64  Msr;
  69
  70   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
  71   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
  72   @endcode
  73   @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
  74 **/
  75 #define MSR_PENTIUM_P5_MC_TYPE  0x00000001
  76
  77 /**
  78   See Section 17.17, "Time-Stamp Counter.".
  79
  80   @param  ECX  MSR_PENTIUM_TSC (0x00000010)
  81   @param  EAX  Lower 32-bits of MSR value.
  82   @param  EDX  Upper 32-bits of MSR value.
  83
  84   <b>Example usage</b>
  85   @code
  86   UINT64  Msr;
  87
  88   Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
  89   AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
  90   @endcode
  91   @note MSR_PENTIUM_TSC is defined as TSC in SDM.
  92 **/
  93 #define MSR_PENTIUM_TSC  0x00000010
  94
  95 /**
  96   See Section 18.6.9.1, "Control and Event Select Register (CESR).".
  97
  98   @param  ECX  MSR_PENTIUM_CESR (0x00000011)
  99   @param  EAX  Lower 32-bits of MSR value.
 100   @param  EDX  Upper 32-bits of MSR value.
 101
 102   <b>Example usage</b>
 103   @code
 104   UINT64  Msr;
 105
 106   Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
 107   AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
 108   @endcode
 109   @note MSR_PENTIUM_CESR is defined as CESR in SDM.
 110 **/
 111 #define MSR_PENTIUM_CESR  0x00000011
 112
 113 /**
 114   Section 18.6.9.3, "Events Counted.".
 115
 116   @param  ECX  MSR_PENTIUM_CTRn
 117   @param  EAX  Lower 32-bits of MSR value.
 118   @param  EDX  Upper 32-bits of MSR value.
 119
 120   <b>Example usage</b>
 121   @code
 122   UINT64  Msr;
 123
 124   Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
 125   AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
 126   @endcode
 127   @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.
 128         MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.
 129   @{
 130 **/
 131 #define MSR_PENTIUM_CTR0  0x00000012
 132 #define MSR_PENTIUM_CTR1  0x00000013
 133 /// @}
 134
 135 #endif