2 MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
18 #ifndef __SANDY_BRIDGE_MSR_H__
19 #define __SANDY_BRIDGE_MSR_H__
21 #include <Register/Intel/ArchitecturalMsr.h>
24 Is Intel processors based on the Sandy Bridge microarchitecture?
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
32 #define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
35 DisplayModel == 0x2A || \
36 DisplayModel == 0x2D \
41 Thread. SMI Counter (R/O).
43 @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)
44 @param EAX Lower 32-bits of MSR value.
45 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
46 @param EDX Upper 32-bits of MSR value.
47 Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
51 MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr;
53 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);
55 @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
57 #define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034
60 MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT
64 /// Individual bit fields
68 /// [Bits 31:0] SMI Count (R/O) Count SMIs.
74 /// All bit fields as a 32-bit value
78 /// All bit fields as a 64-bit value
81 } MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER
;
84 Package. Platform Information Contains power management and other model
85 specific features enumeration. See http://biosbits.org.
87 @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)
88 @param EAX Lower 32-bits of MSR value.
89 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
90 @param EDX Upper 32-bits of MSR value.
91 Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
95 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr;
97 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);
98 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
100 @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
102 #define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE
105 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO
109 /// Individual bit fields
112 UINT32 Reserved1
: 8;
114 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
115 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
118 UINT32 MaximumNonTurboRatio
: 8;
119 UINT32 Reserved2
: 12;
121 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
122 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
123 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
124 /// Turbo mode is disabled.
126 UINT32 RatioLimit
: 1;
128 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
129 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
130 /// and when set to 0, indicates TDP Limit for Turbo mode is not
134 UINT32 Reserved3
: 2;
135 UINT32 Reserved4
: 8;
137 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
138 /// minimum ratio (maximum efficiency) that the processor can operates, in
141 UINT32 MaximumEfficiencyRatio
: 8;
142 UINT32 Reserved5
: 16;
145 /// All bit fields as a 64-bit value
148 } MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER
;
151 Core. C-State Configuration Control (R/W) Note: C-state values are
152 processor specific C-state code names, unrelated to MWAIT extension C-state
153 parameters or ACPI CStates. See http://biosbits.org.
155 @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
156 @param EAX Lower 32-bits of MSR value.
157 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
158 @param EDX Upper 32-bits of MSR value.
159 Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
163 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
165 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);
166 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
168 @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
170 #define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2
173 MSR information returned for MSR index
174 #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL
178 /// Individual bit fields
182 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
183 /// processor-specific C-state code name (consuming the least power). for
184 /// the package. The default is set as factory-configured package C-state
185 /// limit. The following C-state code name encodings are supported: 000b:
186 /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
187 /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
188 /// This field cannot be used to limit package C-state to C3.
191 UINT32 Reserved1
: 7;
193 /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map
194 /// IO_read instructions sent to IO register specified by
195 /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
198 UINT32 Reserved2
: 4;
200 /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register
201 /// until next reset.
204 UINT32 Reserved3
: 9;
206 /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor
207 /// will conditionally demote C6/C7 requests to C3 based on uncore
208 /// auto-demote information.
210 UINT32 C3AutoDemotion
: 1;
212 /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor
213 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
214 /// auto-demote information.
216 UINT32 C1AutoDemotion
: 1;
218 /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from
221 UINT32 C3Undemotion
: 1;
223 /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from
226 UINT32 C1Undemotion
: 1;
227 UINT32 Reserved4
: 3;
228 UINT32 Reserved5
: 32;
231 /// All bit fields as a 32-bit value
235 /// All bit fields as a 64-bit value
238 } MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
;
241 Core. Power Management IO Redirection in C-state (R/W) See
244 @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)
245 @param EAX Lower 32-bits of MSR value.
246 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
247 @param EDX Upper 32-bits of MSR value.
248 Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
252 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr;
254 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);
255 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);
257 @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
259 #define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4
262 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE
266 /// Individual bit fields
270 /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address
271 /// visible to software for IO redirection. If IO MWAIT Redirection is
272 /// enabled, reads to this address will be consumed by the power
273 /// management logic and decoded to MWAIT instructions. When IO port
274 /// address redirection is enabled, this is the IO port address reported
275 /// to the OS/software.
277 UINT32 Lvl2Base
: 16;
279 /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the
280 /// maximum C-State code name to be included when IO read to MWAIT
281 /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
282 /// is the max C-State to include 001b - C6 is the max C-State to include
283 /// 010b - C7 is the max C-State to include.
285 UINT32 CStateRange
: 3;
286 UINT32 Reserved1
: 13;
287 UINT32 Reserved2
: 32;
290 /// All bit fields as a 32-bit value
294 /// All bit fields as a 64-bit value
297 } MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER
;
300 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
301 handler to handle unsuccessful read of this MSR.
303 @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)
304 @param EAX Lower 32-bits of MSR value.
305 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
306 @param EDX Upper 32-bits of MSR value.
307 Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
311 MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr;
313 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
314 AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);
316 @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
318 #define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C
321 MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG
325 /// Individual bit fields
329 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
330 /// MSR, the configuration of AES instruction set availability is as
331 /// follows: 11b: AES instructions are not available until next RESET.
332 /// otherwise, AES instructions are available. Note, AES instruction set
333 /// is not available if read is unsuccessful. If the configuration is not
334 /// 01b, AES instruction can be mis-configured if a privileged agent
335 /// unintentionally writes 11b.
337 UINT32 AESConfiguration
: 2;
338 UINT32 Reserved1
: 30;
339 UINT32 Reserved2
: 32;
342 /// All bit fields as a 32-bit value
346 /// All bit fields as a 64-bit value
349 } MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER
;
352 Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8.
354 @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn
355 @param EAX Lower 32-bits of MSR value.
356 @param EDX Upper 32-bits of MSR value.
362 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);
363 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);
365 @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM.
366 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM.
367 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM.
368 MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.
371 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A
372 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B
373 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C
374 #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D
380 @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)
381 @param EAX Lower 32-bits of MSR value.
382 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
383 @param EDX Upper 32-bits of MSR value.
384 Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
388 MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr;
390 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);
391 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);
393 @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
395 #define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198
398 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS
402 /// Individual bit fields
405 UINT32 Reserved1
: 32;
407 /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed
408 /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).
410 UINT32 CoreVoltage
: 16;
411 UINT32 Reserved2
: 16;
414 /// All bit fields as a 64-bit value
417 } MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER
;
420 Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was
421 originally named IA32_THERM_CONTROL MSR.
423 @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)
424 @param EAX Lower 32-bits of MSR value.
425 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
426 @param EDX Upper 32-bits of MSR value.
427 Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
431 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr;
433 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);
434 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);
436 @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
438 #define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A
441 MSR information returned for MSR index
442 #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION
446 /// Individual bit fields
450 /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%
453 UINT32 OnDemandClockModulationDutyCycle
: 4;
455 /// [Bit 4] On demand Clock Modulation Enable (R/W).
457 UINT32 OnDemandClockModulationEnable
: 1;
458 UINT32 Reserved1
: 27;
459 UINT32 Reserved2
: 32;
462 /// All bit fields as a 32-bit value
466 /// All bit fields as a 64-bit value
469 } MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
;
472 Enable Misc. Processor Features (R/W) Allows a variety of processor
473 functions to be enabled and disabled.
475 @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)
476 @param EAX Lower 32-bits of MSR value.
477 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
478 @param EDX Upper 32-bits of MSR value.
479 Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
483 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr;
485 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);
486 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);
488 @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
490 #define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0
493 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE
497 /// Individual bit fields
501 /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.
503 UINT32 FastStrings
: 1;
504 UINT32 Reserved1
: 6;
506 /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.
508 UINT32 PerformanceMonitoring
: 1;
509 UINT32 Reserved2
: 3;
511 /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.
515 /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
519 UINT32 Reserved3
: 3;
521 /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
525 UINT32 Reserved4
: 1;
527 /// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.
530 UINT32 Reserved5
: 3;
532 /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.
534 UINT32 LimitCpuidMaxval
: 1;
536 /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.
538 UINT32 xTPR_Message_Disable
: 1;
539 UINT32 Reserved6
: 8;
540 UINT32 Reserved7
: 2;
542 /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.
545 UINT32 Reserved8
: 3;
547 /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
548 /// that support Intel Turbo Boost Technology, the turbo mode feature is
549 /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
550 /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
551 /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
552 /// the power-on default value is used by BIOS to detect hardware support
553 /// of turbo mode. If power-on default value is 1, turbo mode is available
554 /// in the processor. If power-on default value is 0, turbo mode is not
557 UINT32 TurboModeDisable
: 1;
558 UINT32 Reserved9
: 25;
561 /// All bit fields as a 64-bit value
564 } MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER
;
569 @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
570 @param EAX Lower 32-bits of MSR value.
571 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
572 @param EDX Upper 32-bits of MSR value.
573 Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
577 MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;
579 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);
580 AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
582 @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
584 #define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2
587 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET
591 /// Individual bit fields
594 UINT32 Reserved1
: 16;
596 /// [Bits 23:16] Temperature Target (R) The minimum temperature at which
597 /// PROCHOT# will be asserted. The value is degree C.
599 UINT32 TemperatureTarget
: 8;
600 UINT32 Reserved2
: 8;
601 UINT32 Reserved3
: 32;
604 /// All bit fields as a 32-bit value
608 /// All bit fields as a 64-bit value
611 } MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER
;
614 Miscellaneous Feature Control (R/W).
616 @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)
617 @param EAX Lower 32-bits of MSR value.
618 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
619 @param EDX Upper 32-bits of MSR value.
620 Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
624 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr;
626 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);
627 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);
629 @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
631 #define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4
634 MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL
638 /// Individual bit fields
642 /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
643 /// L2 hardware prefetcher, which fetches additional lines of code or data
644 /// into the L2 cache.
646 UINT32 L2HardwarePrefetcherDisable
: 1;
648 /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,
649 /// disables the adjacent cache line prefetcher, which fetches the cache
650 /// line that comprises a cache line pair (128 bytes).
652 UINT32 L2AdjacentCacheLinePrefetcherDisable
: 1;
654 /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables
655 /// the L1 data cache prefetcher, which fetches the next cache line into
658 UINT32 DCUHardwarePrefetcherDisable
: 1;
660 /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1
661 /// data cache IP prefetcher, which uses sequential load history (based on
662 /// instruction Pointer of previous loads) to determine whether to
663 /// prefetch additional lines.
665 UINT32 DCUIPPrefetcherDisable
: 1;
666 UINT32 Reserved1
: 28;
667 UINT32 Reserved2
: 32;
670 /// All bit fields as a 32-bit value
674 /// All bit fields as a 64-bit value
677 } MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
;
680 Thread. Offcore Response Event Select Register (R/W).
682 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)
683 @param EAX Lower 32-bits of MSR value.
684 @param EDX Upper 32-bits of MSR value.
690 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);
691 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);
693 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
695 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6
698 Thread. Offcore Response Event Select Register (R/W).
700 @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)
701 @param EAX Lower 32-bits of MSR value.
702 @param EDX Upper 32-bits of MSR value.
708 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);
709 AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);
711 @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
713 #define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7
716 See http://biosbits.org.
718 @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)
719 @param EAX Lower 32-bits of MSR value.
720 @param EDX Upper 32-bits of MSR value.
726 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);
727 AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);
729 @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
731 #define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA
734 Thread. Last Branch Record Filtering Select Register (R/W) See Section
735 17.9.2, "Filtering of Last Branch Records.".
737 @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)
738 @param EAX Lower 32-bits of MSR value.
739 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
740 @param EDX Upper 32-bits of MSR value.
741 Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
745 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr;
747 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);
748 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);
750 @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
752 #define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8
755 MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT
759 /// Individual bit fields
763 /// [Bit 0] CPL_EQ_0.
767 /// [Bit 1] CPL_NEQ_0.
769 UINT32 CPL_NEQ_0
: 1;
775 /// [Bit 3] NEAR_REL_CALL.
777 UINT32 NEAR_REL_CALL
: 1;
779 /// [Bit 4] NEAR_IND_CALL.
781 UINT32 NEAR_IND_CALL
: 1;
783 /// [Bit 5] NEAR_RET.
787 /// [Bit 6] NEAR_IND_JMP.
789 UINT32 NEAR_IND_JMP
: 1;
791 /// [Bit 7] NEAR_REL_JMP.
793 UINT32 NEAR_REL_JMP
: 1;
795 /// [Bit 8] FAR_BRANCH.
797 UINT32 FAR_BRANCH
: 1;
798 UINT32 Reserved1
: 23;
799 UINT32 Reserved2
: 32;
802 /// All bit fields as a 32-bit value
806 /// All bit fields as a 64-bit value
809 } MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER
;
812 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)
813 that points to the MSR containing the most recent branch record. See
814 MSR_LASTBRANCH_0_FROM_IP (at 680H).
816 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)
817 @param EAX Lower 32-bits of MSR value.
818 @param EDX Upper 32-bits of MSR value.
824 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);
825 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);
827 @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
829 #define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9
832 Thread. Last Exception Record From Linear IP (R) Contains a pointer to the
833 last branch instruction that the processor executed prior to the last
834 exception that was generated or the last interrupt that was handled.
836 @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)
837 @param EAX Lower 32-bits of MSR value.
838 @param EDX Upper 32-bits of MSR value.
844 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);
846 @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
848 #define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD
851 Thread. Last Exception Record To Linear IP (R) This area contains a pointer
852 to the target of the last branch instruction that the processor executed
853 prior to the last exception that was generated or the last interrupt that
856 @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)
857 @param EAX Lower 32-bits of MSR value.
858 @param EDX Upper 32-bits of MSR value.
864 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);
866 @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
868 #define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE
871 Core. See http://biosbits.org.
873 @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)
874 @param EAX Lower 32-bits of MSR value.
875 @param EDX Upper 32-bits of MSR value.
881 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);
882 AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);
884 @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.
886 #define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC
889 Package. Always 0 (CMCI not supported).
891 @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284)
892 @param EAX Lower 32-bits of MSR value.
893 @param EDX Upper 32-bits of MSR value.
899 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2);
900 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr);
902 @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
904 #define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284
907 See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".
909 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
910 @param EAX Lower 32-bits of MSR value.
911 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.
912 @param EDX Upper 32-bits of MSR value.
913 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.
917 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
919 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS);
920 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
922 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
924 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E
927 MSR information returned for MSR index
928 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS
932 /// Individual bit fields
936 /// [Bit 0] Thread. Ovf_PMC0.
940 /// [Bit 1] Thread. Ovf_PMC1.
944 /// [Bit 2] Thread. Ovf_PMC2.
948 /// [Bit 3] Thread. Ovf_PMC3.
952 /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
956 /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
960 /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
964 /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
967 UINT32 Reserved1
: 24;
969 /// [Bit 32] Thread. Ovf_FixedCtr0.
971 UINT32 Ovf_FixedCtr0
: 1;
973 /// [Bit 33] Thread. Ovf_FixedCtr1.
975 UINT32 Ovf_FixedCtr1
: 1;
977 /// [Bit 34] Thread. Ovf_FixedCtr2.
979 UINT32 Ovf_FixedCtr2
: 1;
980 UINT32 Reserved2
: 26;
982 /// [Bit 61] Thread. Ovf_Uncore.
984 UINT32 Ovf_Uncore
: 1;
986 /// [Bit 62] Thread. Ovf_BufDSSAVE.
988 UINT32 Ovf_BufDSSAVE
: 1;
990 /// [Bit 63] Thread. CondChgd.
995 /// All bit fields as a 64-bit value
998 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER
;
1001 Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
1004 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)
1005 @param EAX Lower 32-bits of MSR value.
1006 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
1007 @param EDX Upper 32-bits of MSR value.
1008 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
1010 <b>Example usage</b>
1012 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
1014 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);
1015 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
1017 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
1019 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F
1022 MSR information returned for MSR index
1023 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL
1027 /// Individual bit fields
1031 /// [Bit 0] Thread. Set 1 to enable PMC0 to count.
1035 /// [Bit 1] Thread. Set 1 to enable PMC1 to count.
1039 /// [Bit 2] Thread. Set 1 to enable PMC2 to count.
1043 /// [Bit 3] Thread. Set 1 to enable PMC3 to count.
1047 /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >
1052 /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >
1057 /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >
1062 /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >
1066 UINT32 Reserved1
: 24;
1068 /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.
1070 UINT32 FIXED_CTR0
: 1;
1072 /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.
1074 UINT32 FIXED_CTR1
: 1;
1076 /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.
1078 UINT32 FIXED_CTR2
: 1;
1079 UINT32 Reserved2
: 29;
1082 /// All bit fields as a 64-bit value
1085 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
;
1088 See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".
1090 @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
1091 @param EAX Lower 32-bits of MSR value.
1092 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
1093 @param EDX Upper 32-bits of MSR value.
1094 Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
1096 <b>Example usage</b>
1098 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
1100 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);
1101 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
1103 @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
1105 #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
1108 MSR information returned for MSR index
1109 #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL
1113 /// Individual bit fields
1117 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
1119 UINT32 Ovf_PMC0
: 1;
1121 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
1123 UINT32 Ovf_PMC1
: 1;
1125 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
1127 UINT32 Ovf_PMC2
: 1;
1129 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
1131 UINT32 Ovf_PMC3
: 1;
1133 /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
1135 UINT32 Ovf_PMC4
: 1;
1137 /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
1139 UINT32 Ovf_PMC5
: 1;
1141 /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
1143 UINT32 Ovf_PMC6
: 1;
1145 /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
1147 UINT32 Ovf_PMC7
: 1;
1148 UINT32 Reserved1
: 24;
1150 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
1152 UINT32 Ovf_FixedCtr0
: 1;
1154 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
1156 UINT32 Ovf_FixedCtr1
: 1;
1158 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
1160 UINT32 Ovf_FixedCtr2
: 1;
1161 UINT32 Reserved2
: 26;
1163 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
1165 UINT32 Ovf_Uncore
: 1;
1167 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
1169 UINT32 Ovf_BufDSSAVE
: 1;
1171 /// [Bit 63] Thread. Set 1 to clear CondChgd.
1173 UINT32 CondChgd
: 1;
1176 /// All bit fields as a 64-bit value
1179 } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
1182 Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
1184 @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)
1185 @param EAX Lower 32-bits of MSR value.
1186 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
1187 @param EDX Upper 32-bits of MSR value.
1188 Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
1190 <b>Example usage</b>
1192 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr;
1194 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);
1195 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
1197 @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1199 #define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1
1202 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE
1206 /// Individual bit fields
1210 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
1212 UINT32 PEBS_EN_PMC0
: 1;
1214 /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
1216 UINT32 PEBS_EN_PMC1
: 1;
1218 /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
1220 UINT32 PEBS_EN_PMC2
: 1;
1222 /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
1224 UINT32 PEBS_EN_PMC3
: 1;
1225 UINT32 Reserved1
: 28;
1227 /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
1229 UINT32 LL_EN_PMC0
: 1;
1231 /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
1233 UINT32 LL_EN_PMC1
: 1;
1235 /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
1237 UINT32 LL_EN_PMC2
: 1;
1239 /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
1241 UINT32 LL_EN_PMC3
: 1;
1242 UINT32 Reserved2
: 27;
1244 /// [Bit 63] Enable Precise Store. (R/W).
1249 /// All bit fields as a 64-bit value
1252 } MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
;
1255 Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring
1258 @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)
1259 @param EAX Lower 32-bits of MSR value.
1260 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
1261 @param EDX Upper 32-bits of MSR value.
1262 Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
1264 <b>Example usage</b>
1266 MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr;
1268 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);
1269 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);
1271 @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
1273 #define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6
1276 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT
1280 /// Individual bit fields
1284 /// [Bits 15:0] Minimum threshold latency value of tagged load operation
1285 /// that will be counted. (R/W).
1287 UINT32 MinimumThreshold
: 16;
1288 UINT32 Reserved1
: 16;
1289 UINT32 Reserved2
: 32;
1292 /// All bit fields as a 32-bit value
1296 /// All bit fields as a 64-bit value
1299 } MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER
;
1302 Package. Note: C-state values are processor specific C-state code names,
1303 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
1304 Residency Counter. (R/O) Value since last reset that this package is in
1305 processor-specific C3 states. Count at the same frequency as the TSC.
1307 @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)
1308 @param EAX Lower 32-bits of MSR value.
1309 @param EDX Upper 32-bits of MSR value.
1311 <b>Example usage</b>
1315 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);
1316 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);
1318 @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1320 #define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8
1323 Package. Note: C-state values are processor specific C-state code names,
1324 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1325 Residency Counter. (R/O) Value since last reset that this package is in
1326 processor-specific C6 states. Count at the same frequency as the TSC.
1328 @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)
1329 @param EAX Lower 32-bits of MSR value.
1330 @param EDX Upper 32-bits of MSR value.
1332 <b>Example usage</b>
1336 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);
1337 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);
1339 @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1341 #define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9
1344 Package. Note: C-state values are processor specific C-state code names,
1345 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
1346 Residency Counter. (R/O) Value since last reset that this package is in
1347 processor-specific C7 states. Count at the same frequency as the TSC.
1349 @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)
1350 @param EAX Lower 32-bits of MSR value.
1351 @param EDX Upper 32-bits of MSR value.
1353 <b>Example usage</b>
1357 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);
1358 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);
1360 @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1362 #define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA
1365 Core. Note: C-state values are processor specific C-state code names,
1366 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
1367 Residency Counter. (R/O) Value since last reset that this core is in
1368 processor-specific C3 states. Count at the same frequency as the TSC.
1370 @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)
1371 @param EAX Lower 32-bits of MSR value.
1372 @param EDX Upper 32-bits of MSR value.
1374 <b>Example usage</b>
1378 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);
1379 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);
1381 @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
1383 #define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC
1386 Core. Note: C-state values are processor specific C-state code names,
1387 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1388 Residency Counter. (R/O) Value since last reset that this core is in
1389 processor-specific C6 states. Count at the same frequency as the TSC.
1391 @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)
1392 @param EAX Lower 32-bits of MSR value.
1393 @param EDX Upper 32-bits of MSR value.
1395 <b>Example usage</b>
1399 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);
1400 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);
1402 @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1404 #define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD
1407 Core. Note: C-state values are processor specific C-state code names,
1408 unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7
1409 Residency Counter. (R/O) Value since last reset that this core is in
1410 processor-specific C7 states. Count at the same frequency as the TSC.
1412 @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)
1413 @param EAX Lower 32-bits of MSR value.
1414 @param EDX Upper 32-bits of MSR value.
1416 <b>Example usage</b>
1420 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);
1421 AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);
1423 @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.
1425 #define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE
1428 Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
1430 @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410)
1431 @param EAX Lower 32-bits of MSR value.
1432 Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.
1433 @param EDX Upper 32-bits of MSR value.
1434 Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.
1436 <b>Example usage</b>
1438 MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr;
1440 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL);
1441 AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64);
1443 @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
1445 #define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410
1448 MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL
1452 /// Individual bit fields
1456 /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU
1457 /// hardware detected errors.
1459 UINT32 PCUHardwareError
: 1;
1461 /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU
1462 /// controller detected errors.
1464 UINT32 PCUControllerError
: 1;
1466 /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU
1467 /// firmware detected errors.
1469 UINT32 PCUFirmwareError
: 1;
1470 UINT32 Reserved1
: 29;
1471 UINT32 Reserved2
: 32;
1474 /// All bit fields as a 32-bit value
1478 /// All bit fields as a 64-bit value
1481 } MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
;
1484 Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
1486 @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1487 @param EAX Lower 32-bits of MSR value.
1488 @param EDX Upper 32-bits of MSR value.
1490 <b>Example usage</b>
1494 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);
1496 @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1498 #define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1501 Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1504 @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)
1505 @param EAX Lower 32-bits of MSR value.
1506 @param EDX Upper 32-bits of MSR value.
1508 <b>Example usage</b>
1512 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);
1514 @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1516 #define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606
1519 Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are
1520 processor specific C-state code names, unrelated to MWAIT extension C-state
1521 parameters or ACPI CStates.
1523 @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)
1524 @param EAX Lower 32-bits of MSR value.
1525 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
1526 @param EDX Upper 32-bits of MSR value.
1527 Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
1529 <b>Example usage</b>
1531 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr;
1533 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);
1534 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);
1536 @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.
1538 #define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A
1541 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL
1545 /// Individual bit fields
1549 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1550 /// that should be used to decide if the package should be put into a
1551 /// package C3 state.
1553 UINT32 TimeLimit
: 10;
1555 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
1556 /// unit of the interrupt response time limit. The following time unit
1557 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
1558 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
1560 UINT32 TimeUnit
: 3;
1561 UINT32 Reserved1
: 2;
1563 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1564 /// valid and can be used by the processor for package C-sate management.
1567 UINT32 Reserved2
: 16;
1568 UINT32 Reserved3
: 32;
1571 /// All bit fields as a 32-bit value
1575 /// All bit fields as a 64-bit value
1578 } MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER
;
1581 Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the
1582 budget allocated for the package to exit from C6 to a C0 state, where
1583 interrupt request can be delivered to the core and serviced. Additional
1584 core-exit latency amy be applicable depending on the actual C-state the core
1585 is in. Note: C-state values are processor specific C-state code names,
1586 unrelated to MWAIT extension C-state parameters or ACPI CStates.
1588 @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)
1589 @param EAX Lower 32-bits of MSR value.
1590 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
1591 @param EDX Upper 32-bits of MSR value.
1592 Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
1594 <b>Example usage</b>
1596 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr;
1598 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);
1599 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);
1601 @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.
1603 #define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B
1606 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL
1610 /// Individual bit fields
1614 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
1615 /// that should be used to decide if the package should be put into a
1616 /// package C6 state.
1618 UINT32 TimeLimit
: 10;
1620 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
1621 /// unit of the interrupt response time limit. The following time unit
1622 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
1623 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
1625 UINT32 TimeUnit
: 3;
1626 UINT32 Reserved1
: 2;
1628 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
1629 /// valid and can be used by the processor for package C-sate management.
1632 UINT32 Reserved2
: 16;
1633 UINT32 Reserved3
: 32;
1636 /// All bit fields as a 32-bit value
1640 /// All bit fields as a 64-bit value
1643 } MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER
;
1646 Package. Note: C-state values are processor specific C-state code names,
1647 unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
1648 Residency Counter. (R/O) Value since last reset that this package is in
1649 processor-specific C2 states. Count at the same frequency as the TSC.
1651 @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)
1652 @param EAX Lower 32-bits of MSR value.
1653 @param EDX Upper 32-bits of MSR value.
1655 <b>Example usage</b>
1659 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);
1660 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);
1662 @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1664 #define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D
1667 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1670 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)
1671 @param EAX Lower 32-bits of MSR value.
1672 @param EDX Upper 32-bits of MSR value.
1674 <b>Example usage</b>
1678 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);
1679 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);
1681 @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1683 #define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610
1686 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1688 @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)
1689 @param EAX Lower 32-bits of MSR value.
1690 @param EDX Upper 32-bits of MSR value.
1692 <b>Example usage</b>
1696 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);
1698 @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1700 #define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611
1703 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1706 @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)
1707 @param EAX Lower 32-bits of MSR value.
1708 @param EDX Upper 32-bits of MSR value.
1710 <b>Example usage</b>
1714 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);
1715 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);
1717 @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1719 #define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614
1722 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1725 @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)
1726 @param EAX Lower 32-bits of MSR value.
1727 @param EDX Upper 32-bits of MSR value.
1729 <b>Example usage</b>
1733 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);
1734 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);
1736 @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1738 #define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638
1741 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1744 @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
1745 @param EAX Lower 32-bits of MSR value.
1746 @param EDX Upper 32-bits of MSR value.
1748 <b>Example usage</b>
1752 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);
1754 @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1756 #define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639
1759 Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
1760 branch record registers on the last branch record stack. This part of the
1761 stack contains pointers to the source instruction. See also: - Last Branch
1762 Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section
1765 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP
1766 @param EAX Lower 32-bits of MSR value.
1767 @param EDX Upper 32-bits of MSR value.
1769 <b>Example usage</b>
1773 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);
1774 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);
1776 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
1777 MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
1778 MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
1779 MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
1780 MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
1781 MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
1782 MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
1783 MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
1784 MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.
1785 MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.
1786 MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
1787 MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
1788 MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
1789 MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
1790 MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
1791 MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
1794 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680
1795 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681
1796 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682
1797 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683
1798 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684
1799 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685
1800 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686
1801 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687
1802 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688
1803 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689
1804 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A
1805 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B
1806 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C
1807 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D
1808 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E
1809 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F
1813 Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
1814 record registers on the last branch record stack. This part of the stack
1815 contains pointers to the destination instruction.
1817 @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP
1818 @param EAX Lower 32-bits of MSR value.
1819 @param EDX Upper 32-bits of MSR value.
1821 <b>Example usage</b>
1825 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);
1826 AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);
1828 @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
1829 MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
1830 MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
1831 MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
1832 MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
1833 MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
1834 MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
1835 MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
1836 MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.
1837 MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.
1838 MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
1839 MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
1840 MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
1841 MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
1842 MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
1843 MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
1846 #define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0
1847 #define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1
1848 #define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2
1849 #define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3
1850 #define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4
1851 #define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5
1852 #define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6
1853 #define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7
1854 #define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8
1855 #define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9
1856 #define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA
1857 #define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB
1858 #define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC
1859 #define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD
1860 #define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE
1861 #define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF
1865 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
1866 RW if MSR_PLATFORM_INFO.[28] = 1.
1868 @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)
1869 @param EAX Lower 32-bits of MSR value.
1870 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
1871 @param EDX Upper 32-bits of MSR value.
1872 Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
1874 <b>Example usage</b>
1876 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr;
1878 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);
1880 @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
1882 #define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD
1885 MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT
1889 /// Individual bit fields
1893 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
1894 /// limit of 1 core active.
1896 UINT32 Maximum1C
: 8;
1898 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
1899 /// limit of 2 core active.
1901 UINT32 Maximum2C
: 8;
1903 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
1904 /// limit of 3 core active.
1906 UINT32 Maximum3C
: 8;
1908 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
1909 /// limit of 4 core active.
1911 UINT32 Maximum4C
: 8;
1913 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
1914 /// limit of 5 core active.
1916 UINT32 Maximum5C
: 8;
1918 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
1919 /// limit of 6 core active.
1921 UINT32 Maximum6C
: 8;
1923 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
1924 /// limit of 7 core active.
1926 UINT32 Maximum7C
: 8;
1928 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
1929 /// limit of 8 core active.
1931 UINT32 Maximum8C
: 8;
1934 /// All bit fields as a 64-bit value
1937 } MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER
;
1940 Package. Uncore PMU global control.
1942 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)
1943 @param EAX Lower 32-bits of MSR value.
1944 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
1945 @param EDX Upper 32-bits of MSR value.
1946 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
1948 <b>Example usage</b>
1950 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;
1952 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);
1953 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
1955 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
1957 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391
1960 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL
1964 /// Individual bit fields
1968 /// [Bit 0] Slice 0 select.
1970 UINT32 PMI_Sel_Slice0
: 1;
1972 /// [Bit 1] Slice 1 select.
1974 UINT32 PMI_Sel_Slice1
: 1;
1976 /// [Bit 2] Slice 2 select.
1978 UINT32 PMI_Sel_Slice2
: 1;
1980 /// [Bit 3] Slice 3 select.
1982 UINT32 PMI_Sel_Slice3
: 1;
1984 /// [Bit 4] Slice 4 select.
1986 UINT32 PMI_Sel_Slice4
: 1;
1987 UINT32 Reserved1
: 14;
1988 UINT32 Reserved2
: 10;
1990 /// [Bit 29] Enable all uncore counters.
1994 /// [Bit 30] Enable wake on PMI.
1998 /// [Bit 31] Enable Freezing counter when overflow.
2001 UINT32 Reserved3
: 32;
2004 /// All bit fields as a 32-bit value
2008 /// All bit fields as a 64-bit value
2011 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER
;
2014 Package. Uncore PMU main status.
2016 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)
2017 @param EAX Lower 32-bits of MSR value.
2018 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2019 @param EDX Upper 32-bits of MSR value.
2020 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
2022 <b>Example usage</b>
2024 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;
2026 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);
2027 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
2029 @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
2031 #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392
2034 MSR information returned for MSR index
2035 #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS
2039 /// Individual bit fields
2043 /// [Bit 0] Fixed counter overflowed.
2047 /// [Bit 1] An ARB counter overflowed.
2050 UINT32 Reserved1
: 1;
2052 /// [Bit 3] A CBox counter overflowed (on any slice).
2055 UINT32 Reserved2
: 28;
2056 UINT32 Reserved3
: 32;
2059 /// All bit fields as a 32-bit value
2063 /// All bit fields as a 64-bit value
2066 } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER
;
2069 Package. Uncore fixed counter control (R/W).
2071 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)
2072 @param EAX Lower 32-bits of MSR value.
2073 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
2074 @param EDX Upper 32-bits of MSR value.
2075 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
2077 <b>Example usage</b>
2079 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr;
2081 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);
2082 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
2084 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
2086 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394
2089 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL
2093 /// Individual bit fields
2096 UINT32 Reserved1
: 20;
2098 /// [Bit 20] Enable overflow propagation.
2100 UINT32 EnableOverflow
: 1;
2101 UINT32 Reserved2
: 1;
2103 /// [Bit 22] Enable counting.
2105 UINT32 EnableCounting
: 1;
2106 UINT32 Reserved3
: 9;
2107 UINT32 Reserved4
: 32;
2110 /// All bit fields as a 32-bit value
2114 /// All bit fields as a 64-bit value
2117 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER
;
2120 Package. Uncore fixed counter.
2122 @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)
2123 @param EAX Lower 32-bits of MSR value.
2124 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
2125 @param EDX Upper 32-bits of MSR value.
2126 Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
2128 <b>Example usage</b>
2130 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr;
2132 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);
2133 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);
2135 @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
2137 #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395
2140 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR
2144 /// Individual bit fields
2148 /// [Bits 31:0] Current count.
2150 UINT32 CurrentCount
: 32;
2152 /// [Bits 47:32] Current count.
2154 UINT32 CurrentCountHi
: 16;
2155 UINT32 Reserved
: 16;
2158 /// All bit fields as a 64-bit value
2161 } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER
;
2164 Package. Uncore C-Box configuration information (R/O).
2166 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)
2167 @param EAX Lower 32-bits of MSR value.
2168 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
2169 @param EDX Upper 32-bits of MSR value.
2170 Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
2172 <b>Example usage</b>
2174 MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr;
2176 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);
2178 @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
2180 #define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396
2183 MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG
2187 /// Individual bit fields
2191 /// [Bits 3:0] Report the number of C-Box units with performance counters,
2192 /// including processor cores and processor graphics".
2195 UINT32 Reserved1
: 28;
2196 UINT32 Reserved2
: 32;
2199 /// All bit fields as a 32-bit value
2203 /// All bit fields as a 64-bit value
2206 } MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER
;
2209 Package. Uncore Arb unit, performance counter 0.
2211 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)
2212 @param EAX Lower 32-bits of MSR value.
2213 @param EDX Upper 32-bits of MSR value.
2215 <b>Example usage</b>
2219 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);
2220 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);
2222 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
2224 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0
2227 Package. Uncore Arb unit, performance counter 1.
2229 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)
2230 @param EAX Lower 32-bits of MSR value.
2231 @param EDX Upper 32-bits of MSR value.
2233 <b>Example usage</b>
2237 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);
2238 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);
2240 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
2242 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1
2245 Package. Uncore Arb unit, counter 0 event select MSR.
2247 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
2248 @param EAX Lower 32-bits of MSR value.
2249 @param EDX Upper 32-bits of MSR value.
2251 <b>Example usage</b>
2255 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);
2256 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);
2258 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
2260 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2
2263 Package. Uncore Arb unit, counter 1 event select MSR.
2265 @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
2266 @param EAX Lower 32-bits of MSR value.
2267 @param EDX Upper 32-bits of MSR value.
2269 <b>Example usage</b>
2273 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);
2274 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);
2276 @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
2278 #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3
2281 Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the
2282 budget allocated for the package to exit from C7 to a C0 state, where
2283 interrupt request can be delivered to the core and serviced. Additional
2284 core-exit latency amy be applicable depending on the actual C-state the core
2285 is in. Note: C-state values are processor specific C-state code names,
2286 unrelated to MWAIT extension C-state parameters or ACPI CStates.
2288 @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)
2289 @param EAX Lower 32-bits of MSR value.
2290 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
2291 @param EDX Upper 32-bits of MSR value.
2292 Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
2294 <b>Example usage</b>
2296 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr;
2298 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);
2299 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);
2301 @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.
2303 #define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C
2306 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL
2310 /// Individual bit fields
2314 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
2315 /// that should be used to decide if the package should be put into a
2316 /// package C7 state.
2318 UINT32 TimeLimit
: 10;
2320 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time
2321 /// unit of the interrupt response time limit. The following time unit
2322 /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
2323 /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
2325 UINT32 TimeUnit
: 3;
2326 UINT32 Reserved1
: 2;
2328 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are
2329 /// valid and can be used by the processor for package C-sate management.
2332 UINT32 Reserved2
: 16;
2333 UINT32 Reserved3
: 32;
2336 /// All bit fields as a 32-bit value
2340 /// All bit fields as a 64-bit value
2343 } MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
;
2346 Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
2349 @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)
2350 @param EAX Lower 32-bits of MSR value.
2351 @param EDX Upper 32-bits of MSR value.
2353 <b>Example usage</b>
2357 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);
2358 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);
2360 @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.
2362 #define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A
2365 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
2368 @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)
2369 @param EAX Lower 32-bits of MSR value.
2370 @param EDX Upper 32-bits of MSR value.
2372 <b>Example usage</b>
2376 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);
2377 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);
2379 @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
2381 #define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640
2384 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
2387 @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)
2388 @param EAX Lower 32-bits of MSR value.
2389 @param EDX Upper 32-bits of MSR value.
2391 <b>Example usage</b>
2395 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);
2397 @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
2399 #define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641
2402 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
2405 @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)
2406 @param EAX Lower 32-bits of MSR value.
2407 @param EDX Upper 32-bits of MSR value.
2409 <b>Example usage</b>
2413 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);
2414 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);
2416 @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
2418 #define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642
2421 Package. Uncore C-Box 0, counter n event select MSR.
2423 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn
2424 @param EAX Lower 32-bits of MSR value.
2425 @param EDX Upper 32-bits of MSR value.
2427 <b>Example usage</b>
2431 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);
2432 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);
2434 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
2435 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
2436 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM.
2437 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.
2440 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700
2441 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701
2442 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702
2443 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703
2447 Package. Uncore C-Box n, unit status for counter 0-3.
2449 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS
2450 @param EAX Lower 32-bits of MSR value.
2451 @param EDX Upper 32-bits of MSR value.
2453 <b>Example usage</b>
2457 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS);
2458 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr);
2460 @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM.
2461 MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM.
2462 MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM.
2463 MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM.
2464 MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.
2467 #define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705
2468 #define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715
2469 #define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725
2470 #define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735
2471 #define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745
2475 Package. Uncore C-Box 0, performance counter n.
2477 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn
2478 @param EAX Lower 32-bits of MSR value.
2479 @param EDX Upper 32-bits of MSR value.
2481 <b>Example usage</b>
2485 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);
2486 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);
2488 @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
2489 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
2490 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM.
2491 MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.
2494 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706
2495 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707
2496 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708
2497 #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709
2501 Package. Uncore C-Box 1, counter n event select MSR.
2503 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn
2504 @param EAX Lower 32-bits of MSR value.
2505 @param EDX Upper 32-bits of MSR value.
2507 <b>Example usage</b>
2511 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);
2512 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);
2514 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
2515 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
2516 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM.
2517 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.
2520 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710
2521 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711
2522 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712
2523 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713
2527 Package. Uncore C-Box 1, performance counter n.
2529 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn
2530 @param EAX Lower 32-bits of MSR value.
2531 @param EDX Upper 32-bits of MSR value.
2533 <b>Example usage</b>
2537 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);
2538 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);
2540 @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
2541 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
2542 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM.
2543 MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.
2546 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716
2547 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717
2548 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718
2549 #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719
2553 Package. Uncore C-Box 2, counter n event select MSR.
2555 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn
2556 @param EAX Lower 32-bits of MSR value.
2557 @param EDX Upper 32-bits of MSR value.
2559 <b>Example usage</b>
2563 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);
2564 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);
2566 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
2567 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
2568 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM.
2569 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.
2572 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720
2573 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721
2574 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722
2575 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723
2579 Package. Uncore C-Box 2, performance counter n.
2581 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn
2582 @param EAX Lower 32-bits of MSR value.
2583 @param EDX Upper 32-bits of MSR value.
2585 <b>Example usage</b>
2589 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);
2590 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);
2592 @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
2593 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
2594 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM.
2595 MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.
2598 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726
2599 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727
2600 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728
2601 #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729
2605 Package. Uncore C-Box 3, counter n event select MSR.
2607 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn
2608 @param EAX Lower 32-bits of MSR value.
2609 @param EDX Upper 32-bits of MSR value.
2611 <b>Example usage</b>
2615 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);
2616 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);
2618 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
2619 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
2620 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM.
2621 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.
2624 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730
2625 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731
2626 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732
2627 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733
2631 Package. Uncore C-Box 3, performance counter n.
2633 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn
2634 @param EAX Lower 32-bits of MSR value.
2635 @param EDX Upper 32-bits of MSR value.
2637 <b>Example usage</b>
2641 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);
2642 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);
2644 @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
2645 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
2646 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM.
2647 MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.
2650 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736
2651 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737
2652 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738
2653 #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739
2657 Package. Uncore C-Box 4, counter n event select MSR.
2659 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn
2660 @param EAX Lower 32-bits of MSR value.
2661 @param EDX Upper 32-bits of MSR value.
2663 <b>Example usage</b>
2667 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0);
2668 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr);
2670 @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM.
2671 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM.
2672 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM.
2673 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.
2676 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740
2677 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741
2678 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742
2679 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743
2683 Package. Uncore C-Box 4, performance counter n.
2685 @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn
2686 @param EAX Lower 32-bits of MSR value.
2687 @param EDX Upper 32-bits of MSR value.
2689 <b>Example usage</b>
2693 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0);
2694 AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr);
2696 @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM.
2697 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM.
2698 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM.
2699 MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.
2702 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746
2703 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747
2704 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748
2705 #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749
2709 Package. MC Bank Error Configuration (R/W).
2711 @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)
2712 @param EAX Lower 32-bits of MSR value.
2713 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
2714 @param EDX Upper 32-bits of MSR value.
2715 Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
2717 <b>Example usage</b>
2719 MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr;
2721 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);
2722 AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
2724 @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
2726 #define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F
2729 MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL
2733 /// Individual bit fields
2736 UINT32 Reserved1
: 1;
2738 /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank
2739 /// to log additional info in bits 36:32.
2741 UINT32 MemErrorLogEnable
: 1;
2742 UINT32 Reserved2
: 30;
2743 UINT32 Reserved3
: 32;
2746 /// All bit fields as a 32-bit value
2750 /// All bit fields as a 64-bit value
2753 } MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER
;
2758 @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)
2759 @param EAX Lower 32-bits of MSR value.
2760 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
2761 @param EDX Upper 32-bits of MSR value.
2762 Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
2764 <b>Example usage</b>
2766 MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr;
2768 Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);
2769 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);
2771 @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.
2773 #define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C
2776 MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT
2780 /// Individual bit fields
2784 /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS
2785 /// counting logic for specific events requiring additional configuration,
2786 /// see Table 19-17.
2788 UINT32 ENABLE_PEBS_NUM_ALT
: 1;
2789 UINT32 Reserved1
: 31;
2790 UINT32 Reserved2
: 32;
2793 /// All bit fields as a 32-bit value
2797 /// All bit fields as a 64-bit value
2800 } MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER
;
2803 Package. Package RAPL Perf Status (R/O).
2805 @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)
2806 @param EAX Lower 32-bits of MSR value.
2807 @param EDX Upper 32-bits of MSR value.
2809 <b>Example usage</b>
2813 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);
2815 @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
2817 #define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613
2820 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
2823 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
2824 @param EAX Lower 32-bits of MSR value.
2825 @param EDX Upper 32-bits of MSR value.
2827 <b>Example usage</b>
2831 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);
2832 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);
2834 @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
2836 #define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618
2839 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
2841 @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
2842 @param EAX Lower 32-bits of MSR value.
2843 @param EDX Upper 32-bits of MSR value.
2845 <b>Example usage</b>
2849 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);
2851 @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
2853 #define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619
2856 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
2859 @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
2860 @param EAX Lower 32-bits of MSR value.
2861 @param EDX Upper 32-bits of MSR value.
2863 <b>Example usage</b>
2867 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);
2869 @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
2871 #define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B
2874 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
2876 @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
2877 @param EAX Lower 32-bits of MSR value.
2878 @param EDX Upper 32-bits of MSR value.
2880 <b>Example usage</b>
2884 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);
2885 AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);
2887 @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
2889 #define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C
2892 Package. Uncore U-box UCLK fixed counter control.
2894 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)
2895 @param EAX Lower 32-bits of MSR value.
2896 @param EDX Upper 32-bits of MSR value.
2898 <b>Example usage</b>
2902 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);
2903 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);
2905 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
2907 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08
2910 Package. Uncore U-box UCLK fixed counter.
2912 @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)
2913 @param EAX Lower 32-bits of MSR value.
2914 @param EDX Upper 32-bits of MSR value.
2916 <b>Example usage</b>
2920 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);
2921 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);
2923 @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
2925 #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09
2928 Package. Uncore U-box perfmon event select for U-box counter 0.
2930 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)
2931 @param EAX Lower 32-bits of MSR value.
2932 @param EDX Upper 32-bits of MSR value.
2934 <b>Example usage</b>
2938 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);
2939 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);
2941 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
2943 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10
2946 Package. Uncore U-box perfmon event select for U-box counter 1.
2948 @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)
2949 @param EAX Lower 32-bits of MSR value.
2950 @param EDX Upper 32-bits of MSR value.
2952 <b>Example usage</b>
2956 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);
2957 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);
2959 @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
2961 #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11
2964 Package. Uncore U-box perfmon counter 0.
2966 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)
2967 @param EAX Lower 32-bits of MSR value.
2968 @param EDX Upper 32-bits of MSR value.
2970 <b>Example usage</b>
2974 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);
2975 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);
2977 @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
2979 #define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16
2982 Package. Uncore U-box perfmon counter 1.
2984 @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)
2985 @param EAX Lower 32-bits of MSR value.
2986 @param EDX Upper 32-bits of MSR value.
2988 <b>Example usage</b>
2992 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);
2993 AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);
2995 @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
2997 #define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17
3000 Package. Uncore PCU perfmon for PCU-box-wide control.
3002 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)
3003 @param EAX Lower 32-bits of MSR value.
3004 @param EDX Upper 32-bits of MSR value.
3006 <b>Example usage</b>
3010 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);
3011 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);
3013 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
3015 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24
3018 Package. Uncore PCU perfmon event select for PCU counter 0.
3020 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)
3021 @param EAX Lower 32-bits of MSR value.
3022 @param EDX Upper 32-bits of MSR value.
3024 <b>Example usage</b>
3028 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);
3029 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);
3031 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
3033 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30
3036 Package. Uncore PCU perfmon event select for PCU counter 1.
3038 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)
3039 @param EAX Lower 32-bits of MSR value.
3040 @param EDX Upper 32-bits of MSR value.
3042 <b>Example usage</b>
3046 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);
3047 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);
3049 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
3051 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31
3054 Package. Uncore PCU perfmon event select for PCU counter 2.
3056 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)
3057 @param EAX Lower 32-bits of MSR value.
3058 @param EDX Upper 32-bits of MSR value.
3060 <b>Example usage</b>
3064 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);
3065 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);
3067 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
3069 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32
3072 Package. Uncore PCU perfmon event select for PCU counter 3.
3074 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)
3075 @param EAX Lower 32-bits of MSR value.
3076 @param EDX Upper 32-bits of MSR value.
3078 <b>Example usage</b>
3082 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);
3083 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);
3085 @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
3087 #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33
3090 Package. Uncore PCU perfmon box-wide filter.
3092 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)
3093 @param EAX Lower 32-bits of MSR value.
3094 @param EDX Upper 32-bits of MSR value.
3096 <b>Example usage</b>
3100 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);
3101 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);
3103 @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
3105 #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34
3108 Package. Uncore PCU perfmon counter 0.
3110 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)
3111 @param EAX Lower 32-bits of MSR value.
3112 @param EDX Upper 32-bits of MSR value.
3114 <b>Example usage</b>
3118 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);
3119 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);
3121 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
3123 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36
3126 Package. Uncore PCU perfmon counter 1.
3128 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)
3129 @param EAX Lower 32-bits of MSR value.
3130 @param EDX Upper 32-bits of MSR value.
3132 <b>Example usage</b>
3136 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);
3137 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);
3139 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
3141 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37
3144 Package. Uncore PCU perfmon counter 2.
3146 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)
3147 @param EAX Lower 32-bits of MSR value.
3148 @param EDX Upper 32-bits of MSR value.
3150 <b>Example usage</b>
3154 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);
3155 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);
3157 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
3159 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38
3162 Package. Uncore PCU perfmon counter 3.
3164 @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)
3165 @param EAX Lower 32-bits of MSR value.
3166 @param EDX Upper 32-bits of MSR value.
3168 <b>Example usage</b>
3172 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);
3173 AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);
3175 @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
3177 #define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39
3180 Package. Uncore C-box 0 perfmon local box wide control.
3182 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)
3183 @param EAX Lower 32-bits of MSR value.
3184 @param EDX Upper 32-bits of MSR value.
3186 <b>Example usage</b>
3190 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);
3191 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);
3193 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
3195 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04
3198 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
3200 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)
3201 @param EAX Lower 32-bits of MSR value.
3202 @param EDX Upper 32-bits of MSR value.
3204 <b>Example usage</b>
3208 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);
3209 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);
3211 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
3213 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10
3216 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
3218 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)
3219 @param EAX Lower 32-bits of MSR value.
3220 @param EDX Upper 32-bits of MSR value.
3222 <b>Example usage</b>
3226 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);
3227 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);
3229 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
3231 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11
3234 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
3236 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)
3237 @param EAX Lower 32-bits of MSR value.
3238 @param EDX Upper 32-bits of MSR value.
3240 <b>Example usage</b>
3244 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);
3245 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);
3247 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
3249 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12
3252 Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
3254 @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)
3255 @param EAX Lower 32-bits of MSR value.
3256 @param EDX Upper 32-bits of MSR value.
3258 <b>Example usage</b>
3262 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);
3263 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);
3265 @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
3267 #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13
3270 Package. Uncore C-box 0 perfmon box wide filter.
3272 @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)
3273 @param EAX Lower 32-bits of MSR value.
3274 @param EDX Upper 32-bits of MSR value.
3276 <b>Example usage</b>
3280 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);
3281 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);
3283 @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.
3285 #define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14
3288 Package. Uncore C-box 0 perfmon counter 0.
3290 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)
3291 @param EAX Lower 32-bits of MSR value.
3292 @param EDX Upper 32-bits of MSR value.
3294 <b>Example usage</b>
3298 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);
3299 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);
3301 @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
3303 #define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16
3306 Package. Uncore C-box 0 perfmon counter 1.
3308 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)
3309 @param EAX Lower 32-bits of MSR value.
3310 @param EDX Upper 32-bits of MSR value.
3312 <b>Example usage</b>
3316 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);
3317 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);
3319 @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
3321 #define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17
3324 Package. Uncore C-box 0 perfmon counter 2.
3326 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)
3327 @param EAX Lower 32-bits of MSR value.
3328 @param EDX Upper 32-bits of MSR value.
3330 <b>Example usage</b>
3334 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);
3335 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);
3337 @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
3339 #define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18
3342 Package. Uncore C-box 0 perfmon counter 3.
3344 @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)
3345 @param EAX Lower 32-bits of MSR value.
3346 @param EDX Upper 32-bits of MSR value.
3348 <b>Example usage</b>
3352 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);
3353 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);
3355 @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
3357 #define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19
3360 Package. Uncore C-box 1 perfmon local box wide control.
3362 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)
3363 @param EAX Lower 32-bits of MSR value.
3364 @param EDX Upper 32-bits of MSR value.
3366 <b>Example usage</b>
3370 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);
3371 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);
3373 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
3375 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24
3378 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
3380 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)
3381 @param EAX Lower 32-bits of MSR value.
3382 @param EDX Upper 32-bits of MSR value.
3384 <b>Example usage</b>
3388 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);
3389 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);
3391 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
3393 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30
3396 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
3398 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)
3399 @param EAX Lower 32-bits of MSR value.
3400 @param EDX Upper 32-bits of MSR value.
3402 <b>Example usage</b>
3406 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);
3407 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);
3409 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
3411 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31
3414 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
3416 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)
3417 @param EAX Lower 32-bits of MSR value.
3418 @param EDX Upper 32-bits of MSR value.
3420 <b>Example usage</b>
3424 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);
3425 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);
3427 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
3429 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32
3432 Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
3434 @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)
3435 @param EAX Lower 32-bits of MSR value.
3436 @param EDX Upper 32-bits of MSR value.
3438 <b>Example usage</b>
3442 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);
3443 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);
3445 @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
3447 #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33
3450 Package. Uncore C-box 1 perfmon box wide filter.
3452 @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)
3453 @param EAX Lower 32-bits of MSR value.
3454 @param EDX Upper 32-bits of MSR value.
3456 <b>Example usage</b>
3460 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);
3461 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);
3463 @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.
3465 #define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34
3468 Package. Uncore C-box 1 perfmon counter 0.
3470 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)
3471 @param EAX Lower 32-bits of MSR value.
3472 @param EDX Upper 32-bits of MSR value.
3474 <b>Example usage</b>
3478 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);
3479 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);
3481 @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
3483 #define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36
3486 Package. Uncore C-box 1 perfmon counter 1.
3488 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)
3489 @param EAX Lower 32-bits of MSR value.
3490 @param EDX Upper 32-bits of MSR value.
3492 <b>Example usage</b>
3496 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);
3497 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);
3499 @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
3501 #define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37
3504 Package. Uncore C-box 1 perfmon counter 2.
3506 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)
3507 @param EAX Lower 32-bits of MSR value.
3508 @param EDX Upper 32-bits of MSR value.
3510 <b>Example usage</b>
3514 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);
3515 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);
3517 @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
3519 #define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38
3522 Package. Uncore C-box 1 perfmon counter 3.
3524 @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)
3525 @param EAX Lower 32-bits of MSR value.
3526 @param EDX Upper 32-bits of MSR value.
3528 <b>Example usage</b>
3532 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);
3533 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);
3535 @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
3537 #define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39
3540 Package. Uncore C-box 2 perfmon local box wide control.
3542 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)
3543 @param EAX Lower 32-bits of MSR value.
3544 @param EDX Upper 32-bits of MSR value.
3546 <b>Example usage</b>
3550 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);
3551 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);
3553 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
3555 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44
3558 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
3560 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)
3561 @param EAX Lower 32-bits of MSR value.
3562 @param EDX Upper 32-bits of MSR value.
3564 <b>Example usage</b>
3568 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);
3569 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);
3571 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
3573 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50
3576 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
3578 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)
3579 @param EAX Lower 32-bits of MSR value.
3580 @param EDX Upper 32-bits of MSR value.
3582 <b>Example usage</b>
3586 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);
3587 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);
3589 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
3591 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51
3594 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
3596 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)
3597 @param EAX Lower 32-bits of MSR value.
3598 @param EDX Upper 32-bits of MSR value.
3600 <b>Example usage</b>
3604 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);
3605 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);
3607 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
3609 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52
3612 Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
3614 @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)
3615 @param EAX Lower 32-bits of MSR value.
3616 @param EDX Upper 32-bits of MSR value.
3618 <b>Example usage</b>
3622 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);
3623 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);
3625 @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
3627 #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53
3630 Package. Uncore C-box 2 perfmon box wide filter.
3632 @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)
3633 @param EAX Lower 32-bits of MSR value.
3634 @param EDX Upper 32-bits of MSR value.
3636 <b>Example usage</b>
3640 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);
3641 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);
3643 @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.
3645 #define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54
3648 Package. Uncore C-box 2 perfmon counter 0.
3650 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)
3651 @param EAX Lower 32-bits of MSR value.
3652 @param EDX Upper 32-bits of MSR value.
3654 <b>Example usage</b>
3658 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);
3659 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);
3661 @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
3663 #define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56
3666 Package. Uncore C-box 2 perfmon counter 1.
3668 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)
3669 @param EAX Lower 32-bits of MSR value.
3670 @param EDX Upper 32-bits of MSR value.
3672 <b>Example usage</b>
3676 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);
3677 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);
3679 @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
3681 #define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57
3684 Package. Uncore C-box 2 perfmon counter 2.
3686 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)
3687 @param EAX Lower 32-bits of MSR value.
3688 @param EDX Upper 32-bits of MSR value.
3690 <b>Example usage</b>
3694 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);
3695 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);
3697 @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
3699 #define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58
3702 Package. Uncore C-box 2 perfmon counter 3.
3704 @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)
3705 @param EAX Lower 32-bits of MSR value.
3706 @param EDX Upper 32-bits of MSR value.
3708 <b>Example usage</b>
3712 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);
3713 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);
3715 @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
3717 #define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59
3720 Package. Uncore C-box 3 perfmon local box wide control.
3722 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)
3723 @param EAX Lower 32-bits of MSR value.
3724 @param EDX Upper 32-bits of MSR value.
3726 <b>Example usage</b>
3730 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);
3731 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);
3733 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
3735 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64
3738 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
3740 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)
3741 @param EAX Lower 32-bits of MSR value.
3742 @param EDX Upper 32-bits of MSR value.
3744 <b>Example usage</b>
3748 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);
3749 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);
3751 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
3753 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70
3756 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
3758 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)
3759 @param EAX Lower 32-bits of MSR value.
3760 @param EDX Upper 32-bits of MSR value.
3762 <b>Example usage</b>
3766 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);
3767 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);
3769 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
3771 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71
3774 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
3776 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)
3777 @param EAX Lower 32-bits of MSR value.
3778 @param EDX Upper 32-bits of MSR value.
3780 <b>Example usage</b>
3784 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);
3785 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);
3787 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
3789 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72
3792 Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
3794 @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)
3795 @param EAX Lower 32-bits of MSR value.
3796 @param EDX Upper 32-bits of MSR value.
3798 <b>Example usage</b>
3802 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);
3803 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);
3805 @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
3807 #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73
3810 Package. Uncore C-box 3 perfmon box wide filter.
3812 @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)
3813 @param EAX Lower 32-bits of MSR value.
3814 @param EDX Upper 32-bits of MSR value.
3816 <b>Example usage</b>
3820 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);
3821 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);
3823 @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.
3825 #define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74
3828 Package. Uncore C-box 3 perfmon counter 0.
3830 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)
3831 @param EAX Lower 32-bits of MSR value.
3832 @param EDX Upper 32-bits of MSR value.
3834 <b>Example usage</b>
3838 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);
3839 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);
3841 @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
3843 #define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76
3846 Package. Uncore C-box 3 perfmon counter 1.
3848 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)
3849 @param EAX Lower 32-bits of MSR value.
3850 @param EDX Upper 32-bits of MSR value.
3852 <b>Example usage</b>
3856 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);
3857 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);
3859 @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
3861 #define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77
3864 Package. Uncore C-box 3 perfmon counter 2.
3866 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)
3867 @param EAX Lower 32-bits of MSR value.
3868 @param EDX Upper 32-bits of MSR value.
3870 <b>Example usage</b>
3874 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);
3875 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);
3877 @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
3879 #define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78
3882 Package. Uncore C-box 3 perfmon counter 3.
3884 @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)
3885 @param EAX Lower 32-bits of MSR value.
3886 @param EDX Upper 32-bits of MSR value.
3888 <b>Example usage</b>
3892 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);
3893 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);
3895 @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
3897 #define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79
3900 Package. Uncore C-box 4 perfmon local box wide control.
3902 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)
3903 @param EAX Lower 32-bits of MSR value.
3904 @param EDX Upper 32-bits of MSR value.
3906 <b>Example usage</b>
3910 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);
3911 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);
3913 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
3915 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84
3918 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
3920 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)
3921 @param EAX Lower 32-bits of MSR value.
3922 @param EDX Upper 32-bits of MSR value.
3924 <b>Example usage</b>
3928 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);
3929 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);
3931 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
3933 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90
3936 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
3938 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)
3939 @param EAX Lower 32-bits of MSR value.
3940 @param EDX Upper 32-bits of MSR value.
3942 <b>Example usage</b>
3946 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);
3947 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);
3949 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
3951 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91
3954 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
3956 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)
3957 @param EAX Lower 32-bits of MSR value.
3958 @param EDX Upper 32-bits of MSR value.
3960 <b>Example usage</b>
3964 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);
3965 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);
3967 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
3969 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92
3972 Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
3974 @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)
3975 @param EAX Lower 32-bits of MSR value.
3976 @param EDX Upper 32-bits of MSR value.
3978 <b>Example usage</b>
3982 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);
3983 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);
3985 @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
3987 #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93
3990 Package. Uncore C-box 4 perfmon box wide filter.
3992 @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)
3993 @param EAX Lower 32-bits of MSR value.
3994 @param EDX Upper 32-bits of MSR value.
3996 <b>Example usage</b>
4000 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);
4001 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);
4003 @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.
4005 #define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94
4008 Package. Uncore C-box 4 perfmon counter 0.
4010 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)
4011 @param EAX Lower 32-bits of MSR value.
4012 @param EDX Upper 32-bits of MSR value.
4014 <b>Example usage</b>
4018 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);
4019 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);
4021 @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
4023 #define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96
4026 Package. Uncore C-box 4 perfmon counter 1.
4028 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)
4029 @param EAX Lower 32-bits of MSR value.
4030 @param EDX Upper 32-bits of MSR value.
4032 <b>Example usage</b>
4036 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);
4037 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);
4039 @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
4041 #define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97
4044 Package. Uncore C-box 4 perfmon counter 2.
4046 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)
4047 @param EAX Lower 32-bits of MSR value.
4048 @param EDX Upper 32-bits of MSR value.
4050 <b>Example usage</b>
4054 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);
4055 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);
4057 @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
4059 #define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98
4062 Package. Uncore C-box 4 perfmon counter 3.
4064 @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)
4065 @param EAX Lower 32-bits of MSR value.
4066 @param EDX Upper 32-bits of MSR value.
4068 <b>Example usage</b>
4072 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);
4073 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);
4075 @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
4077 #define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99
4080 Package. Uncore C-box 5 perfmon local box wide control.
4082 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)
4083 @param EAX Lower 32-bits of MSR value.
4084 @param EDX Upper 32-bits of MSR value.
4086 <b>Example usage</b>
4090 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);
4091 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);
4093 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
4095 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4
4098 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
4100 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)
4101 @param EAX Lower 32-bits of MSR value.
4102 @param EDX Upper 32-bits of MSR value.
4104 <b>Example usage</b>
4108 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);
4109 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);
4111 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
4113 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0
4116 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
4118 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)
4119 @param EAX Lower 32-bits of MSR value.
4120 @param EDX Upper 32-bits of MSR value.
4122 <b>Example usage</b>
4126 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);
4127 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);
4129 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
4131 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1
4134 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
4136 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)
4137 @param EAX Lower 32-bits of MSR value.
4138 @param EDX Upper 32-bits of MSR value.
4140 <b>Example usage</b>
4144 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);
4145 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);
4147 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
4149 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2
4152 Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
4154 @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)
4155 @param EAX Lower 32-bits of MSR value.
4156 @param EDX Upper 32-bits of MSR value.
4158 <b>Example usage</b>
4162 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);
4163 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);
4165 @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
4167 #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3
4170 Package. Uncore C-box 5 perfmon box wide filter.
4172 @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)
4173 @param EAX Lower 32-bits of MSR value.
4174 @param EDX Upper 32-bits of MSR value.
4176 <b>Example usage</b>
4180 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);
4181 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);
4183 @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.
4185 #define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4
4188 Package. Uncore C-box 5 perfmon counter 0.
4190 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)
4191 @param EAX Lower 32-bits of MSR value.
4192 @param EDX Upper 32-bits of MSR value.
4194 <b>Example usage</b>
4198 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);
4199 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);
4201 @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
4203 #define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6
4206 Package. Uncore C-box 5 perfmon counter 1.
4208 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)
4209 @param EAX Lower 32-bits of MSR value.
4210 @param EDX Upper 32-bits of MSR value.
4212 <b>Example usage</b>
4216 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);
4217 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);
4219 @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
4221 #define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7
4224 Package. Uncore C-box 5 perfmon counter 2.
4226 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)
4227 @param EAX Lower 32-bits of MSR value.
4228 @param EDX Upper 32-bits of MSR value.
4230 <b>Example usage</b>
4234 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);
4235 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);
4237 @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
4239 #define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8
4242 Package. Uncore C-box 5 perfmon counter 3.
4244 @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)
4245 @param EAX Lower 32-bits of MSR value.
4246 @param EDX Upper 32-bits of MSR value.
4248 <b>Example usage</b>
4252 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);
4253 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);
4255 @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
4257 #define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9
4260 Package. Uncore C-box 6 perfmon local box wide control.
4262 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)
4263 @param EAX Lower 32-bits of MSR value.
4264 @param EDX Upper 32-bits of MSR value.
4266 <b>Example usage</b>
4270 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);
4271 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);
4273 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
4275 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4
4278 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
4280 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)
4281 @param EAX Lower 32-bits of MSR value.
4282 @param EDX Upper 32-bits of MSR value.
4284 <b>Example usage</b>
4288 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);
4289 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);
4291 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
4293 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0
4296 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
4298 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)
4299 @param EAX Lower 32-bits of MSR value.
4300 @param EDX Upper 32-bits of MSR value.
4302 <b>Example usage</b>
4306 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);
4307 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);
4309 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
4311 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1
4314 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
4316 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)
4317 @param EAX Lower 32-bits of MSR value.
4318 @param EDX Upper 32-bits of MSR value.
4320 <b>Example usage</b>
4324 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);
4325 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);
4327 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
4329 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2
4332 Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
4334 @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)
4335 @param EAX Lower 32-bits of MSR value.
4336 @param EDX Upper 32-bits of MSR value.
4338 <b>Example usage</b>
4342 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);
4343 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);
4345 @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
4347 #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3
4350 Package. Uncore C-box 6 perfmon box wide filter.
4352 @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)
4353 @param EAX Lower 32-bits of MSR value.
4354 @param EDX Upper 32-bits of MSR value.
4356 <b>Example usage</b>
4360 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);
4361 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);
4363 @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.
4365 #define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4
4368 Package. Uncore C-box 6 perfmon counter 0.
4370 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)
4371 @param EAX Lower 32-bits of MSR value.
4372 @param EDX Upper 32-bits of MSR value.
4374 <b>Example usage</b>
4378 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);
4379 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);
4381 @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
4383 #define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6
4386 Package. Uncore C-box 6 perfmon counter 1.
4388 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)
4389 @param EAX Lower 32-bits of MSR value.
4390 @param EDX Upper 32-bits of MSR value.
4392 <b>Example usage</b>
4396 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);
4397 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);
4399 @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
4401 #define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7
4404 Package. Uncore C-box 6 perfmon counter 2.
4406 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)
4407 @param EAX Lower 32-bits of MSR value.
4408 @param EDX Upper 32-bits of MSR value.
4410 <b>Example usage</b>
4414 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);
4415 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);
4417 @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
4419 #define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8
4422 Package. Uncore C-box 6 perfmon counter 3.
4424 @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)
4425 @param EAX Lower 32-bits of MSR value.
4426 @param EDX Upper 32-bits of MSR value.
4428 <b>Example usage</b>
4432 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);
4433 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);
4435 @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
4437 #define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9
4440 Package. Uncore C-box 7 perfmon local box wide control.
4442 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)
4443 @param EAX Lower 32-bits of MSR value.
4444 @param EDX Upper 32-bits of MSR value.
4446 <b>Example usage</b>
4450 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);
4451 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);
4453 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
4455 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4
4458 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
4460 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)
4461 @param EAX Lower 32-bits of MSR value.
4462 @param EDX Upper 32-bits of MSR value.
4464 <b>Example usage</b>
4468 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);
4469 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);
4471 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
4473 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0
4476 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
4478 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)
4479 @param EAX Lower 32-bits of MSR value.
4480 @param EDX Upper 32-bits of MSR value.
4482 <b>Example usage</b>
4486 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);
4487 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);
4489 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
4491 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1
4494 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
4496 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)
4497 @param EAX Lower 32-bits of MSR value.
4498 @param EDX Upper 32-bits of MSR value.
4500 <b>Example usage</b>
4504 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);
4505 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);
4507 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
4509 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2
4512 Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
4514 @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)
4515 @param EAX Lower 32-bits of MSR value.
4516 @param EDX Upper 32-bits of MSR value.
4518 <b>Example usage</b>
4522 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);
4523 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);
4525 @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
4527 #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3
4530 Package. Uncore C-box 7 perfmon box wide filter.
4532 @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)
4533 @param EAX Lower 32-bits of MSR value.
4534 @param EDX Upper 32-bits of MSR value.
4536 <b>Example usage</b>
4540 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);
4541 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);
4543 @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.
4545 #define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4
4548 Package. Uncore C-box 7 perfmon counter 0.
4550 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)
4551 @param EAX Lower 32-bits of MSR value.
4552 @param EDX Upper 32-bits of MSR value.
4554 <b>Example usage</b>
4558 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);
4559 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);
4561 @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
4563 #define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6
4566 Package. Uncore C-box 7 perfmon counter 1.
4568 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)
4569 @param EAX Lower 32-bits of MSR value.
4570 @param EDX Upper 32-bits of MSR value.
4572 <b>Example usage</b>
4576 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);
4577 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);
4579 @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
4581 #define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7
4584 Package. Uncore C-box 7 perfmon counter 2.
4586 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)
4587 @param EAX Lower 32-bits of MSR value.
4588 @param EDX Upper 32-bits of MSR value.
4590 <b>Example usage</b>
4594 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);
4595 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);
4597 @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
4599 #define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8
4602 Package. Uncore C-box 7 perfmon counter 3.
4604 @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)
4605 @param EAX Lower 32-bits of MSR value.
4606 @param EDX Upper 32-bits of MSR value.
4608 <b>Example usage</b>
4612 Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);
4613 AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);
4615 @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
4617 #define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9