MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h

   1 /** @file
   2   MSR Definitions for Intel processors based on the Silvermont microarchitecture.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __SILVERMONT_MSR_H__
  19 #define __SILVERMONT_MSR_H__
  20
  21 #include <Register/Intel/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Intel processors based on the Silvermont microarchitecture?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x06 && \
  34    (                        \
  35     DisplayModel == 0x37 || \
  36     DisplayModel == 0x4A || \
  37     DisplayModel == 0x4D || \
  38     DisplayModel == 0x5A || \
  39     DisplayModel == 0x5D    \
  40     )                       \
  41    )
  42
  43 /**
  44   Module. Model Specific Platform ID (R).
  45
  46   @param  ECX  MSR_SILVERMONT_PLATFORM_ID (0x00000017)
  47   @param  EAX  Lower 32-bits of MSR value.
  48                Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
  49   @param  EDX  Upper 32-bits of MSR value.
  50                Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
  51
  52   <b>Example usage</b>
  53   @code
  54   MSR_SILVERMONT_PLATFORM_ID_REGISTER  Msr;
  55
  56   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);
  57   @endcode
  58   @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
  59 **/
  60 #define MSR_SILVERMONT_PLATFORM_ID  0x00000017
  61
  62 /**
  63   MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID
  64 **/
  65 typedef union {
  66   ///
  67   /// Individual bit fields
  68   ///
  69   struct {
  70     UINT32    Reserved1             : 8;
  71     ///
  72     /// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
  73     ///
  74     UINT32    MaximumQualifiedRatio : 5;
  75     UINT32    Reserved2             : 19;
  76     UINT32    Reserved3             : 18;
  77     ///
  78     /// [Bits 52:50] See Table 2-2.
  79     ///
  80     UINT32    PlatformId            : 3;
  81     UINT32    Reserved4             : 11;
  82   } Bits;
  83   ///
  84   /// All bit fields as a 64-bit value
  85   ///
  86   UINT64    Uint64;
  87 } MSR_SILVERMONT_PLATFORM_ID_REGISTER;
  88
  89 /**
  90   Module. Processor Hard Power-On Configuration (R/W) Writes ignored.
  91
  92   @param  ECX  MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)
  93   @param  EAX  Lower 32-bits of MSR value.
  94                Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
  95   @param  EDX  Upper 32-bits of MSR value.
  96                Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
  97
  98   <b>Example usage</b>
  99   @code
 100   MSR_SILVERMONT_EBL_CR_POWERON_REGISTER  Msr;
 101
 102   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);
 103   AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);
 104   @endcode
 105   @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
 106 **/
 107 #define MSR_SILVERMONT_EBL_CR_POWERON  0x0000002A
 108
 109 /**
 110   MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON
 111 **/
 112 typedef union {
 113   ///
 114   /// Individual bit fields
 115   ///
 116   struct {
 117     UINT32    Reserved1 : 32;
 118     UINT32    Reserved2 : 32;
 119   } Bits;
 120   ///
 121   /// All bit fields as a 32-bit value
 122   ///
 123   UINT32    Uint32;
 124   ///
 125   /// All bit fields as a 64-bit value
 126   ///
 127   UINT64    Uint64;
 128 } MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;
 129
 130 /**
 131   Core. SMI Counter (R/O).
 132
 133   @param  ECX  MSR_SILVERMONT_SMI_COUNT (0x00000034)
 134   @param  EAX  Lower 32-bits of MSR value.
 135                Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
 136   @param  EDX  Upper 32-bits of MSR value.
 137                Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
 138
 139   <b>Example usage</b>
 140   @code
 141   MSR_SILVERMONT_SMI_COUNT_REGISTER  Msr;
 142
 143   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);
 144   @endcode
 145   @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
 146 **/
 147 #define MSR_SILVERMONT_SMI_COUNT  0x00000034
 148
 149 /**
 150   MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT
 151 **/
 152 typedef union {
 153   ///
 154   /// Individual bit fields
 155   ///
 156   struct {
 157     ///
 158     /// [Bits 31:0] SMI Count (R/O)  Running count of SMI events since last
 159     /// RESET.
 160     ///
 161     UINT32    SMICount : 32;
 162     UINT32    Reserved : 32;
 163   } Bits;
 164   ///
 165   /// All bit fields as a 32-bit value
 166   ///
 167   UINT32    Uint32;
 168   ///
 169   /// All bit fields as a 64-bit value
 170   ///
 171   UINT64    Uint64;
 172 } MSR_SILVERMONT_SMI_COUNT_REGISTER;
 173
 174 /**
 175   Core. Control Features in Intel 64 Processor (R/W). See Table 2-2.
 176
 177   @param  ECX  MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)
 178   @param  EAX  Lower 32-bits of MSR value.
 179                Described by the type
 180                MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.
 181   @param  EDX  Upper 32-bits of MSR value.
 182                Described by the type
 183                MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.
 184
 185   <b>Example usage</b>
 186   @code
 187   MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER  Msr;
 188
 189   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL);
 190   AsmWriteMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL, Msr.Uint64);
 191   @endcode
 192   @note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
 193 **/
 194 #define MSR_SILVERMONT_IA32_FEATURE_CONTROL  0x0000003A
 195
 196 /**
 197   MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL
 198 **/
 199 typedef union {
 200   ///
 201   /// Individual bit fields
 202   ///
 203   struct {
 204     ///
 205     /// [Bit 0] Lock (R/WL).
 206     ///
 207     UINT32    Lock                : 1;
 208     UINT32    Reserved1           : 1;
 209     ///
 210     /// [Bit 2] Enable VMX outside SMX operation (R/WL).
 211     ///
 212     UINT32    EnableVmxOutsideSmx : 1;
 213     UINT32    Reserved2           : 29;
 214     UINT32    Reserved3           : 32;
 215   } Bits;
 216   ///
 217   /// All bit fields as a 32-bit value
 218   ///
 219   UINT32    Uint32;
 220   ///
 221   /// All bit fields as a 64-bit value
 222   ///
 223   UINT64    Uint64;
 224 } MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;
 225
 226 /**
 227   Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch
 228   record registers on the last branch record stack. The From_IP part of the
 229   stack contains pointers to the source instruction. See also: -  Last Branch
 230   Record Stack TOS at 1C9H -  Section 17.5 and record format in Section
 231   17.4.8.1.
 232
 233   @param  ECX  MSR_SILVERMONT_LASTBRANCH_n_FROM_IP
 234   @param  EAX  Lower 32-bits of MSR value.
 235   @param  EDX  Upper 32-bits of MSR value.
 236
 237   <b>Example usage</b>
 238   @code
 239   UINT64  Msr;
 240
 241   Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
 242   AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
 243   @endcode
 244   @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
 245         MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
 246         MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
 247         MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
 248         MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
 249         MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
 250         MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
 251         MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
 252   @{
 253 **/
 254 #define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP  0x00000040
 255 #define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP  0x00000041
 256 #define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP  0x00000042
 257 #define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP  0x00000043
 258 #define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP  0x00000044
 259 #define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP  0x00000045
 260 #define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP  0x00000046
 261 #define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP  0x00000047
 262 /// @}
 263
 264 /**
 265   Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch
 266   record registers on the last branch record stack. The To_IP part of the
 267   stack contains pointers to the destination instruction.
 268
 269   @param  ECX  MSR_SILVERMONT_LASTBRANCH_n_TO_IP
 270   @param  EAX  Lower 32-bits of MSR value.
 271   @param  EDX  Upper 32-bits of MSR value.
 272
 273   <b>Example usage</b>
 274   @code
 275   UINT64  Msr;
 276
 277   Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
 278   AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
 279   @endcode
 280   @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
 281         MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
 282         MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
 283         MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
 284         MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
 285         MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
 286         MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
 287         MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
 288   @{
 289 **/
 290 #define MSR_SILVERMONT_LASTBRANCH_0_TO_IP  0x00000060
 291 #define MSR_SILVERMONT_LASTBRANCH_1_TO_IP  0x00000061
 292 #define MSR_SILVERMONT_LASTBRANCH_2_TO_IP  0x00000062
 293 #define MSR_SILVERMONT_LASTBRANCH_3_TO_IP  0x00000063
 294 #define MSR_SILVERMONT_LASTBRANCH_4_TO_IP  0x00000064
 295 #define MSR_SILVERMONT_LASTBRANCH_5_TO_IP  0x00000065
 296 #define MSR_SILVERMONT_LASTBRANCH_6_TO_IP  0x00000066
 297 #define MSR_SILVERMONT_LASTBRANCH_7_TO_IP  0x00000067
 298 /// @}
 299
 300 /**
 301   Module. Scalable Bus Speed(RO) This field indicates the intended scalable
 302   bus clock speed for processors based on Silvermont microarchitecture:.
 303
 304   @param  ECX  MSR_SILVERMONT_FSB_FREQ (0x000000CD)
 305   @param  EAX  Lower 32-bits of MSR value.
 306                Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
 307   @param  EDX  Upper 32-bits of MSR value.
 308                Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
 309
 310   <b>Example usage</b>
 311   @code
 312   MSR_SILVERMONT_FSB_FREQ_REGISTER  Msr;
 313
 314   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);
 315   @endcode
 316   @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
 317 **/
 318 #define MSR_SILVERMONT_FSB_FREQ  0x000000CD
 319
 320 /**
 321   MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ
 322 **/
 323 typedef union {
 324   ///
 325   /// Individual bit fields
 326   ///
 327   struct {
 328     ///
 329     /// [Bits 3:0] Scalable Bus Speed
 330     ///
 331     /// Silvermont Processor Family
 332     /// ---------------------------
 333     ///   100B: 080.0 MHz
 334     ///   000B: 083.3 MHz
 335     ///   001B: 100.0 MHz
 336     ///   010B: 133.3 MHz
 337     ///   011B: 116.7 MHz
 338     ///
 339     /// Airmont Processor Family
 340     /// ---------------------------
 341     ///   0000B: 083.3 MHz
 342     ///   0001B: 100.0 MHz
 343     ///   0010B: 133.3 MHz
 344     ///   0011B: 116.7 MHz
 345     ///   0100B: 080.0 MHz
 346     ///   0101B: 093.3 MHz
 347     ///   0110B: 090.0 MHz
 348     ///   0111B: 088.9 MHz
 349     ///   1000B: 087.5 MHz
 350     ///
 351     UINT32    ScalableBusSpeed : 4;
 352     UINT32    Reserved1        : 28;
 353     UINT32    Reserved2        : 32;
 354   } Bits;
 355   ///
 356   /// All bit fields as a 32-bit value
 357   ///
 358   UINT32    Uint32;
 359   ///
 360   /// All bit fields as a 64-bit value
 361   ///
 362   UINT64    Uint64;
 363 } MSR_SILVERMONT_FSB_FREQ_REGISTER;
 364
 365 /**
 366   Package. Platform Information: Contains power management and other model
 367   specific features enumeration. See http://biosbits.org.
 368
 369   @param  ECX  MSR_SILVERMONT_PLATFORM_INFO (0x000000CE)
 370   @param  EAX  Lower 32-bits of MSR value.
 371                Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
 372   @param  EDX  Upper 32-bits of MSR value.
 373                Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
 374
 375   <b>Example usage</b>
 376   @code
 377   MSR_SILVERMONT_PLATFORM_INFO_REGISTER  Msr;
 378
 379   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO);
 380   AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);
 381   @endcode
 382 **/
 383 #define MSR_SILVERMONT_PLATFORM_INFO  0x000000CE
 384
 385 /**
 386   MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO
 387 **/
 388 typedef union {
 389   ///
 390   /// Individual bit fields
 391   ///
 392   struct {
 393     UINT32    Reserved1             : 8;
 394     ///
 395     /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio
 396     /// of the maximum frequency that does not require turbo. Frequency =
 397     /// ratio * Scalable Bus Frequency.
 398     ///
 399     UINT32    MaximumNon_TurboRatio : 8;
 400     UINT32    Reserved2             : 16;
 401     UINT32    Reserved3             : 32;
 402   } Bits;
 403   ///
 404   /// All bit fields as a 32-bit value
 405   ///
 406   UINT32    Uint32;
 407   ///
 408   /// All bit fields as a 64-bit value
 409   ///
 410   UINT64    Uint64;
 411 } MSR_SILVERMONT_PLATFORM_INFO_REGISTER;
 412
 413 /**
 414   Module. C-State Configuration Control (R/W)  Note: C-state values are
 415   processor specific C-state code names, unrelated to MWAIT extension C-state
 416   parameters or ACPI CStates. See http://biosbits.org.
 417
 418   @param  ECX  MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
 419   @param  EAX  Lower 32-bits of MSR value.
 420                Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
 421   @param  EDX  Upper 32-bits of MSR value.
 422                Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
 423
 424   <b>Example usage</b>
 425   @code
 426   MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
 427
 428   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);
 429   AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
 430   @endcode
 431   @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
 432 **/
 433 #define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL  0x000000E2
 434
 435 /**
 436   MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL
 437 **/
 438 typedef union {
 439   ///
 440   /// Individual bit fields
 441   ///
 442   struct {
 443     ///
 444     /// [Bits 2:0] Package C-State Limit (R/W)  Specifies the lowest
 445     /// processor-specific C-state code name (consuming the least power). for
 446     /// the package. The default is set as factory-configured package C-state
 447     /// limit. The following C-state code name encodings are supported: 000b:
 448     /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
 449     /// 100b: C4 110b: C6 111b: C7 (Silvermont only).
 450     ///
 451     UINT32    Limit     : 3;
 452     UINT32    Reserved1 : 7;
 453     ///
 454     /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
 455     /// IO_read instructions sent to IO register specified by
 456     /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
 457     ///
 458     UINT32    IO_MWAIT  : 1;
 459     UINT32    Reserved2 : 4;
 460     ///
 461     /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
 462     /// until next reset.
 463     ///
 464     UINT32    CFGLock   : 1;
 465     UINT32    Reserved3 : 16;
 466     UINT32    Reserved4 : 32;
 467   } Bits;
 468   ///
 469   /// All bit fields as a 32-bit value
 470   ///
 471   UINT32    Uint32;
 472   ///
 473   /// All bit fields as a 64-bit value
 474   ///
 475   UINT64    Uint64;
 476 } MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
 477
 478 /**
 479   Module. Power Management IO Redirection in C-state (R/W) See
 480   http://biosbits.org.
 481
 482   @param  ECX  MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)
 483   @param  EAX  Lower 32-bits of MSR value.
 484                Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
 485   @param  EDX  Upper 32-bits of MSR value.
 486                Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
 487
 488   <b>Example usage</b>
 489   @code
 490   MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER  Msr;
 491
 492   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);
 493   AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);
 494   @endcode
 495   @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
 496 **/
 497 #define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE  0x000000E4
 498
 499 /**
 500   MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE
 501 **/
 502 typedef union {
 503   ///
 504   /// Individual bit fields
 505   ///
 506   struct {
 507     ///
 508     /// [Bits 15:0] LVL_2 Base Address (R/W)  Specifies the base address
 509     /// visible to software for IO redirection. If IO MWAIT Redirection is
 510     /// enabled, reads to this address will be consumed by the power
 511     /// management logic and decoded to MWAIT instructions. When IO port
 512     /// address redirection is enabled, this is the IO port address reported
 513     /// to the OS/software.
 514     ///
 515     UINT32    Lvl2Base    : 16;
 516     ///
 517     /// [Bits 18:16] C-state Range (R/W)  Specifies the encoding value of the
 518     /// maximum C-State code name to be included when IO read to MWAIT
 519     /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
 520     /// is the max C-State to include 110b - C6 is the max C-State to include
 521     /// 111b - C7 is the max C-State to include.
 522     ///
 523     UINT32    CStateRange : 3;
 524     UINT32    Reserved1   : 13;
 525     UINT32    Reserved2   : 32;
 526   } Bits;
 527   ///
 528   /// All bit fields as a 32-bit value
 529   ///
 530   UINT32    Uint32;
 531   ///
 532   /// All bit fields as a 64-bit value
 533   ///
 534   UINT64    Uint64;
 535 } MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;
 536
 537 /**
 538   Module.
 539
 540   @param  ECX  MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)
 541   @param  EAX  Lower 32-bits of MSR value.
 542                Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
 543   @param  EDX  Upper 32-bits of MSR value.
 544                Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
 545
 546   <b>Example usage</b>
 547   @code
 548   MSR_SILVERMONT_BBL_CR_CTL3_REGISTER  Msr;
 549
 550   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);
 551   AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);
 552   @endcode
 553   @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
 554 **/
 555 #define MSR_SILVERMONT_BBL_CR_CTL3  0x0000011E
 556
 557 /**
 558   MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3
 559 **/
 560 typedef union {
 561   ///
 562   /// Individual bit fields
 563   ///
 564   struct {
 565     ///
 566     /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
 567     /// Indicates if the L2 is hardware-disabled.
 568     ///
 569     UINT32    L2HardwareEnabled : 1;
 570     UINT32    Reserved1         : 7;
 571     ///
 572     /// [Bit 8] L2 Enabled. (R/W)  1 = L2 cache has been initialized 0 =
 573     /// Disabled (default) Until this bit is set the processor will not
 574     /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
 575     ///
 576     UINT32    L2Enabled         : 1;
 577     UINT32    Reserved2         : 14;
 578     ///
 579     /// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.
 580     ///
 581     UINT32    L2NotPresent      : 1;
 582     UINT32    Reserved3         : 8;
 583     UINT32    Reserved4         : 32;
 584   } Bits;
 585   ///
 586   /// All bit fields as a 32-bit value
 587   ///
 588   UINT32    Uint32;
 589   ///
 590   /// All bit fields as a 64-bit value
 591   ///
 592   UINT64    Uint64;
 593 } MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;
 594
 595 /**
 596   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
 597   handler to handle unsuccessful read of this MSR.
 598
 599   @param  ECX  MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)
 600   @param  EAX  Lower 32-bits of MSR value.
 601                Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
 602   @param  EDX  Upper 32-bits of MSR value.
 603                Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
 604
 605   <b>Example usage</b>
 606   @code
 607   MSR_SILVERMONT_FEATURE_CONFIG_REGISTER  Msr;
 608
 609   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);
 610   AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);
 611   @endcode
 612   @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
 613 **/
 614 #define MSR_SILVERMONT_FEATURE_CONFIG  0x0000013C
 615
 616 /**
 617   MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG
 618 **/
 619 typedef union {
 620   ///
 621   /// Individual bit fields
 622   ///
 623   struct {
 624     ///
 625     /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
 626     /// MSR, the configuration of AES instruction set availability is as
 627     /// follows: 11b: AES instructions are not available until next RESET.
 628     /// otherwise, AES instructions are available. Note, AES instruction set
 629     /// is not available if read is unsuccessful. If the configuration is not
 630     /// 01b, AES instruction can be mis-configured if a privileged agent
 631     /// unintentionally writes 11b.
 632     ///
 633     UINT32    AESConfiguration : 2;
 634     UINT32    Reserved1        : 30;
 635     UINT32    Reserved2        : 32;
 636   } Bits;
 637   ///
 638   /// All bit fields as a 32-bit value
 639   ///
 640   UINT32    Uint32;
 641   ///
 642   /// All bit fields as a 64-bit value
 643   ///
 644   UINT64    Uint64;
 645 } MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;
 646
 647 /**
 648   Enable Misc. Processor Features (R/W)  Allows a variety of processor
 649   functions to be enabled and disabled.
 650
 651   @param  ECX  MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)
 652   @param  EAX  Lower 32-bits of MSR value.
 653                Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
 654   @param  EDX  Upper 32-bits of MSR value.
 655                Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
 656
 657   <b>Example usage</b>
 658   @code
 659   MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER  Msr;
 660
 661   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);
 662   AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);
 663   @endcode
 664   @note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
 665 **/
 666 #define MSR_SILVERMONT_IA32_MISC_ENABLE  0x000001A0
 667
 668 /**
 669   MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE
 670 **/
 671 typedef union {
 672   ///
 673   /// Individual bit fields
 674   ///
 675   struct {
 676     ///
 677     /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.
 678     ///
 679     UINT32    FastStrings                    : 1;
 680     UINT32    Reserved1                      : 2;
 681     ///
 682     /// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See
 683     /// Table 2-2. Default value is 0.
 684     ///
 685     UINT32    AutomaticThermalControlCircuit : 1;
 686     UINT32    Reserved2                      : 3;
 687     ///
 688     /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.
 689     ///
 690     UINT32    PerformanceMonitoring          : 1;
 691     UINT32    Reserved3                      : 3;
 692     ///
 693     /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.
 694     ///
 695     UINT32    BTS                            : 1;
 696     ///
 697     /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
 698     /// Table 2-2.
 699     ///
 700     UINT32    PEBS                           : 1;
 701     UINT32    Reserved4                      : 3;
 702     ///
 703     /// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See
 704     /// Table 2-2.
 705     ///
 706     UINT32    EIST                           : 1;
 707     UINT32    Reserved5                      : 1;
 708     ///
 709     /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.
 710     ///
 711     UINT32    MONITOR                        : 1;
 712     UINT32    Reserved6                      : 3;
 713     ///
 714     /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.
 715     ///
 716     UINT32    LimitCpuidMaxval               : 1;
 717     ///
 718     /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.
 719     ///
 720     UINT32    xTPR_Message_Disable           : 1;
 721     UINT32    Reserved7                      : 8;
 722     UINT32    Reserved8                      : 2;
 723     ///
 724     /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.
 725     ///
 726     UINT32    XD                             : 1;
 727     UINT32    Reserved9                      : 3;
 728     ///
 729     /// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors
 730     /// that support Intel Turbo Boost Technology, the turbo mode feature is
 731     /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
 732     /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
 733     /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
 734     /// the power-on default value is used by BIOS to detect hardware support
 735     /// of turbo mode. If power-on default value is 1, turbo mode is available
 736     /// in the processor. If power-on default value is 0, turbo mode is not
 737     /// available.
 738     ///
 739     UINT32    TurboModeDisable : 1;
 740     UINT32    Reserved10       : 25;
 741   } Bits;
 742   ///
 743   /// All bit fields as a 64-bit value
 744   ///
 745   UINT64    Uint64;
 746 } MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;
 747
 748 /**
 749   Package.
 750
 751   @param  ECX  MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)
 752   @param  EAX  Lower 32-bits of MSR value.
 753                Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
 754   @param  EDX  Upper 32-bits of MSR value.
 755                Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
 756
 757   <b>Example usage</b>
 758   @code
 759   MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER  Msr;
 760
 761   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);
 762   AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);
 763   @endcode
 764   @note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
 765 **/
 766 #define MSR_SILVERMONT_TEMPERATURE_TARGET  0x000001A2
 767
 768 /**
 769   MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET
 770 **/
 771 typedef union {
 772   ///
 773   /// Individual bit fields
 774   ///
 775   struct {
 776     UINT32    Reserved1         : 16;
 777     ///
 778     /// [Bits 23:16] Temperature Target (R)  The default thermal throttling or
 779     /// PROCHOT# activation temperature in degree C, The effective temperature
 780     /// for thermal throttling or PROCHOT# activation is "Temperature Target"
 781     /// + "Target Offset".
 782     ///
 783     UINT32    TemperatureTarget : 8;
 784     ///
 785     /// [Bits 29:24] Target Offset (R/W)  Specifies an offset in degrees C to
 786     /// adjust the throttling and PROCHOT# activation temperature from the
 787     /// default target specified in TEMPERATURE_TARGET (bits 23:16).
 788     ///
 789     UINT32    TargetOffset      : 6;
 790     UINT32    Reserved2         : 2;
 791     UINT32    Reserved3         : 32;
 792   } Bits;
 793   ///
 794   /// All bit fields as a 32-bit value
 795   ///
 796   UINT32    Uint32;
 797   ///
 798   /// All bit fields as a 64-bit value
 799   ///
 800   UINT64    Uint64;
 801 } MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;
 802
 803 /**
 804   Miscellaneous Feature Control (R/W).
 805
 806   @param  ECX  MSR_SILVERMONT_MISC_FEATURE_CONTROL (0x000001A4)
 807   @param  EAX  Lower 32-bits of MSR value.
 808                Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.
 809   @param  EDX  Upper 32-bits of MSR value.
 810                Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.
 811
 812   <b>Example usage</b>
 813   @code
 814   MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER  Msr;
 815
 816   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL);
 817   AsmWriteMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL, Msr.Uint64);
 818   @endcode
 819   @note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
 820 **/
 821 #define MSR_SILVERMONT_MISC_FEATURE_CONTROL  0x000001A4
 822
 823 /**
 824   MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL
 825 **/
 826 typedef union {
 827   ///
 828   /// Individual bit fields
 829   ///
 830   struct {
 831     ///
 832     /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W)  If 1, disables the
 833     /// L2 hardware prefetcher, which fetches additional lines of code or data
 834     /// into the L2 cache.
 835     ///
 836     UINT32    L2HardwarePrefetcherDisable  : 1;
 837     UINT32    Reserved1                    : 1;
 838     ///
 839     /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W)  If 1, disables
 840     /// the L1 data cache prefetcher, which fetches the next cache line into
 841     /// L1 data cache.
 842     ///
 843     UINT32    DCUHardwarePrefetcherDisable : 1;
 844     UINT32    Reserved2                    : 29;
 845     UINT32    Reserved3                    : 32;
 846   } Bits;
 847   ///
 848   /// All bit fields as a 32-bit value
 849   ///
 850   UINT32    Uint32;
 851   ///
 852   /// All bit fields as a 64-bit value
 853   ///
 854   UINT64    Uint64;
 855 } MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;
 856
 857 /**
 858   Module. Offcore Response Event Select Register (R/W).
 859
 860   @param  ECX  MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)
 861   @param  EAX  Lower 32-bits of MSR value.
 862   @param  EDX  Upper 32-bits of MSR value.
 863
 864   <b>Example usage</b>
 865   @code
 866   UINT64  Msr;
 867
 868   Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);
 869   AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);
 870   @endcode
 871   @note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
 872 **/
 873 #define MSR_SILVERMONT_OFFCORE_RSP_0  0x000001A6
 874
 875 /**
 876   Module. Offcore Response Event Select Register (R/W).
 877
 878   @param  ECX  MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)
 879   @param  EAX  Lower 32-bits of MSR value.
 880   @param  EDX  Upper 32-bits of MSR value.
 881
 882   <b>Example usage</b>
 883   @code
 884   UINT64  Msr;
 885
 886   Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);
 887   AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);
 888   @endcode
 889   @note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 890 **/
 891 #define MSR_SILVERMONT_OFFCORE_RSP_1  0x000001A7
 892
 893 /**
 894   Package. Maximum Ratio Limit of Turbo Mode (RW).
 895
 896   @param  ECX  MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)
 897   @param  EAX  Lower 32-bits of MSR value.
 898                Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
 899   @param  EDX  Upper 32-bits of MSR value.
 900                Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
 901
 902   <b>Example usage</b>
 903   @code
 904   MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER  Msr;
 905
 906   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);
 907   AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
 908   @endcode
 909   @note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 910 **/
 911 #define MSR_SILVERMONT_TURBO_RATIO_LIMIT  0x000001AD
 912
 913 /**
 914   MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT
 915 **/
 916 typedef union {
 917   ///
 918   /// Individual bit fields
 919   ///
 920   struct {
 921     ///
 922     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
 923     /// limit of 1 core active.
 924     ///
 925     UINT32    Maximum1C : 8;
 926     ///
 927     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
 928     /// limit of 2 core active.
 929     ///
 930     UINT32    Maximum2C : 8;
 931     ///
 932     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
 933     /// limit of 3 core active.
 934     ///
 935     UINT32    Maximum3C : 8;
 936     ///
 937     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
 938     /// limit of 4 core active.
 939     ///
 940     UINT32    Maximum4C : 8;
 941     ///
 942     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
 943     /// limit of 5 core active.
 944     ///
 945     UINT32    Maximum5C : 8;
 946     ///
 947     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
 948     /// limit of 6 core active.
 949     ///
 950     UINT32    Maximum6C : 8;
 951     ///
 952     /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
 953     /// limit of 7 core active.
 954     ///
 955     UINT32    Maximum7C : 8;
 956     ///
 957     /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
 958     /// limit of 8 core active.
 959     ///
 960     UINT32    Maximum8C : 8;
 961   } Bits;
 962   ///
 963   /// All bit fields as a 64-bit value
 964   ///
 965   UINT64    Uint64;
 966 } MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;
 967
 968 /**
 969   Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
 970   "Filtering of Last Branch Records.".
 971
 972   @param  ECX  MSR_SILVERMONT_LBR_SELECT (0x000001C8)
 973   @param  EAX  Lower 32-bits of MSR value.
 974                Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.
 975   @param  EDX  Upper 32-bits of MSR value.
 976                Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.
 977
 978   <b>Example usage</b>
 979   @code
 980   MSR_SILVERMONT_LBR_SELECT_REGISTER  Msr;
 981
 982   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_LBR_SELECT);
 983   AsmWriteMsr64 (MSR_SILVERMONT_LBR_SELECT, Msr.Uint64);
 984   @endcode
 985   @note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
 986 **/
 987 #define MSR_SILVERMONT_LBR_SELECT  0x000001C8
 988
 989 /**
 990   MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT
 991 **/
 992 typedef union {
 993   ///
 994   /// Individual bit fields
 995   ///
 996   struct {
 997     ///
 998     /// [Bit 0] CPL_EQ_0.
 999     ///
1000     UINT32    CPL_EQ_0      : 1;
1001     ///
1002     /// [Bit 1] CPL_NEQ_0.
1003     ///
1004     UINT32    CPL_NEQ_0     : 1;
1005     ///
1006     /// [Bit 2] JCC.
1007     ///
1008     UINT32    JCC           : 1;
1009     ///
1010     /// [Bit 3] NEAR_REL_CALL.
1011     ///
1012     UINT32    NEAR_REL_CALL : 1;
1013     ///
1014     /// [Bit 4] NEAR_IND_CALL.
1015     ///
1016     UINT32    NEAR_IND_CALL : 1;
1017     ///
1018     /// [Bit 5] NEAR_RET.
1019     ///
1020     UINT32    NEAR_RET      : 1;
1021     ///
1022     /// [Bit 6] NEAR_IND_JMP.
1023     ///
1024     UINT32    NEAR_IND_JMP  : 1;
1025     ///
1026     /// [Bit 7] NEAR_REL_JMP.
1027     ///
1028     UINT32    NEAR_REL_JMP  : 1;
1029     ///
1030     /// [Bit 8] FAR_BRANCH.
1031     ///
1032     UINT32    FAR_BRANCH    : 1;
1033     UINT32    Reserved1     : 23;
1034     UINT32    Reserved2     : 32;
1035   } Bits;
1036   ///
1037   /// All bit fields as a 32-bit value
1038   ///
1039   UINT32    Uint32;
1040   ///
1041   /// All bit fields as a 64-bit value
1042   ///
1043   UINT64    Uint64;
1044 } MSR_SILVERMONT_LBR_SELECT_REGISTER;
1045
1046 /**
1047   Core. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-2) that
1048   points to the MSR containing the most recent branch record. See
1049   MSR_LASTBRANCH_0_FROM_IP.
1050
1051   @param  ECX  MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)
1052   @param  EAX  Lower 32-bits of MSR value.
1053   @param  EDX  Upper 32-bits of MSR value.
1054
1055   <b>Example usage</b>
1056   @code
1057   UINT64  Msr;
1058
1059   Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);
1060   AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);
1061   @endcode
1062   @note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
1063 **/
1064 #define MSR_SILVERMONT_LASTBRANCH_TOS  0x000001C9
1065
1066 /**
1067   Core. Last Exception Record From Linear IP (R)  Contains a pointer to the
1068   last branch instruction that the processor executed prior to the last
1069   exception that was generated or the last interrupt that was handled.
1070
1071   @param  ECX  MSR_SILVERMONT_LER_FROM_LIP (0x000001DD)
1072   @param  EAX  Lower 32-bits of MSR value.
1073   @param  EDX  Upper 32-bits of MSR value.
1074
1075   <b>Example usage</b>
1076   @code
1077   UINT64  Msr;
1078
1079   Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);
1080   @endcode
1081   @note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
1082 **/
1083 #define MSR_SILVERMONT_LER_FROM_LIP  0x000001DD
1084
1085 /**
1086   Core. Last Exception Record To Linear IP (R)  This area contains a pointer
1087   to the target of the last branch instruction that the processor executed
1088   prior to the last exception that was generated or the last interrupt that
1089   was handled.
1090
1091   @param  ECX  MSR_SILVERMONT_LER_TO_LIP (0x000001DE)
1092   @param  EAX  Lower 32-bits of MSR value.
1093   @param  EDX  Upper 32-bits of MSR value.
1094
1095   <b>Example usage</b>
1096   @code
1097   UINT64  Msr;
1098
1099   Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);
1100   @endcode
1101   @note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
1102 **/
1103 #define MSR_SILVERMONT_LER_TO_LIP  0x000001DE
1104
1105 /**
1106   Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
1107   (PEBS).".
1108
1109   @param  ECX  MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)
1110   @param  EAX  Lower 32-bits of MSR value.
1111                Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
1112   @param  EDX  Upper 32-bits of MSR value.
1113                Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
1114
1115   <b>Example usage</b>
1116   @code
1117   MSR_SILVERMONT_PEBS_ENABLE_REGISTER  Msr;
1118
1119   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);
1120   AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);
1121   @endcode
1122   @note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1123 **/
1124 #define MSR_SILVERMONT_PEBS_ENABLE  0x000003F1
1125
1126 /**
1127   MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE
1128 **/
1129 typedef union {
1130   ///
1131   /// Individual bit fields
1132   ///
1133   struct {
1134     ///
1135     /// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).
1136     ///
1137     UINT32    PEBS      : 1;
1138     UINT32    Reserved1 : 31;
1139     UINT32    Reserved2 : 32;
1140   } Bits;
1141   ///
1142   /// All bit fields as a 32-bit value
1143   ///
1144   UINT32    Uint32;
1145   ///
1146   /// All bit fields as a 64-bit value
1147   ///
1148   UINT64    Uint64;
1149 } MSR_SILVERMONT_PEBS_ENABLE_REGISTER;
1150
1151 /**
1152   Package. Note: C-state values are processor specific C-state code names,
1153   unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
1154   Residency Counter. (R/O) Value since last reset that this package is in
1155   processor-specific C6 states. Counts at the TSC Frequency.
1156
1157   @param  ECX  MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)
1158   @param  EAX  Lower 32-bits of MSR value.
1159   @param  EDX  Upper 32-bits of MSR value.
1160
1161   <b>Example usage</b>
1162   @code
1163   UINT64  Msr;
1164
1165   Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);
1166   AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);
1167   @endcode
1168   @note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1169 **/
1170 #define MSR_SILVERMONT_PKG_C6_RESIDENCY  0x000003FA
1171
1172 /**
1173   Core. Note: C-state values are processor specific C-state code names,
1174   unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
1175   Residency Counter. (R/O) Value since last reset that this core is in
1176   processor-specific C6 states. Counts at the TSC Frequency.
1177
1178   @param  ECX  MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)
1179   @param  EAX  Lower 32-bits of MSR value.
1180   @param  EDX  Upper 32-bits of MSR value.
1181
1182   <b>Example usage</b>
1183   @code
1184   UINT64  Msr;
1185
1186   Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);
1187   AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);
1188   @endcode
1189   @note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1190 **/
1191 #define MSR_SILVERMONT_CORE_C6_RESIDENCY  0x000003FD
1192
1193 /**
1194   Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
1195
1196   @param  ECX  MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1197   @param  EAX  Lower 32-bits of MSR value.
1198   @param  EDX  Upper 32-bits of MSR value.
1199
1200   <b>Example usage</b>
1201   @code
1202   UINT64  Msr;
1203
1204   Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);
1205   @endcode
1206   @note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1207 **/
1208 #define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM  0x0000048C
1209
1210 /**
1211   Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
1212   2-2.
1213
1214   @param  ECX  MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)
1215   @param  EAX  Lower 32-bits of MSR value.
1216   @param  EDX  Upper 32-bits of MSR value.
1217
1218   <b>Example usage</b>
1219   @code
1220   UINT64  Msr;
1221
1222   Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);
1223   @endcode
1224   @note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
1225 **/
1226 #define MSR_SILVERMONT_IA32_VMX_FMFUNC  0x00000491
1227
1228 /**
1229   Core. Note: C-state values are processor specific C-state code names,
1230   unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1
1231   Residency Counter. (R/O) Value since last reset that this core is in
1232   processor-specific C1 states. Counts at the TSC frequency.
1233
1234   @param  ECX  MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)
1235   @param  EAX  Lower 32-bits of MSR value.
1236   @param  EDX  Upper 32-bits of MSR value.
1237
1238   <b>Example usage</b>
1239   @code
1240   UINT64  Msr;
1241
1242   Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);
1243   AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);
1244   @endcode
1245   @note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.
1246 **/
1247 #define MSR_SILVERMONT_CORE_C1_RESIDENCY  0x00000660
1248
1249 /**
1250   Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
1251   "RAPL Interfaces.".
1252
1253   @param  ECX  MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)
1254   @param  EAX  Lower 32-bits of MSR value.
1255                Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
1256   @param  EDX  Upper 32-bits of MSR value.
1257                Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
1258
1259   <b>Example usage</b>
1260   @code
1261   MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER  Msr;
1262
1263   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);
1264   @endcode
1265   @note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1266 **/
1267 #define MSR_SILVERMONT_RAPL_POWER_UNIT  0x00000606
1268
1269 /**
1270   MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT
1271 **/
1272 typedef union {
1273   ///
1274   /// Individual bit fields
1275   ///
1276   struct {
1277     ///
1278     /// [Bits 3:0] Power Units. Power related information (in milliWatts) is
1279     /// based on the multiplier, 2^PU; where PU is an unsigned integer
1280     /// represented by bits 3:0. Default value is 0101b, indicating power unit
1281     /// is in 32 milliWatts increment.
1282     ///
1283     UINT32    PowerUnits        : 4;
1284     UINT32    Reserved1         : 4;
1285     ///
1286     /// [Bits 12:8] Energy Status Units. Energy related information (in
1287     /// microJoules) is based on the multiplier, 2^ESU; where ESU is an
1288     /// unsigned integer represented by bits 12:8. Default value is 00101b,
1289     /// indicating energy unit is in 32 microJoules increment.
1290     ///
1291     UINT32    EnergyStatusUnits : 5;
1292     UINT32    Reserved2         : 3;
1293     ///
1294     /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in
1295     /// one second.
1296     ///
1297     UINT32    TimeUnits         : 4;
1298     UINT32    Reserved3         : 12;
1299     UINT32    Reserved4         : 32;
1300   } Bits;
1301   ///
1302   /// All bit fields as a 32-bit value
1303   ///
1304   UINT32    Uint32;
1305   ///
1306   /// All bit fields as a 64-bit value
1307   ///
1308   UINT64    Uint64;
1309 } MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;
1310
1311 /**
1312   Package. PKG RAPL Power Limit Control (R/W).
1313
1314   @param  ECX  MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)
1315   @param  EAX  Lower 32-bits of MSR value.
1316                Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
1317   @param  EDX  Upper 32-bits of MSR value.
1318                Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
1319
1320   <b>Example usage</b>
1321   @code
1322   MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER  Msr;
1323
1324   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);
1325   AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);
1326   @endcode
1327   @note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1328 **/
1329 #define MSR_SILVERMONT_PKG_POWER_LIMIT  0x00000610
1330
1331 /**
1332   MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT
1333 **/
1334 typedef union {
1335   ///
1336   /// Individual bit fields
1337   ///
1338   struct {
1339     ///
1340     /// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package
1341     /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.
1342     ///
1343     UINT32    Limit         : 15;
1344     ///
1345     /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package
1346     /// RAPL Domain.".
1347     ///
1348     UINT32    Enable        : 1;
1349     ///
1350     /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,
1351     /// "Package RAPL Domain.".
1352     ///
1353     UINT32    ClampingLimit : 1;
1354     ///
1355     /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.
1356     /// If 0 is specified in bits [23:17], defaults to 1 second window.
1357     ///
1358     UINT32    Time          : 7;
1359     UINT32    Reserved1     : 8;
1360     UINT32    Reserved2     : 32;
1361   } Bits;
1362   ///
1363   /// All bit fields as a 32-bit value
1364   ///
1365   UINT32    Uint32;
1366   ///
1367   /// All bit fields as a 64-bit value
1368   ///
1369   UINT64    Uint64;
1370 } MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;
1371
1372 /**
1373   Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."
1374   and MSR_RAPL_POWER_UNIT in Table 2-8.
1375
1376   @param  ECX  MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)
1377   @param  EAX  Lower 32-bits of MSR value.
1378   @param  EDX  Upper 32-bits of MSR value.
1379
1380   <b>Example usage</b>
1381   @code
1382   UINT64  Msr;
1383
1384   Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);
1385   @endcode
1386   @note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1387 **/
1388 #define MSR_SILVERMONT_PKG_ENERGY_STATUS  0x00000611
1389
1390 /**
1391   Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains."
1392   and MSR_RAPL_POWER_UNIT in Table 2-8.
1393
1394   @param  ECX  MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)
1395   @param  EAX  Lower 32-bits of MSR value.
1396   @param  EDX  Upper 32-bits of MSR value.
1397
1398   <b>Example usage</b>
1399   @code
1400   UINT64  Msr;
1401
1402   Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);
1403   @endcode
1404   @note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1405 **/
1406 #define MSR_SILVERMONT_PP0_ENERGY_STATUS  0x00000639
1407
1408 /**
1409   Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion
1410   policy. Writing a value of 0 disables core level HW demotion policy.
1411
1412   @param  ECX  MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)
1413   @param  EAX  Lower 32-bits of MSR value.
1414   @param  EDX  Upper 32-bits of MSR value.
1415
1416   <b>Example usage</b>
1417   @code
1418   UINT64  Msr;
1419
1420   Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);
1421   AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);
1422   @endcode
1423   @note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.
1424 **/
1425 #define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG  0x00000668
1426
1427 /**
1428   Package. Module C6 demotion policy config MSR. Controls module (i.e. two
1429   cores sharing the second-level cache) C6 demotion policy. Writing a value of
1430   0 disables module level HW demotion policy.
1431
1432   @param  ECX  MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)
1433   @param  EAX  Lower 32-bits of MSR value.
1434   @param  EDX  Upper 32-bits of MSR value.
1435
1436   <b>Example usage</b>
1437   @code
1438   UINT64  Msr;
1439
1440   Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);
1441   AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);
1442   @endcode
1443   @note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.
1444 **/
1445 #define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG  0x00000669
1446
1447 /**
1448   Module. Module C6 Residency Counter (R/0) Note: C-state values are processor
1449   specific C-state code names, unrelated to MWAIT extension C-state parameters
1450   or ACPI CStates. Time that this module is in module-specific C6 states since
1451   last reset. Counts at 1 Mhz frequency.
1452
1453   @param  ECX  MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)
1454   @param  EAX  Lower 32-bits of MSR value.
1455   @param  EDX  Upper 32-bits of MSR value.
1456
1457   <b>Example usage</b>
1458   @code
1459   UINT64  Msr;
1460
1461   Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);
1462   @endcode
1463   @note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.
1464 **/
1465 #define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER  0x00000664
1466
1467 /**
1468   Package. PKG RAPL Parameter (R/0).
1469
1470   @param  ECX  MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)
1471   @param  EAX  Lower 32-bits of MSR value.
1472                Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
1473   @param  EDX  Upper 32-bits of MSR value.
1474                Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
1475
1476   <b>Example usage</b>
1477   @code
1478   MSR_SILVERMONT_PKG_POWER_INFO_REGISTER  Msr;
1479
1480   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);
1481   @endcode
1482   @note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1483 **/
1484 #define MSR_SILVERMONT_PKG_POWER_INFO  0x0000066E
1485
1486 /**
1487   MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO
1488 **/
1489 typedef union {
1490   ///
1491   /// Individual bit fields
1492   ///
1493   struct {
1494     ///
1495     /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is
1496     /// the equivalent of thermal specification power of the package domain.
1497     /// The unit of this field is specified by the "Power Units" field of
1498     /// MSR_RAPL_POWER_UNIT.
1499     ///
1500     UINT32    ThermalSpecPower : 15;
1501     UINT32    Reserved1        : 17;
1502     UINT32    Reserved2        : 32;
1503   } Bits;
1504   ///
1505   /// All bit fields as a 32-bit value
1506   ///
1507   UINT32    Uint32;
1508   ///
1509   /// All bit fields as a 64-bit value
1510   ///
1511   UINT64    Uint64;
1512 } MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;
1513
1514 /**
1515   Package. PP0 RAPL Power Limit Control (R/W).
1516
1517   @param  ECX  MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)
1518   @param  EAX  Lower 32-bits of MSR value.
1519                Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
1520   @param  EDX  Upper 32-bits of MSR value.
1521                Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
1522
1523   <b>Example usage</b>
1524   @code
1525   MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER  Msr;
1526
1527   Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);
1528   AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);
1529   @endcode
1530   @note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1531 **/
1532 #define MSR_SILVERMONT_PP0_POWER_LIMIT  0x00000638
1533
1534 /**
1535   MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT
1536 **/
1537 typedef union {
1538   ///
1539   /// Individual bit fields
1540   ///
1541   struct {
1542     ///
1543     /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
1544     /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.
1545     ///
1546     UINT32    Limit     : 15;
1547     ///
1548     /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
1549     /// RAPL Domains.".
1550     ///
1551     UINT32    Enable    : 1;
1552     UINT32    Reserved1 : 1;
1553     ///
1554     /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time
1555     /// duration over which the average power must remain below
1556     /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time
1557     /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time
1558     /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration.
1559     /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35
1560     /// second time duration. 0x8: 40 second time duration. 0x9: 45 second
1561     /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.
1562     ///
1563     UINT32    Time      : 7;
1564     UINT32    Reserved2 : 8;
1565     UINT32    Reserved3 : 32;
1566   } Bits;
1567   ///
1568   /// All bit fields as a 32-bit value
1569   ///
1570   UINT32    Uint32;
1571   ///
1572   /// All bit fields as a 64-bit value
1573   ///
1574   UINT64    Uint64;
1575 } MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;
1576
1577 #endif