MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h

   1 /** @file
   2   MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __XEON_5600_MSR_H__
  19 #define __XEON_5600_MSR_H__
  20
  21 #include <Register/Intel/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Intel(R) Xeon(R) Processor Series 5600?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x06 && \
  34    (                        \
  35     DisplayModel == 0x25 || \
  36     DisplayModel == 0x2C    \
  37     )                       \
  38    )
  39
  40 /**
  41   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
  42   handler to handle unsuccessful read of this MSR.
  43
  44   @param  ECX  MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
  45   @param  EAX  Lower 32-bits of MSR value.
  46                Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
  47   @param  EDX  Upper 32-bits of MSR value.
  48                Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
  49
  50   <b>Example usage</b>
  51   @code
  52   MSR_XEON_5600_FEATURE_CONFIG_REGISTER  Msr;
  53
  54   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
  55   AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
  56   @endcode
  57   @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
  58 **/
  59 #define MSR_XEON_5600_FEATURE_CONFIG  0x0000013C
  60
  61 /**
  62   MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
  63 **/
  64 typedef union {
  65   ///
  66   /// Individual bit fields
  67   ///
  68   struct {
  69     ///
  70     /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
  71     /// MSR, the configuration of AES instruction set availability is as
  72     /// follows: 11b: AES instructions are not available until next RESET.
  73     /// otherwise, AES instructions are available. Note, AES instruction set
  74     /// is not available if read is unsuccessful. If the configuration is not
  75     /// 01b, AES instruction can be mis-configured if a privileged agent
  76     /// unintentionally writes 11b.
  77     ///
  78     UINT32    AESConfiguration : 2;
  79     UINT32    Reserved1        : 30;
  80     UINT32    Reserved2        : 32;
  81   } Bits;
  82   ///
  83   /// All bit fields as a 32-bit value
  84   ///
  85   UINT32    Uint32;
  86   ///
  87   /// All bit fields as a 64-bit value
  88   ///
  89   UINT64    Uint64;
  90 } MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
  91
  92 /**
  93   Thread. Offcore Response Event Select Register (R/W).
  94
  95   @param  ECX  MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
  96   @param  EAX  Lower 32-bits of MSR value.
  97   @param  EDX  Upper 32-bits of MSR value.
  98
  99   <b>Example usage</b>
 100   @code
 101   UINT64  Msr;
 102
 103   Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
 104   AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
 105   @endcode
 106   @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 107 **/
 108 #define MSR_XEON_5600_OFFCORE_RSP_1  0x000001A7
 109
 110 /**
 111   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 112   RW if MSR_PLATFORM_INFO.[28] = 1.
 113
 114   @param  ECX  MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
 115   @param  EAX  Lower 32-bits of MSR value.
 116                Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
 117   @param  EDX  Upper 32-bits of MSR value.
 118                Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
 119
 120   <b>Example usage</b>
 121   @code
 122   MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER  Msr;
 123
 124   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
 125   @endcode
 126   @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 127 **/
 128 #define MSR_XEON_5600_TURBO_RATIO_LIMIT  0x000001AD
 129
 130 /**
 131   MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
 132 **/
 133 typedef union {
 134   ///
 135   /// Individual bit fields
 136   ///
 137   struct {
 138     ///
 139     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
 140     /// limit of 1 core active.
 141     ///
 142     UINT32    Maximum1C : 8;
 143     ///
 144     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
 145     /// limit of 2 core active.
 146     ///
 147     UINT32    Maximum2C : 8;
 148     ///
 149     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
 150     /// limit of 3 core active.
 151     ///
 152     UINT32    Maximum3C : 8;
 153     ///
 154     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
 155     /// limit of 4 core active.
 156     ///
 157     UINT32    Maximum4C : 8;
 158     ///
 159     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
 160     /// limit of 5 core active.
 161     ///
 162     UINT32    Maximum5C : 8;
 163     ///
 164     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
 165     /// limit of 6 core active.
 166     ///
 167     UINT32    Maximum6C : 8;
 168     UINT32    Reserved  : 16;
 169   } Bits;
 170   ///
 171   /// All bit fields as a 64-bit value
 172   ///
 173   UINT64    Uint64;
 174 } MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;
 175
 176 /**
 177   Package. See Table 2-2.
 178
 179   @param  ECX  MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
 180   @param  EAX  Lower 32-bits of MSR value.
 181   @param  EDX  Upper 32-bits of MSR value.
 182
 183   <b>Example usage</b>
 184   @code
 185   UINT64  Msr;
 186
 187   Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
 188   AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
 189   @endcode
 190   @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
 191 **/
 192 #define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS  0x000001B0
 193
 194 #endif