MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h

   1 /** @file
   2   MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
  10   SPDX-License-Identifier: BSD-2-Clause-Patent
  11
  12   @par Specification Reference:
  13   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
  14   May 2018, Volume 4: Model-Specific-Registers (MSR)
  15
  16 **/
  17
  18 #ifndef __XEON_E7_MSR_H__
  19 #define __XEON_E7_MSR_H__
  20
  21 #include <Register/Intel/ArchitecturalMsr.h>
  22
  23 /**
  24   Is Intel(R) Xeon(R) Processor E7 Family?
  25
  26   @param   DisplayFamily  Display Family ID
  27   @param   DisplayModel   Display Model ID
  28
  29   @retval  TRUE   Yes, it is.
  30   @retval  FALSE  No, it isn't.
  31 **/
  32 #define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \
  33   (DisplayFamily == 0x06 && \
  34    (                        \
  35     DisplayModel == 0x2F    \
  36     )                       \
  37    )
  38
  39 /**
  40   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
  41   handler to handle unsuccessful read of this MSR.
  42
  43   @param  ECX  MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)
  44   @param  EAX  Lower 32-bits of MSR value.
  45                Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
  46   @param  EDX  Upper 32-bits of MSR value.
  47                Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
  48
  49   <b>Example usage</b>
  50   @code
  51   MSR_XEON_E7_FEATURE_CONFIG_REGISTER  Msr;
  52
  53   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);
  54   AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);
  55   @endcode
  56   @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
  57 **/
  58 #define MSR_XEON_E7_FEATURE_CONFIG  0x0000013C
  59
  60 /**
  61   MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG
  62 **/
  63 typedef union {
  64   ///
  65   /// Individual bit fields
  66   ///
  67   struct {
  68     ///
  69     /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
  70     /// MSR, the configuration of AES instruction set availability is as
  71     /// follows: 11b: AES instructions are not available until next RESET.
  72     /// otherwise, AES instructions are available. Note, AES instruction set
  73     /// is not available if read is unsuccessful. If the configuration is not
  74     /// 01b, AES instruction can be mis-configured if a privileged agent
  75     /// unintentionally writes 11b.
  76     ///
  77     UINT32    AESConfiguration : 2;
  78     UINT32    Reserved1        : 30;
  79     UINT32    Reserved2        : 32;
  80   } Bits;
  81   ///
  82   /// All bit fields as a 32-bit value
  83   ///
  84   UINT32    Uint32;
  85   ///
  86   /// All bit fields as a 64-bit value
  87   ///
  88   UINT64    Uint64;
  89 } MSR_XEON_E7_FEATURE_CONFIG_REGISTER;
  90
  91 /**
  92   Thread. Offcore Response Event Select Register (R/W).
  93
  94   @param  ECX  MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)
  95   @param  EAX  Lower 32-bits of MSR value.
  96   @param  EDX  Upper 32-bits of MSR value.
  97
  98   <b>Example usage</b>
  99   @code
 100   UINT64  Msr;
 101
 102   Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);
 103   AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);
 104   @endcode
 105   @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
 106 **/
 107 #define MSR_XEON_E7_OFFCORE_RSP_1  0x000001A7
 108
 109 /**
 110   Package. Reserved Attempt to read/write will cause #UD.
 111
 112   @param  ECX  MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
 113   @param  EAX  Lower 32-bits of MSR value.
 114   @param  EDX  Upper 32-bits of MSR value.
 115
 116   <b>Example usage</b>
 117   @code
 118   UINT64  Msr;
 119
 120   Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
 121   AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
 122   @endcode
 123   @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 124 **/
 125 #define MSR_XEON_E7_TURBO_RATIO_LIMIT  0x000001AD
 126
 127 /**
 128   Package. Uncore C-box 8 perfmon local box control MSR.
 129
 130   @param  ECX  MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)
 131   @param  EAX  Lower 32-bits of MSR value.
 132   @param  EDX  Upper 32-bits of MSR value.
 133
 134   <b>Example usage</b>
 135   @code
 136   UINT64  Msr;
 137
 138   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
 139   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
 140   @endcode
 141   @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.
 142 **/
 143 #define MSR_XEON_E7_C8_PMON_BOX_CTRL  0x00000F40
 144
 145 /**
 146   Package. Uncore C-box 8 perfmon local box status MSR.
 147
 148   @param  ECX  MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)
 149   @param  EAX  Lower 32-bits of MSR value.
 150   @param  EDX  Upper 32-bits of MSR value.
 151
 152   <b>Example usage</b>
 153   @code
 154   UINT64  Msr;
 155
 156   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
 157   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
 158   @endcode
 159   @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
 160 **/
 161 #define MSR_XEON_E7_C8_PMON_BOX_STATUS  0x00000F41
 162
 163 /**
 164   Package. Uncore C-box 8 perfmon local box overflow control MSR.
 165
 166   @param  ECX  MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)
 167   @param  EAX  Lower 32-bits of MSR value.
 168   @param  EDX  Upper 32-bits of MSR value.
 169
 170   <b>Example usage</b>
 171   @code
 172   UINT64  Msr;
 173
 174   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
 175   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
 176   @endcode
 177   @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.
 178 **/
 179 #define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL  0x00000F42
 180
 181 /**
 182   Package. Uncore C-box 8 perfmon event select MSR.
 183
 184   @param  ECX  MSR_XEON_E7_C8_PMON_EVNT_SELn
 185   @param  EAX  Lower 32-bits of MSR value.
 186   @param  EDX  Upper 32-bits of MSR value.
 187
 188   <b>Example usage</b>
 189   @code
 190   UINT64  Msr;
 191
 192   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
 193   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
 194   @endcode
 195   @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.
 196         MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.
 197         MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.
 198         MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.
 199         MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.
 200         MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.
 201   @{
 202 **/
 203 #define MSR_XEON_E7_C8_PMON_EVNT_SEL0  0x00000F50
 204 #define MSR_XEON_E7_C8_PMON_EVNT_SEL1  0x00000F52
 205 #define MSR_XEON_E7_C8_PMON_EVNT_SEL2  0x00000F54
 206 #define MSR_XEON_E7_C8_PMON_EVNT_SEL3  0x00000F56
 207 #define MSR_XEON_E7_C8_PMON_EVNT_SEL4  0x00000F58
 208 #define MSR_XEON_E7_C8_PMON_EVNT_SEL5  0x00000F5A
 209 /// @}
 210
 211 /**
 212   Package. Uncore C-box 8 perfmon counter MSR.
 213
 214   @param  ECX  MSR_XEON_E7_C8_PMON_CTRn
 215   @param  EAX  Lower 32-bits of MSR value.
 216   @param  EDX  Upper 32-bits of MSR value.
 217
 218   <b>Example usage</b>
 219   @code
 220   UINT64  Msr;
 221
 222   Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
 223   AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
 224   @endcode
 225   @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
 226         MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
 227         MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
 228         MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
 229         MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.
 230         MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.
 231   @{
 232 **/
 233 #define MSR_XEON_E7_C8_PMON_CTR0  0x00000F51
 234 #define MSR_XEON_E7_C8_PMON_CTR1  0x00000F53
 235 #define MSR_XEON_E7_C8_PMON_CTR2  0x00000F55
 236 #define MSR_XEON_E7_C8_PMON_CTR3  0x00000F57
 237 #define MSR_XEON_E7_C8_PMON_CTR4  0x00000F59
 238 #define MSR_XEON_E7_C8_PMON_CTR5  0x00000F5B
 239 /// @}
 240
 241 /**
 242   Package. Uncore C-box 9 perfmon local box control MSR.
 243
 244   @param  ECX  MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)
 245   @param  EAX  Lower 32-bits of MSR value.
 246   @param  EDX  Upper 32-bits of MSR value.
 247
 248   <b>Example usage</b>
 249   @code
 250   UINT64  Msr;
 251
 252   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
 253   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
 254   @endcode
 255   @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.
 256 **/
 257 #define MSR_XEON_E7_C9_PMON_BOX_CTRL  0x00000FC0
 258
 259 /**
 260   Package. Uncore C-box 9 perfmon local box status MSR.
 261
 262   @param  ECX  MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)
 263   @param  EAX  Lower 32-bits of MSR value.
 264   @param  EDX  Upper 32-bits of MSR value.
 265
 266   <b>Example usage</b>
 267   @code
 268   UINT64  Msr;
 269
 270   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
 271   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
 272   @endcode
 273   @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
 274 **/
 275 #define MSR_XEON_E7_C9_PMON_BOX_STATUS  0x00000FC1
 276
 277 /**
 278   Package. Uncore C-box 9 perfmon local box overflow control MSR.
 279
 280   @param  ECX  MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)
 281   @param  EAX  Lower 32-bits of MSR value.
 282   @param  EDX  Upper 32-bits of MSR value.
 283
 284   <b>Example usage</b>
 285   @code
 286   UINT64  Msr;
 287
 288   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
 289   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
 290   @endcode
 291   @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.
 292 **/
 293 #define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL  0x00000FC2
 294
 295 /**
 296   Package. Uncore C-box 9 perfmon event select MSR.
 297
 298   @param  ECX  MSR_XEON_E7_C9_PMON_EVNT_SELn
 299   @param  EAX  Lower 32-bits of MSR value.
 300   @param  EDX  Upper 32-bits of MSR value.
 301
 302   <b>Example usage</b>
 303   @code
 304   UINT64  Msr;
 305
 306   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
 307   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
 308   @endcode
 309   @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.
 310         MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.
 311         MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.
 312         MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.
 313         MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.
 314         MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.
 315   @{
 316 **/
 317 #define MSR_XEON_E7_C9_PMON_EVNT_SEL0  0x00000FD0
 318 #define MSR_XEON_E7_C9_PMON_EVNT_SEL1  0x00000FD2
 319 #define MSR_XEON_E7_C9_PMON_EVNT_SEL2  0x00000FD4
 320 #define MSR_XEON_E7_C9_PMON_EVNT_SEL3  0x00000FD6
 321 #define MSR_XEON_E7_C9_PMON_EVNT_SEL4  0x00000FD8
 322 #define MSR_XEON_E7_C9_PMON_EVNT_SEL5  0x00000FDA
 323 /// @}
 324
 325 /**
 326   Package. Uncore C-box 9 perfmon counter MSR.
 327
 328   @param  ECX  MSR_XEON_E7_C9_PMON_CTRn
 329   @param  EAX  Lower 32-bits of MSR value.
 330   @param  EDX  Upper 32-bits of MSR value.
 331
 332   <b>Example usage</b>
 333   @code
 334   UINT64  Msr;
 335
 336   Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
 337   AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
 338   @endcode
 339   @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
 340         MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
 341         MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
 342         MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
 343         MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.
 344         MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.
 345   @{
 346 **/
 347 #define MSR_XEON_E7_C9_PMON_CTR0  0x00000FD1
 348 #define MSR_XEON_E7_C9_PMON_CTR1  0x00000FD3
 349 #define MSR_XEON_E7_C9_PMON_CTR2  0x00000FD5
 350 #define MSR_XEON_E7_C9_PMON_CTR3  0x00000FD7
 351 #define MSR_XEON_E7_C9_PMON_CTR4  0x00000FD9
 352 #define MSR_XEON_E7_C9_PMON_CTR5  0x00000FDB
 353 /// @}
 354
 355 #endif