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1 /** @file
2 MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.
3
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
7 provided for that MSR.
8
9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
10 SPDX-License-Identifier: BSD-2-Clause-Patent
11
12 @par Specification Reference:
13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
14 May 2018, Volume 4: Model-Specific-Registers (MSR)
15
16 **/
17
18 #ifndef __XEON_PHI_MSR_H__
19 #define __XEON_PHI_MSR_H__
20
21 #include <Register/Intel/ArchitecturalMsr.h>
22
23 /**
24 Is Intel(R) Xeon(R) Phi(TM) processor Family?
25
26 @param DisplayFamily Display Family ID
27 @param DisplayModel Display Model ID
28
29 @retval TRUE Yes, it is.
30 @retval FALSE No, it isn't.
31 **/
32 #define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
33 (DisplayFamily == 0x06 && \
34 ( \
35 DisplayModel == 0x57 || \
36 DisplayModel == 0x85 \
37 ) \
38 )
39
40 /**
41 Thread. SMI Counter (R/O).
42
43 @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)
44 @param EAX Lower 32-bits of MSR value.
45 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
46 @param EDX Upper 32-bits of MSR value.
47 Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
48
49 <b>Example usage</b>
50 @code
51 MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;
52
53 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
54 @endcode
55 @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
56 **/
57 #define MSR_XEON_PHI_SMI_COUNT 0x00000034
58
59 /**
60 MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
61 **/
62 typedef union {
63 ///
64 /// Individual bit fields
65 ///
66 struct {
67 ///
68 /// [Bits 31:0] SMI Count (R/O).
69 ///
70 UINT32 SMICount : 32;
71 UINT32 Reserved : 32;
72 } Bits;
73 ///
74 /// All bit fields as a 32-bit value
75 ///
76 UINT32 Uint32;
77 ///
78 /// All bit fields as a 64-bit value
79 ///
80 UINT64 Uint64;
81 } MSR_XEON_PHI_SMI_COUNT_REGISTER;
82
83 /**
84 Package. Protected Processor Inventory Number Enable Control (R/W).
85
86 @param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E)
87 @param EAX Lower 32-bits of MSR value.
88 Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
89 @param EDX Upper 32-bits of MSR value.
90 Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
91
92 <b>Example usage</b>
93 @code
94 MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;
95
96 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);
97 AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);
98 @endcode
99 **/
100 #define MSR_XEON_PHI_PPIN_CTL 0x0000004E
101
102 /**
103 MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL
104 **/
105 typedef union {
106 ///
107 /// Individual bit fields
108 ///
109 struct {
110 ///
111 /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to
112 /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if
113 /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an
114 /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a
115 /// privileged inventory initialization agent to access MSR_PPIN. After
116 /// reading MSR_PPIN, the privileged inventory initialization agent should
117 /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
118 /// prevent unauthorized modification to MSR_PPIN_CTL.
119 ///
120 UINT32 LockOut : 1;
121 ///
122 /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
123 /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]
124 /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.
125 /// Default is 0.
126 ///
127 UINT32 Enable_PPIN : 1;
128 UINT32 Reserved1 : 30;
129 UINT32 Reserved2 : 32;
130 } Bits;
131 ///
132 /// All bit fields as a 32-bit value
133 ///
134 UINT32 Uint32;
135 ///
136 /// All bit fields as a 64-bit value
137 ///
138 UINT64 Uint64;
139 } MSR_XEON_PHI_PPIN_CTL_REGISTER;
140
141 /**
142 Package. Protected Processor Inventory Number (R/O). Protected Processor
143 Inventory Number (R/O) A unique value within a given CPUID
144 family/model/stepping signature that a privileged inventory initialization
145 agent can access to identify each physical processor, when access to
146 MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
147 MSR_PPIN_CTL[bits 1:0] = '10b'.
148
149 @param ECX MSR_XEON_PHI_PPIN (0x0000004F)
150 @param EAX Lower 32-bits of MSR value.
151 @param EDX Upper 32-bits of MSR value.
152
153 <b>Example usage</b>
154 @code
155 UINT64 Msr;
156
157 Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);
158 @endcode
159 **/
160 #define MSR_XEON_PHI_PPIN 0x0000004F
161
162 /**
163 Package. Platform Information Contains power management and other model
164 specific features enumeration. See http://biosbits.org.
165
166 @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
167 @param EAX Lower 32-bits of MSR value.
168 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
169 @param EDX Upper 32-bits of MSR value.
170 Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
171
172 <b>Example usage</b>
173 @code
174 MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;
175
176 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
177 AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
178 @endcode
179 @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
180 **/
181 #define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE
182
183 /**
184 MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
185 **/
186 typedef union {
187 ///
188 /// Individual bit fields
189 ///
190 struct {
191 UINT32 Reserved1 : 8;
192 ///
193 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio
194 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
195 /// MHz.
196 ///
197 UINT32 MaximumNonTurboRatio : 8;
198 UINT32 Reserved2 : 12;
199 ///
200 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When
201 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
202 /// enabled, and when set to 0, indicates Programmable Ratio Limits for
203 /// Turbo mode is disabled.
204 ///
205 UINT32 RatioLimit : 1;
206 ///
207 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When
208 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
209 /// and when set to 0, indicates TDP Limit for Turbo mode is not
210 /// programmable.
211 ///
212 UINT32 TDPLimit : 1;
213 UINT32 Reserved3 : 2;
214 UINT32 Reserved4 : 8;
215 ///
216 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the
217 /// minimum ratio (maximum efficiency) that the processor can operates, in
218 /// units of 100MHz.
219 ///
220 UINT32 MaximumEfficiencyRatio : 8;
221 UINT32 Reserved5 : 16;
222 } Bits;
223 ///
224 /// All bit fields as a 64-bit value
225 ///
226 UINT64 Uint64;
227 } MSR_XEON_PHI_PLATFORM_INFO_REGISTER;
228
229 /**
230 Module. C-State Configuration Control (R/W).
231
232 @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)
233 @param EAX Lower 32-bits of MSR value.
234 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
235 @param EDX Upper 32-bits of MSR value.
236 Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
237
238 <b>Example usage</b>
239 @code
240 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;
241
242 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
243 AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
244 @endcode
245 @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
246 **/
247 #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2
248
249 /**
250 MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL
251 **/
252 typedef union {
253 ///
254 /// Individual bit fields
255 ///
256 struct {
257 ///
258 /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code
259 /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No
260 /// Retention 011b: C6 Retention 111b: No limit.
261 ///
262 UINT32 Limit : 3;
263 UINT32 Reserved1 : 7;
264 ///
265 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
266 ///
267 UINT32 IO_MWAIT : 1;
268 UINT32 Reserved2 : 4;
269 ///
270 /// [Bit 15] CFG Lock (R/WO).
271 ///
272 UINT32 CFGLock : 1;
273 UINT32 Reserved5 : 10;
274 ///
275 /// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor
276 /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
277 /// auto-demote information.
278 ///
279 UINT32 C1StateAutoDemotionEnable : 1;
280 UINT32 Reserved6 : 1;
281 ///
282 /// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables
283 /// Undemotion from Demoted C1.
284 ///
285 UINT32 C1StateAutoUndemotionEnable : 1;
286 ///
287 /// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables
288 /// Package C state demotion.
289 ///
290 UINT32 PKGC_StateAutoDemotionEnable : 1;
291 UINT32 Reserved7 : 2;
292 UINT32 Reserved4 : 32;
293 } Bits;
294 ///
295 /// All bit fields as a 32-bit value
296 ///
297 UINT32 Uint32;
298 ///
299 /// All bit fields as a 64-bit value
300 ///
301 UINT64 Uint64;
302 } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;
303
304 /**
305 Module. Power Management IO Redirection in C-state (R/W).
306
307 @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)
308 @param EAX Lower 32-bits of MSR value.
309 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
310 @param EDX Upper 32-bits of MSR value.
311 Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
312
313 <b>Example usage</b>
314 @code
315 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;
316
317 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
318 AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
319 @endcode
320 @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
321 **/
322 #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4
323
324 /**
325 MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE
326 **/
327 typedef union {
328 ///
329 /// Individual bit fields
330 ///
331 struct {
332 ///
333 /// [Bits 15:0] LVL_2 Base Address (R/W).
334 ///
335 UINT32 Lvl2Base : 16;
336 ///
337 /// [Bits 22:16] C-State Range (R/W) The IO-port block size in which
338 /// IO-redirection will be executed (0-127). Should be programmed based on
339 /// the number of LVLx registers existing in the chipset.
340 ///
341 UINT32 CStateRange : 7;
342 UINT32 Reserved3 : 9;
343 UINT32 Reserved2 : 32;
344 } Bits;
345 ///
346 /// All bit fields as a 32-bit value
347 ///
348 UINT32 Uint32;
349 ///
350 /// All bit fields as a 64-bit value
351 ///
352 UINT64 Uint64;
353 } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;
354
355 /**
356 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
357 handler to handle unsuccessful read of this MSR.
358
359 @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)
360 @param EAX Lower 32-bits of MSR value.
361 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
362 @param EDX Upper 32-bits of MSR value.
363 Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
364
365 <b>Example usage</b>
366 @code
367 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;
368
369 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
370 AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
371 @endcode
372 @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
373 **/
374 #define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C
375
376 /**
377 MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG
378 **/
379 typedef union {
380 ///
381 /// Individual bit fields
382 ///
383 struct {
384 ///
385 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
386 /// MSR, the configuration of AES instruction set availability is as
387 /// follows: 11b: AES instructions are not available until next RESET.
388 /// otherwise, AES instructions are available. Note, AES instruction set
389 /// is not available if read is unsuccessful. If the configuration is not
390 /// 01b, AES instruction can be mis-configured if a privileged agent
391 /// unintentionally writes 11b.
392 ///
393 UINT32 AESConfiguration : 2;
394 UINT32 Reserved1 : 30;
395 UINT32 Reserved2 : 32;
396 } Bits;
397 ///
398 /// All bit fields as a 32-bit value
399 ///
400 UINT32 Uint32;
401 ///
402 /// All bit fields as a 64-bit value
403 ///
404 UINT64 Uint64;
405 } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;
406
407 /**
408 Thread. MISC_FEATURE_ENABLES.
409
410 @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)
411 @param EAX Lower 32-bits of MSR value.
412 Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
413 @param EDX Upper 32-bits of MSR value.
414 Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
415
416 <b>Example usage</b>
417 @code
418 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;
419
420 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);
421 AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);
422 @endcode
423 **/
424 #define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140
425
426 /**
427 MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES
428 **/
429 typedef union {
430 ///
431 /// Individual bit fields
432 ///
433 struct {
434 UINT32 Reserved1 : 1;
435 ///
436 /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and
437 /// MWAIT instructions do not cause invalid-opcode exceptions when
438 /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed
439 /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state
440 /// other than C0 or C1, the instruction operates as if EAX indicated the
441 /// C-state C1.
442 ///
443 UINT32 UserModeMonitorAndMwait : 1;
444 UINT32 Reserved2 : 30;
445 UINT32 Reserved3 : 32;
446 } Bits;
447 ///
448 /// All bit fields as a 32-bit value
449 ///
450 UINT32 Uint32;
451 ///
452 /// All bit fields as a 64-bit value
453 ///
454 UINT64 Uint64;
455 } MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;
456
457 /**
458 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
459 Enhancement. Accessible only while in SMM.
460
461 @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)
462 @param EAX Lower 32-bits of MSR value.
463 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
464 @param EDX Upper 32-bits of MSR value.
465 Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
466
467 <b>Example usage</b>
468 @code
469 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;
470
471 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);
472 AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);
473 @endcode
474 @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
475 **/
476 #define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D
477
478 /**
479 MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP
480 **/
481 typedef union {
482 ///
483 /// Individual bit fields
484 ///
485 struct {
486 ///
487 /// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is
488 /// set, that bank supports Enhanced MCA (Default all 0; does not support
489 /// EMCA).
490 ///
491 UINT32 BankSupport : 32;
492 UINT32 Reserved4 : 24;
493 ///
494 /// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.
495 ///
496 UINT32 TargetedSMI : 1;
497 ///
498 /// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature
499 /// is supported.
500 ///
501 UINT32 SMM_CPU_SVRSTR : 1;
502 ///
503 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
504 /// SMM code access restriction is supported and a host-space interface
505 /// available to SMM handler.
506 ///
507 UINT32 SMM_Code_Access_Chk : 1;
508 ///
509 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
510 /// SMM long flow indicator is supported and a host-space interface
511 /// available to SMM handler.
512 ///
513 UINT32 Long_Flow_Indication : 1;
514 UINT32 Reserved3 : 4;
515 } Bits;
516 ///
517 /// All bit fields as a 64-bit value
518 ///
519 UINT64 Uint64;
520 } MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;
521
522 /**
523 Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor
524 functions to be enabled and disabled.
525
526 @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)
527 @param EAX Lower 32-bits of MSR value.
528 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
529 @param EDX Upper 32-bits of MSR value.
530 Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
531
532 <b>Example usage</b>
533 @code
534 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;
535
536 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
537 AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
538 @endcode
539 @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
540 **/
541 #define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0
542
543 /**
544 MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE
545 **/
546 typedef union {
547 ///
548 /// Individual bit fields
549 ///
550 struct {
551 ///
552 /// [Bit 0] Fast-Strings Enable.
553 ///
554 UINT32 FastStrings : 1;
555 UINT32 Reserved1 : 2;
556 ///
557 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value
558 /// is 1.
559 ///
560 UINT32 AutomaticThermalControlCircuit : 1;
561 UINT32 Reserved2 : 3;
562 ///
563 /// [Bit 7] Performance Monitoring Available (R).
564 ///
565 UINT32 PerformanceMonitoring : 1;
566 UINT32 Reserved3 : 3;
567 ///
568 /// [Bit 11] Branch Trace Storage Unavailable (RO).
569 ///
570 UINT32 BTS : 1;
571 ///
572 /// [Bit 12] Processor Event Based Sampling Unavailable (RO).
573 ///
574 UINT32 PEBS : 1;
575 UINT32 Reserved4 : 3;
576 ///
577 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).
578 ///
579 UINT32 EIST : 1;
580 UINT32 Reserved5 : 1;
581 ///
582 /// [Bit 18] ENABLE MONITOR FSM (R/W).
583 ///
584 UINT32 MONITOR : 1;
585 UINT32 Reserved6 : 3;
586 ///
587 /// [Bit 22] Limit CPUID Maxval (R/W).
588 ///
589 UINT32 LimitCpuidMaxval : 1;
590 ///
591 /// [Bit 23] xTPR Message Disable (R/W).
592 ///
593 UINT32 xTPR_Message_Disable : 1;
594 UINT32 Reserved7 : 8;
595 UINT32 Reserved8 : 2;
596 ///
597 /// [Bit 34] XD Bit Disable (R/W).
598 ///
599 UINT32 XD : 1;
600 UINT32 Reserved9 : 3;
601 ///
602 /// [Bit 38] Turbo Mode Disable (R/W).
603 ///
604 UINT32 TurboModeDisable : 1;
605 UINT32 Reserved10 : 25;
606 } Bits;
607 ///
608 /// All bit fields as a 64-bit value
609 ///
610 UINT64 Uint64;
611 } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;
612
613 /**
614 Package.
615
616 @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)
617 @param EAX Lower 32-bits of MSR value.
618 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
619 @param EDX Upper 32-bits of MSR value.
620 Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
621
622 <b>Example usage</b>
623 @code
624 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;
625
626 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
627 AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
628 @endcode
629 @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
630 **/
631 #define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2
632
633 /**
634 MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET
635 **/
636 typedef union {
637 ///
638 /// Individual bit fields
639 ///
640 struct {
641 UINT32 Reserved1 : 16;
642 ///
643 /// [Bits 23:16] Temperature Target (R).
644 ///
645 UINT32 TemperatureTarget : 8;
646 ///
647 /// [Bits 29:24] Target Offset (R/W).
648 ///
649 UINT32 TargetOffset : 6;
650 UINT32 Reserved2 : 2;
651 UINT32 Reserved3 : 32;
652 } Bits;
653 ///
654 /// All bit fields as a 32-bit value
655 ///
656 UINT32 Uint32;
657 ///
658 /// All bit fields as a 64-bit value
659 ///
660 UINT64 Uint64;
661 } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;
662
663 /**
664 Miscellaneous Feature Control (R/W).
665
666 @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)
667 @param EAX Lower 32-bits of MSR value.
668 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
669 @param EDX Upper 32-bits of MSR value.
670 Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
671
672 <b>Example usage</b>
673 @code
674 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;
675
676 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);
677 AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);
678 @endcode
679 @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
680 **/
681 #define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4
682
683 /**
684 MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL
685 **/
686 typedef union {
687 ///
688 /// Individual bit fields
689 ///
690 struct {
691 ///
692 /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the
693 /// L1 data cache prefetcher.
694 ///
695 UINT32 DCUHardwarePrefetcherDisable : 1;
696 ///
697 /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the
698 /// L2 hardware prefetcher.
699 ///
700 UINT32 L2HardwarePrefetcherDisable : 1;
701 UINT32 Reserved1 : 30;
702 UINT32 Reserved2 : 32;
703 } Bits;
704 ///
705 /// All bit fields as a 32-bit value
706 ///
707 UINT32 Uint32;
708 ///
709 /// All bit fields as a 64-bit value
710 ///
711 UINT64 Uint64;
712 } MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;
713
714 /**
715 Shared. Offcore Response Event Select Register (R/W).
716
717 @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
718 @param EAX Lower 32-bits of MSR value.
719 @param EDX Upper 32-bits of MSR value.
720
721 <b>Example usage</b>
722 @code
723 UINT64 Msr;
724
725 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
726 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
727 @endcode
728 @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
729 **/
730 #define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6
731
732 /**
733 Shared. Offcore Response Event Select Register (R/W).
734
735 @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)
736 @param EAX Lower 32-bits of MSR value.
737 @param EDX Upper 32-bits of MSR value.
738
739 <b>Example usage</b>
740 @code
741 UINT64 Msr;
742
743 Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
744 AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
745 @endcode
746 @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
747 **/
748 #define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7
749
750 /**
751 Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).
752
753 @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)
754 @param EAX Lower 32-bits of MSR value.
755 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
756 @param EDX Upper 32-bits of MSR value.
757 Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
758
759 <b>Example usage</b>
760 @code
761 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;
762
763 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
764 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
765 @endcode
766 @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
767 **/
768 #define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD
769
770 /**
771 MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT
772 **/
773 typedef union {
774 ///
775 /// Individual bit fields
776 ///
777 struct {
778 UINT32 Reserved : 1;
779 ///
780 /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active
781 /// processor cores which operates under the maximum ratio limit for group
782 /// 0.
783 ///
784 UINT32 MaxCoresGroup0 : 7;
785 ///
786 /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo
787 /// ratio limit when the number of active cores are not more than the
788 /// group 0 maximum core count.
789 ///
790 UINT32 MaxRatioLimitGroup0 : 8;
791 ///
792 /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1
793 /// Group 1, which includes the specified number of additional cores plus
794 /// the cores in group 0, operates under the group 1 turbo max ratio limit
795 /// = "group 0 Max ratio limit" - "group ratio delta for group 1".
796 ///
797 UINT32 MaxIncrementalCoresGroup1 : 5;
798 ///
799 /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned
800 /// integer specifying the ratio decrement relative to the Max ratio limit
801 /// to Group 0.
802 ///
803 UINT32 DeltaRatioGroup1 : 3;
804 ///
805 /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2
806 /// Group 2, which includes the specified number of additional cores plus
807 /// all the cores in group 1, operates under the group 2 turbo max ratio
808 /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".
809 ///
810 UINT32 MaxIncrementalCoresGroup2 : 5;
811 ///
812 /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned
813 /// integer specifying the ratio decrement relative to the Max ratio limit
814 /// for Group 1.
815 ///
816 UINT32 DeltaRatioGroup2 : 3;
817 ///
818 /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3
819 /// Group 3, which includes the specified number of additional cores plus
820 /// all the cores in group 2, operates under the group 3 turbo max ratio
821 /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".
822 ///
823 UINT32 MaxIncrementalCoresGroup3 : 5;
824 ///
825 /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned
826 /// integer specifying the ratio decrement relative to the Max ratio limit
827 /// for Group 2.
828 ///
829 UINT32 DeltaRatioGroup3 : 3;
830 ///
831 /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4
832 /// Group 4, which includes the specified number of additional cores plus
833 /// all the cores in group 3, operates under the group 4 turbo max ratio
834 /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".
835 ///
836 UINT32 MaxIncrementalCoresGroup4 : 5;
837 ///
838 /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned
839 /// integer specifying the ratio decrement relative to the Max ratio limit
840 /// for Group 3.
841 ///
842 UINT32 DeltaRatioGroup4 : 3;
843 ///
844 /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5
845 /// Group 5, which includes the specified number of additional cores plus
846 /// all the cores in group 4, operates under the group 5 turbo max ratio
847 /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".
848 ///
849 UINT32 MaxIncrementalCoresGroup5 : 5;
850 ///
851 /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned
852 /// integer specifying the ratio decrement relative to the Max ratio limit
853 /// for Group 4.
854 ///
855 UINT32 DeltaRatioGroup5 : 3;
856 ///
857 /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6
858 /// Group 6, which includes the specified number of additional cores plus
859 /// all the cores in group 5, operates under the group 6 turbo max ratio
860 /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".
861 ///
862 UINT32 MaxIncrementalCoresGroup6 : 5;
863 ///
864 /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned
865 /// integer specifying the ratio decrement relative to the Max ratio limit
866 /// for Group 5.
867 ///
868 UINT32 DeltaRatioGroup6 : 3;
869 } Bits;
870 ///
871 /// All bit fields as a 64-bit value
872 ///
873 UINT64 Uint64;
874 } MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;
875
876 /**
877 Thread. Last Branch Record Filtering Select Register (R/W).
878
879 @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)
880 @param EAX Lower 32-bits of MSR value.
881 @param EDX Upper 32-bits of MSR value.
882
883 <b>Example usage</b>
884 @code
885 UINT64 Msr;
886
887 Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
888 AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
889 @endcode
890 @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
891 **/
892 #define MSR_XEON_PHI_LBR_SELECT 0x000001C8
893
894 /**
895 MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT
896 **/
897 typedef union {
898 ///
899 /// Individual bit fields
900 ///
901 struct {
902 ///
903 /// [Bit 0] CPL_EQ_0.
904 ///
905 UINT32 CPL_EQ_0 : 1;
906 ///
907 /// [Bit 1] CPL_NEQ_0.
908 ///
909 UINT32 CPL_NEQ_0 : 1;
910 ///
911 /// [Bit 2] JCC.
912 ///
913 UINT32 JCC : 1;
914 ///
915 /// [Bit 3] NEAR_REL_CALL.
916 ///
917 UINT32 NEAR_REL_CALL : 1;
918 ///
919 /// [Bit 4] NEAR_IND_CALL.
920 ///
921 UINT32 NEAR_IND_CALL : 1;
922 ///
923 /// [Bit 5] NEAR_RET.
924 ///
925 UINT32 NEAR_RET : 1;
926 ///
927 /// [Bit 6] NEAR_IND_JMP.
928 ///
929 UINT32 NEAR_IND_JMP : 1;
930 ///
931 /// [Bit 7] NEAR_REL_JMP.
932 ///
933 UINT32 NEAR_REL_JMP : 1;
934 ///
935 /// [Bit 8] FAR_BRANCH.
936 ///
937 UINT32 FAR_BRANCH : 1;
938 UINT32 Reserved1 : 23;
939 UINT32 Reserved2 : 32;
940 } Bits;
941 ///
942 /// All bit fields as a 32-bit value
943 ///
944 UINT32 Uint32;
945 ///
946 /// All bit fields as a 64-bit value
947 ///
948 UINT64 Uint64;
949 } MSR_XEON_PHI_LBR_SELECT_REGISTER;
950
951 /**
952 Thread. Last Branch Record Stack TOS (R/W).
953
954 @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)
955 @param EAX Lower 32-bits of MSR value.
956 @param EDX Upper 32-bits of MSR value.
957
958 <b>Example usage</b>
959 @code
960 UINT64 Msr;
961
962 Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
963 AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
964 @endcode
965 @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
966 **/
967 #define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9
968
969 /**
970 Thread. Last Exception Record From Linear IP (R).
971
972 @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)
973 @param EAX Lower 32-bits of MSR value.
974 @param EDX Upper 32-bits of MSR value.
975
976 <b>Example usage</b>
977 @code
978 UINT64 Msr;
979
980 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
981 @endcode
982 @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
983 **/
984 #define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD
985
986 /**
987 Thread. Last Exception Record To Linear IP (R).
988
989 @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)
990 @param EAX Lower 32-bits of MSR value.
991 @param EDX Upper 32-bits of MSR value.
992
993 <b>Example usage</b>
994 @code
995 UINT64 Msr;
996
997 Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
998 @endcode
999 @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
1000 **/
1001 #define MSR_XEON_PHI_LER_TO_LIP 0x000001DE
1002
1003 /**
1004 Thread. See Table 2-2.
1005
1006 @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
1007 @param EAX Lower 32-bits of MSR value.
1008 @param EDX Upper 32-bits of MSR value.
1009
1010 <b>Example usage</b>
1011 @code
1012 UINT64 Msr;
1013
1014 Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
1015 AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
1016 @endcode
1017 @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
1018 **/
1019 #define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1
1020
1021 /**
1022 Package. Note: C-state values are processor specific C-state code names,
1023 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3
1024 Residency Counter. (R/O).
1025
1026 @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)
1027 @param EAX Lower 32-bits of MSR value.
1028 @param EDX Upper 32-bits of MSR value.
1029
1030 <b>Example usage</b>
1031 @code
1032 UINT64 Msr;
1033
1034 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
1035 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
1036 @endcode
1037 @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
1038 **/
1039 #define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8
1040
1041 /**
1042 Package. Package C6 Residency Counter. (R/O).
1043
1044 @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)
1045 @param EAX Lower 32-bits of MSR value.
1046 @param EDX Upper 32-bits of MSR value.
1047
1048 <b>Example usage</b>
1049 @code
1050 UINT64 Msr;
1051
1052 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
1053 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
1054 @endcode
1055 @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
1056 **/
1057 #define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9
1058
1059 /**
1060 Package. Package C7 Residency Counter. (R/O).
1061
1062 @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)
1063 @param EAX Lower 32-bits of MSR value.
1064 @param EDX Upper 32-bits of MSR value.
1065
1066 <b>Example usage</b>
1067 @code
1068 UINT64 Msr;
1069
1070 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
1071 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
1072 @endcode
1073 @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
1074 **/
1075 #define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA
1076
1077 /**
1078 Module. Note: C-state values are processor specific C-state code names,
1079 unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0
1080 Residency Counter. (R/O).
1081
1082 @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)
1083 @param EAX Lower 32-bits of MSR value.
1084 @param EDX Upper 32-bits of MSR value.
1085
1086 <b>Example usage</b>
1087 @code
1088 UINT64 Msr;
1089
1090 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
1091 AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
1092 @endcode
1093 @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.
1094 **/
1095 #define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC
1096
1097 /**
1098 Module. Module C6 Residency Counter. (R/O).
1099
1100 @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)
1101 @param EAX Lower 32-bits of MSR value.
1102 @param EDX Upper 32-bits of MSR value.
1103
1104 <b>Example usage</b>
1105 @code
1106 UINT64 Msr;
1107
1108 Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
1109 AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
1110 @endcode
1111 @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.
1112 **/
1113 #define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD
1114
1115 /**
1116 Core. Note: C-state values are processor specific C-state code names,
1117 unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6
1118 Residency Counter. (R/O).
1119
1120 @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)
1121 @param EAX Lower 32-bits of MSR value.
1122 @param EDX Upper 32-bits of MSR value.
1123
1124 <b>Example usage</b>
1125 @code
1126 UINT64 Msr;
1127
1128 Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
1129 AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
1130 @endcode
1131 @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
1132 **/
1133 #define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF
1134
1135 /**
1136 Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
1137
1138 @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
1139 @param EAX Lower 32-bits of MSR value.
1140 @param EDX Upper 32-bits of MSR value.
1141
1142 <b>Example usage</b>
1143 @code
1144 UINT64 Msr;
1145
1146 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
1147 @endcode
1148 @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
1149 **/
1150 #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C
1151
1152 /**
1153 Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
1154 2-2.
1155
1156 @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
1157 @param EAX Lower 32-bits of MSR value.
1158 @param EDX Upper 32-bits of MSR value.
1159
1160 <b>Example usage</b>
1161 @code
1162 UINT64 Msr;
1163
1164 Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
1165 @endcode
1166 @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
1167 **/
1168 #define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491
1169
1170 /**
1171 Package. Unit Multipliers used in RAPL Interfaces (R/O).
1172
1173 @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)
1174 @param EAX Lower 32-bits of MSR value.
1175 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
1176 @param EDX Upper 32-bits of MSR value.
1177 Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
1178
1179 <b>Example usage</b>
1180 @code
1181 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;
1182
1183 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
1184 @endcode
1185 @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
1186 **/
1187 #define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606
1188
1189 /**
1190 MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT
1191 **/
1192 typedef union {
1193 ///
1194 /// Individual bit fields
1195 ///
1196 struct {
1197 ///
1198 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
1199 ///
1200 UINT32 PowerUnits : 4;
1201 UINT32 Reserved1 : 4;
1202 ///
1203 /// [Bits 12:8] Package. Energy Status Units Energy related information
1204 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
1205 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
1206 /// micro-joules).
1207 ///
1208 UINT32 EnergyStatusUnits : 5;
1209 UINT32 Reserved2 : 3;
1210 ///
1211 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
1212 /// Interfaces.".
1213 ///
1214 UINT32 TimeUnits : 4;
1215 UINT32 Reserved3 : 12;
1216 UINT32 Reserved4 : 32;
1217 } Bits;
1218 ///
1219 /// All bit fields as a 32-bit value
1220 ///
1221 UINT32 Uint32;
1222 ///
1223 /// All bit fields as a 64-bit value
1224 ///
1225 UINT64 Uint64;
1226 } MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;
1227
1228 /**
1229 Package. Note: C-state values are processor specific C-state code names,
1230 unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2
1231 Residency Counter. (R/O).
1232
1233 @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)
1234 @param EAX Lower 32-bits of MSR value.
1235 @param EDX Upper 32-bits of MSR value.
1236
1237 <b>Example usage</b>
1238 @code
1239 UINT64 Msr;
1240
1241 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
1242 AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
1243 @endcode
1244 @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
1245 **/
1246 #define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D
1247
1248 /**
1249 Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
1250 RAPL Domain.".
1251
1252 @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)
1253 @param EAX Lower 32-bits of MSR value.
1254 @param EDX Upper 32-bits of MSR value.
1255
1256 <b>Example usage</b>
1257 @code
1258 UINT64 Msr;
1259
1260 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
1261 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
1262 @endcode
1263 @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
1264 **/
1265 #define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610
1266
1267 /**
1268 Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1269
1270 @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)
1271 @param EAX Lower 32-bits of MSR value.
1272 @param EDX Upper 32-bits of MSR value.
1273
1274 <b>Example usage</b>
1275 @code
1276 UINT64 Msr;
1277
1278 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
1279 @endcode
1280 @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
1281 **/
1282 #define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611
1283
1284 /**
1285 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
1286
1287 @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)
1288 @param EAX Lower 32-bits of MSR value.
1289 @param EDX Upper 32-bits of MSR value.
1290
1291 <b>Example usage</b>
1292 @code
1293 UINT64 Msr;
1294
1295 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
1296 @endcode
1297 @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
1298 **/
1299 #define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613
1300
1301 /**
1302 Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
1303 Domain.".
1304
1305 @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)
1306 @param EAX Lower 32-bits of MSR value.
1307 @param EDX Upper 32-bits of MSR value.
1308
1309 <b>Example usage</b>
1310 @code
1311 UINT64 Msr;
1312
1313 Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
1314 AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
1315 @endcode
1316 @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
1317 **/
1318 #define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614
1319
1320 /**
1321 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
1322 Domain.".
1323
1324 @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)
1325 @param EAX Lower 32-bits of MSR value.
1326 @param EDX Upper 32-bits of MSR value.
1327
1328 <b>Example usage</b>
1329 @code
1330 UINT64 Msr;
1331
1332 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
1333 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
1334 @endcode
1335 @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
1336 **/
1337 #define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618
1338
1339 /**
1340 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".
1341
1342 @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)
1343 @param EAX Lower 32-bits of MSR value.
1344 @param EDX Upper 32-bits of MSR value.
1345
1346 <b>Example usage</b>
1347 @code
1348 UINT64 Msr;
1349
1350 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
1351 @endcode
1352 @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
1353 **/
1354 #define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619
1355
1356 /**
1357 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
1358 RAPL Domain.".
1359
1360 @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)
1361 @param EAX Lower 32-bits of MSR value.
1362 @param EDX Upper 32-bits of MSR value.
1363
1364 <b>Example usage</b>
1365 @code
1366 UINT64 Msr;
1367
1368 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
1369 @endcode
1370 @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
1371 **/
1372 #define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B
1373
1374 /**
1375 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
1376
1377 @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)
1378 @param EAX Lower 32-bits of MSR value.
1379 @param EDX Upper 32-bits of MSR value.
1380
1381 <b>Example usage</b>
1382 @code
1383 UINT64 Msr;
1384
1385 Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
1386 AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
1387 @endcode
1388 @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
1389 **/
1390 #define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C
1391
1392 /**
1393 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
1394 fields represent the widest possible range of uncore frequencies. Writing to
1395 these fields allows software to control the minimum and the maximum
1396 frequency that hardware will select.
1397
1398 @param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)
1399 @param EAX Lower 32-bits of MSR value.
1400 Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
1401 @param EDX Upper 32-bits of MSR value.
1402 Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
1403
1404 <b>Example usage</b>
1405 @code
1406 MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;
1407
1408 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);
1409 AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
1410 @endcode
1411 **/
1412 #define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620
1413
1414 /**
1415 MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
1416 **/
1417 typedef union {
1418 ///
1419 /// Individual bit fields
1420 ///
1421 struct {
1422 ///
1423 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
1424 /// LLC/Ring.
1425 ///
1426 UINT32 MAX_RATIO : 7;
1427 UINT32 Reserved1 : 1;
1428 ///
1429 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
1430 /// possible ratio of the LLC/Ring.
1431 ///
1432 UINT32 MIN_RATIO : 7;
1433 UINT32 Reserved2 : 17;
1434 UINT32 Reserved3 : 32;
1435 } Bits;
1436 ///
1437 /// All bit fields as a 32-bit value
1438 ///
1439 UINT32 Uint32;
1440 ///
1441 /// All bit fields as a 64-bit value
1442 ///
1443 UINT64 Uint64;
1444 } MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;
1445
1446 /**
1447 Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
1448 RAPL Domains.".
1449
1450 @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
1451 @param EAX Lower 32-bits of MSR value.
1452 @param EDX Upper 32-bits of MSR value.
1453
1454 <b>Example usage</b>
1455 @code
1456 UINT64 Msr;
1457
1458 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
1459 AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
1460 @endcode
1461 @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
1462 **/
1463 #define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638
1464
1465 /**
1466 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL
1467 Domains.".
1468
1469 @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)
1470 @param EAX Lower 32-bits of MSR value.
1471 @param EDX Upper 32-bits of MSR value.
1472
1473 <b>Example usage</b>
1474 @code
1475 UINT64 Msr;
1476
1477 Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
1478 @endcode
1479 @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
1480 **/
1481 #define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639
1482
1483 /**
1484 Package. Base TDP Ratio (R/O) See Table 2-24.
1485
1486 @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
1487 @param EAX Lower 32-bits of MSR value.
1488 @param EDX Upper 32-bits of MSR value.
1489
1490 <b>Example usage</b>
1491 @code
1492 UINT64 Msr;
1493
1494 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
1495 @endcode
1496 @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
1497 **/
1498 #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648
1499
1500 /**
1501 Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.
1502
1503 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
1504 @param EAX Lower 32-bits of MSR value.
1505 @param EDX Upper 32-bits of MSR value.
1506
1507 <b>Example usage</b>
1508 @code
1509 UINT64 Msr;
1510
1511 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
1512 @endcode
1513 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
1514 **/
1515 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649
1516
1517 /**
1518 Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.
1519
1520 @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
1521 @param EAX Lower 32-bits of MSR value.
1522 @param EDX Upper 32-bits of MSR value.
1523
1524 <b>Example usage</b>
1525 @code
1526 UINT64 Msr;
1527
1528 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
1529 @endcode
1530 @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
1531 **/
1532 #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A
1533
1534 /**
1535 Package. ConfigTDP Control (R/W) See Table 2-24.
1536
1537 @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
1538 @param EAX Lower 32-bits of MSR value.
1539 @param EDX Upper 32-bits of MSR value.
1540
1541 <b>Example usage</b>
1542 @code
1543 UINT64 Msr;
1544
1545 Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
1546 AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
1547 @endcode
1548 @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
1549 **/
1550 #define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B
1551
1552 /**
1553 Package. ConfigTDP Control (R/W) See Table 2-24.
1554
1555 @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
1556 @param EAX Lower 32-bits of MSR value.
1557 @param EDX Upper 32-bits of MSR value.
1558
1559 <b>Example usage</b>
1560 @code
1561 UINT64 Msr;
1562
1563 Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
1564 AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
1565 @endcode
1566 @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
1567 **/
1568 #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C
1569
1570 /**
1571 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
1572 refers to processor core frequency).
1573
1574 @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)
1575 @param EAX Lower 32-bits of MSR value.
1576 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1577 @param EDX Upper 32-bits of MSR value.
1578 Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
1579
1580 <b>Example usage</b>
1581 @code
1582 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;
1583
1584 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
1585 AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
1586 @endcode
1587 @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
1588 **/
1589 #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690
1590
1591 /**
1592 MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS
1593 **/
1594 typedef union {
1595 ///
1596 /// Individual bit fields
1597 ///
1598 struct {
1599 ///
1600 /// [Bit 0] PROCHOT Status (R0).
1601 ///
1602 UINT32 PROCHOT_Status : 1;
1603 ///
1604 /// [Bit 1] Thermal Status (R0).
1605 ///
1606 UINT32 ThermalStatus : 1;
1607 UINT32 Reserved1 : 4;
1608 ///
1609 /// [Bit 6] VR Therm Alert Status (R0).
1610 ///
1611 UINT32 VRThermAlertStatus : 1;
1612 UINT32 Reserved2 : 1;
1613 ///
1614 /// [Bit 8] Electrical Design Point Status (R0).
1615 ///
1616 UINT32 ElectricalDesignPointStatus : 1;
1617 UINT32 Reserved3 : 23;
1618 UINT32 Reserved4 : 32;
1619 } Bits;
1620 ///
1621 /// All bit fields as a 32-bit value
1622 ///
1623 UINT32 Uint32;
1624 ///
1625 /// All bit fields as a 64-bit value
1626 ///
1627 UINT64 Uint64;
1628 } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;
1629
1630 #endif
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