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1 /** @file
2 This header file contains all of the PXE type definitions,
3 structure prototypes, global variables and constants that
4 are needed for porting PXE to EFI.
5
6 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
8
9 @par Revision Reference:
10 32/64-bit PXE specification:
11 alpha-4, 99-Dec-17.
12
13 **/
14
15 #ifndef __EFI_PXE_H__
16 #define __EFI_PXE_H__
17
18 #pragma pack(1)
19
20 #define PXE_BUSTYPE(a, b, c, d) \
21 ( \
22 (((PXE_UINT32) (d) & 0xFF) << 24) | (((PXE_UINT32) (c) & 0xFF) << 16) | (((PXE_UINT32) (b) & 0xFF) << 8) | \
23 ((PXE_UINT32) (a) & 0xFF) \
24 )
25
26 ///
27 /// UNDI ROM ID and devive ID signature.
28 ///
29 #define PXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E')
30
31 ///
32 /// BUS ROM ID signatures.
33 ///
34 #define PXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R')
35 #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R')
36 #define PXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R')
37 #define PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4')
38
39 #define PXE_SWAP_UINT16(n) ((((PXE_UINT16) (n) & 0x00FF) << 8) | (((PXE_UINT16) (n) & 0xFF00) >> 8))
40
41 #define PXE_SWAP_UINT32(n) \
42 ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \
43 (((PXE_UINT32)(n) & 0x0000FF00) << 8) | \
44 (((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \
45 (((PXE_UINT32)(n) & 0xFF000000) >> 24))
46
47 #define PXE_SWAP_UINT64(n) \
48 ((((PXE_UINT64)(n) & 0x00000000000000FFULL) << 56) | \
49 (((PXE_UINT64)(n) & 0x000000000000FF00ULL) << 40) | \
50 (((PXE_UINT64)(n) & 0x0000000000FF0000ULL) << 24) | \
51 (((PXE_UINT64)(n) & 0x00000000FF000000ULL) << 8) | \
52 (((PXE_UINT64)(n) & 0x000000FF00000000ULL) >> 8) | \
53 (((PXE_UINT64)(n) & 0x0000FF0000000000ULL) >> 24) | \
54 (((PXE_UINT64)(n) & 0x00FF000000000000ULL) >> 40) | \
55 (((PXE_UINT64)(n) & 0xFF00000000000000ULL) >> 56))
56
57 #define PXE_CPBSIZE_NOT_USED 0 ///< zero
58 #define PXE_DBSIZE_NOT_USED 0 ///< zero
59 #define PXE_CPBADDR_NOT_USED (PXE_UINT64) 0 ///< zero
60 #define PXE_DBADDR_NOT_USED (PXE_UINT64) 0 ///< zero
61 #define PXE_CONST CONST
62
63 #define PXE_VOLATILE volatile
64
65 typedef VOID PXE_VOID;
66 typedef UINT8 PXE_UINT8;
67 typedef UINT16 PXE_UINT16;
68 typedef UINT32 PXE_UINT32;
69 typedef UINTN PXE_UINTN;
70
71 ///
72 /// Typedef unsigned long PXE_UINT64.
73 ///
74 typedef UINT64 PXE_UINT64;
75
76 typedef PXE_UINT8 PXE_BOOL;
77 #define PXE_FALSE 0 ///< zero
78 #define PXE_TRUE (!PXE_FALSE)
79
80 typedef PXE_UINT16 PXE_OPCODE;
81
82 ///
83 /// Return UNDI operational state.
84 ///
85 #define PXE_OPCODE_GET_STATE 0x0000
86
87 ///
88 /// Change UNDI operational state from Stopped to Started.
89 ///
90 #define PXE_OPCODE_START 0x0001
91
92 ///
93 /// Change UNDI operational state from Started to Stopped.
94 ///
95 #define PXE_OPCODE_STOP 0x0002
96
97 ///
98 /// Get UNDI initialization information.
99 ///
100 #define PXE_OPCODE_GET_INIT_INFO 0x0003
101
102 ///
103 /// Get NIC configuration information.
104 ///
105 #define PXE_OPCODE_GET_CONFIG_INFO 0x0004
106
107 ///
108 /// Changed UNDI operational state from Started to Initialized.
109 ///
110 #define PXE_OPCODE_INITIALIZE 0x0005
111
112 ///
113 /// Re-initialize the NIC H/W.
114 ///
115 #define PXE_OPCODE_RESET 0x0006
116
117 ///
118 /// Change the UNDI operational state from Initialized to Started.
119 ///
120 #define PXE_OPCODE_SHUTDOWN 0x0007
121
122 ///
123 /// Read & change state of external interrupt enables.
124 ///
125 #define PXE_OPCODE_INTERRUPT_ENABLES 0x0008
126
127 ///
128 /// Read & change state of packet receive filters.
129 ///
130 #define PXE_OPCODE_RECEIVE_FILTERS 0x0009
131
132 ///
133 /// Read & change station MAC address.
134 ///
135 #define PXE_OPCODE_STATION_ADDRESS 0x000A
136
137 ///
138 /// Read traffic statistics.
139 ///
140 #define PXE_OPCODE_STATISTICS 0x000B
141
142 ///
143 /// Convert multicast IP address to multicast MAC address.
144 ///
145 #define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C
146
147 ///
148 /// Read or change non-volatile storage on the NIC.
149 ///
150 #define PXE_OPCODE_NVDATA 0x000D
151
152 ///
153 /// Get & clear interrupt status.
154 ///
155 #define PXE_OPCODE_GET_STATUS 0x000E
156
157 ///
158 /// Fill media header in packet for transmit.
159 ///
160 #define PXE_OPCODE_FILL_HEADER 0x000F
161
162 ///
163 /// Transmit packet(s).
164 ///
165 #define PXE_OPCODE_TRANSMIT 0x0010
166
167 ///
168 /// Receive packet.
169 ///
170 #define PXE_OPCODE_RECEIVE 0x0011
171
172 ///
173 /// Last valid PXE UNDI OpCode number.
174 ///
175 #define PXE_OPCODE_LAST_VALID 0x0011
176
177 typedef PXE_UINT16 PXE_OPFLAGS;
178
179 #define PXE_OPFLAGS_NOT_USED 0x0000
180
181 //
182 // //////////////////////////////////////
183 // UNDI Get State
184 //
185 // No OpFlags
186
187 ////////////////////////////////////////
188 // UNDI Start
189 //
190 // No OpFlags
191
192 ////////////////////////////////////////
193 // UNDI Stop
194 //
195 // No OpFlags
196
197 ////////////////////////////////////////
198 // UNDI Get Init Info
199 //
200 // No Opflags
201
202 ////////////////////////////////////////
203 // UNDI Get Config Info
204 //
205 // No Opflags
206
207 ///
208 /// UNDI Initialize
209 ///
210 #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001
211 #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000
212 #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001
213
214 ///
215 ///
216 /// UNDI Reset
217 ///
218 #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001
219 #define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002
220
221 ///
222 /// UNDI Shutdown.
223 ///
224 /// No OpFlags.
225
226 ///
227 /// UNDI Interrupt Enables.
228 ///
229 ///
230 /// Select whether to enable or disable external interrupt signals.
231 /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS.
232 ///
233 #define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000
234 #define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000
235 #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000
236 #define PXE_OPFLAGS_INTERRUPT_READ 0x0000
237
238 ///
239 /// Enable receive interrupts. An external interrupt will be generated
240 /// after a complete non-error packet has been received.
241 ///
242 #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001
243
244 ///
245 /// Enable transmit interrupts. An external interrupt will be generated
246 /// after a complete non-error packet has been transmitted.
247 ///
248 #define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002
249
250 ///
251 /// Enable command interrupts. An external interrupt will be generated
252 /// when command execution stops.
253 ///
254 #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004
255
256 ///
257 /// Generate software interrupt. Setting this bit generates an external
258 /// interrupt, if it is supported by the hardware.
259 ///
260 #define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008
261
262 ///
263 /// UNDI Receive Filters.
264 ///
265 ///
266 /// Select whether to enable or disable receive filters.
267 /// Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE.
268 ///
269 #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000
270 #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000
271 #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000
272 #define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000
273
274 ///
275 /// To reset the contents of the multicast MAC address filter list,
276 /// set this OpFlag:
277 ///
278 #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000
279
280 ///
281 /// Enable unicast packet receiving. Packets sent to the current station
282 /// MAC address will be received.
283 ///
284 #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001
285
286 ///
287 /// Enable broadcast packet receiving. Packets sent to the broadcast
288 /// MAC address will be received.
289 ///
290 #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
291
292 ///
293 /// Enable filtered multicast packet receiving. Packets sent to any
294 /// of the multicast MAC addresses in the multicast MAC address filter
295 /// list will be received. If the filter list is empty, no multicast
296 ///
297 #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
298
299 ///
300 /// Enable promiscuous packet receiving. All packets will be received.
301 ///
302 #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
303
304 ///
305 /// Enable promiscuous multicast packet receiving. All multicast
306 /// packets will be received.
307 ///
308 #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
309
310 ///
311 /// UNDI Station Address.
312 ///
313 #define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000
314 #define PXE_OPFLAGS_STATION_ADDRESS_WRITE 0x0000
315 #define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001
316
317 ///
318 /// UNDI Statistics.
319 ///
320 #define PXE_OPFLAGS_STATISTICS_READ 0x0000
321 #define PXE_OPFLAGS_STATISTICS_RESET 0x0001
322
323 ///
324 /// UNDI MCast IP to MAC.
325 ///
326 ///
327 /// Identify the type of IP address in the CPB.
328 ///
329 #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003
330 #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000
331 #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001
332
333 ///
334 /// UNDI NvData.
335 ///
336 ///
337 /// Select the type of non-volatile data operation.
338 ///
339 #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001
340 #define PXE_OPFLAGS_NVDATA_READ 0x0000
341 #define PXE_OPFLAGS_NVDATA_WRITE 0x0001
342
343 ///
344 /// UNDI Get Status.
345 ///
346 ///
347 /// Return current interrupt status. This will also clear any interrupts
348 /// that are currently set. This can be used in a polling routine. The
349 /// interrupt flags are still set and cleared even when the interrupts
350 /// are disabled.
351 ///
352 #define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001
353
354 ///
355 /// Return list of transmitted buffers for recycling. Transmit buffers
356 /// must not be changed or unallocated until they have recycled. After
357 /// issuing a transmit command, wait for a transmit complete interrupt.
358 /// When a transmit complete interrupt is received, read the transmitted
359 /// buffers. Do not plan on getting one buffer per interrupt. Some
360 /// NICs and UNDIs may transmit multiple buffers per interrupt.
361 ///
362 #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002
363
364 ///
365 /// Return current media status.
366 ///
367 #define PXE_OPFLAGS_GET_MEDIA_STATUS 0x0004
368
369 ///
370 /// UNDI Fill Header.
371 ///
372 #define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001
373 #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001
374 #define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000
375
376 ///
377 /// UNDI Transmit.
378 ///
379 ///
380 /// S/W UNDI only. Return after the packet has been transmitted. A
381 /// transmit complete interrupt will still be generated and the transmit
382 /// buffer will have to be recycled.
383 ///
384 #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001
385 #define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001
386 #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000
387
388 #define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002
389 #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002
390 #define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000
391
392 ///
393 /// UNDI Receive.
394 ///
395 /// No OpFlags.
396 ///
397
398 ///
399 /// PXE STATFLAGS.
400 ///
401 typedef PXE_UINT16 PXE_STATFLAGS;
402
403 #define PXE_STATFLAGS_INITIALIZE 0x0000
404
405 ///
406 /// Common StatFlags that can be returned by all commands.
407 ///
408 ///
409 /// The COMMAND_COMPLETE and COMMAND_FAILED status flags must be
410 /// implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs
411 /// that support command queuing.
412 ///
413 #define PXE_STATFLAGS_STATUS_MASK 0xC000
414 #define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000
415 #define PXE_STATFLAGS_COMMAND_FAILED 0x8000
416 #define PXE_STATFLAGS_COMMAND_QUEUED 0x4000
417
418 ///
419 /// UNDI Get State.
420 ///
421 #define PXE_STATFLAGS_GET_STATE_MASK 0x0003
422 #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002
423 #define PXE_STATFLAGS_GET_STATE_STARTED 0x0001
424 #define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000
425
426 ///
427 /// UNDI Start.
428 ///
429 /// No additional StatFlags.
430 ///
431
432 ///
433 /// UNDI Get Init Info.
434 ///
435 #define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001
436 #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000
437 #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001
438
439 #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_MASK 0x0002
440 #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_NOT_SUPPORTED 0x0000
441 #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA_SUPPORTED 0x0002
442
443 ///
444 /// UNDI Initialize.
445 ///
446 #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001
447
448 ///
449 /// UNDI Reset.
450 ///
451 #define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001
452
453 ///
454 /// UNDI Shutdown.
455 ///
456 /// No additional StatFlags.
457
458 ///
459 /// UNDI Interrupt Enables.
460 ///
461 ///
462 /// If set, receive interrupts are enabled.
463 ///
464 #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001
465
466 ///
467 /// If set, transmit interrupts are enabled.
468 ///
469 #define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002
470
471 ///
472 /// If set, command interrupts are enabled.
473 ///
474 #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004
475
476 ///
477 /// UNDI Receive Filters.
478 ///
479
480 ///
481 /// If set, unicast packets will be received.
482 ///
483 #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001
484
485 ///
486 /// If set, broadcast packets will be received.
487 ///
488 #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002
489
490 ///
491 /// If set, multicast packets that match up with the multicast address
492 /// filter list will be received.
493 ///
494 #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004
495
496 ///
497 /// If set, all packets will be received.
498 ///
499 #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008
500
501 ///
502 /// If set, all multicast packets will be received.
503 ///
504 #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010
505
506 ///
507 /// UNDI Station Address.
508 ///
509 /// No additional StatFlags.
510 ///
511
512 ///
513 /// UNDI Statistics.
514 ///
515 /// No additional StatFlags.
516 ///
517
518 ///
519 //// UNDI MCast IP to MAC.
520 ////
521 //// No additional StatFlags.
522
523 ///
524 /// UNDI NvData.
525 ///
526 /// No additional StatFlags.
527 ///
528
529 ///
530 /// UNDI Get Status.
531 ///
532
533 ///
534 /// Use to determine if an interrupt has occurred.
535 ///
536 #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F
537 #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000
538
539 ///
540 /// If set, at least one receive interrupt occurred.
541 ///
542 #define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001
543
544 ///
545 /// If set, at least one transmit interrupt occurred.
546 ///
547 #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002
548
549 ///
550 /// If set, at least one command interrupt occurred.
551 ///
552 #define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004
553
554 ///
555 /// If set, at least one software interrupt occurred.
556 ///
557 #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008
558
559 ///
560 /// This flag is set if the transmitted buffer queue is empty. This flag
561 /// will be set if all transmitted buffer addresses get written into the DB.
562 ///
563 #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010
564
565 ///
566 /// This flag is set if no transmitted buffer addresses were written
567 /// into the DB. (This could be because DBsize was too small.)
568 ///
569 #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020
570
571 ///
572 /// This flag is set if there is no media detected.
573 ///
574 #define PXE_STATFLAGS_GET_STATUS_NO_MEDIA 0x0040
575
576 ///
577 /// UNDI Fill Header.
578 ///
579 /// No additional StatFlags.
580 ///
581
582 ///
583 /// UNDI Transmit.
584 ///
585 /// No additional StatFlags.
586
587 ///
588 /// UNDI Receive
589 /// .
590
591 ///
592 /// No additional StatFlags.
593 ///
594 typedef PXE_UINT16 PXE_STATCODE;
595
596 #define PXE_STATCODE_INITIALIZE 0x0000
597
598 ///
599 /// Common StatCodes returned by all UNDI commands, UNDI protocol functions
600 /// and BC protocol functions.
601 ///
602 #define PXE_STATCODE_SUCCESS 0x0000
603
604 #define PXE_STATCODE_INVALID_CDB 0x0001
605 #define PXE_STATCODE_INVALID_CPB 0x0002
606 #define PXE_STATCODE_BUSY 0x0003
607 #define PXE_STATCODE_QUEUE_FULL 0x0004
608 #define PXE_STATCODE_ALREADY_STARTED 0x0005
609 #define PXE_STATCODE_NOT_STARTED 0x0006
610 #define PXE_STATCODE_NOT_SHUTDOWN 0x0007
611 #define PXE_STATCODE_ALREADY_INITIALIZED 0x0008
612 #define PXE_STATCODE_NOT_INITIALIZED 0x0009
613 #define PXE_STATCODE_DEVICE_FAILURE 0x000A
614 #define PXE_STATCODE_NVDATA_FAILURE 0x000B
615 #define PXE_STATCODE_UNSUPPORTED 0x000C
616 #define PXE_STATCODE_BUFFER_FULL 0x000D
617 #define PXE_STATCODE_INVALID_PARAMETER 0x000E
618 #define PXE_STATCODE_INVALID_UNDI 0x000F
619 #define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010
620 #define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011
621 #define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012
622 #define PXE_STATCODE_NO_DATA 0x0013
623
624 typedef PXE_UINT16 PXE_IFNUM;
625
626 ///
627 /// This interface number must be passed to the S/W UNDI Start command.
628 ///
629 #define PXE_IFNUM_START 0x0000
630
631 ///
632 /// This interface number is returned by the S/W UNDI Get State and
633 /// Start commands if information in the CDB, CPB or DB is invalid.
634 ///
635 #define PXE_IFNUM_INVALID 0x0000
636
637 typedef PXE_UINT16 PXE_CONTROL;
638
639 ///
640 /// Setting this flag directs the UNDI to queue this command for later
641 /// execution if the UNDI is busy and it supports command queuing.
642 /// If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error
643 /// is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL
644 /// error is returned.
645 ///
646 #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002
647
648 ///
649 /// These two bit values are used to determine if there are more UNDI
650 /// CDB structures following this one. If the link bit is set, there
651 /// must be a CDB structure following this one. Execution will start
652 /// on the next CDB structure as soon as this one completes successfully.
653 /// If an error is generated by this command, execution will stop.
654 ///
655 #define PXE_CONTROL_LINK 0x0001
656 #define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000
657
658 typedef PXE_UINT8 PXE_FRAME_TYPE;
659
660 #define PXE_FRAME_TYPE_NONE 0x00
661 #define PXE_FRAME_TYPE_UNICAST 0x01
662 #define PXE_FRAME_TYPE_BROADCAST 0x02
663 #define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03
664 #define PXE_FRAME_TYPE_PROMISCUOUS 0x04
665 #define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05
666
667 #define PXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST
668
669 typedef PXE_UINT32 PXE_IPV4;
670
671 typedef PXE_UINT32 PXE_IPV6[4];
672 #define PXE_MAC_LENGTH 32
673
674 typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH];
675
676 typedef PXE_UINT8 PXE_IFTYPE;
677 typedef UINT16 PXE_MEDIA_PROTOCOL;
678
679 ///
680 /// This information is from the ARP section of RFC 1700.
681 ///
682 /// 1 Ethernet (10Mb) [JBP]
683 /// 2 Experimental Ethernet (3Mb) [JBP]
684 /// 3 Amateur Radio AX.25 [PXK]
685 /// 4 Proteon ProNET Token Ring [JBP]
686 /// 5 Chaos [GXP]
687 /// 6 IEEE 802 Networks [JBP]
688 /// 7 ARCNET [JBP]
689 /// 8 Hyperchannel [JBP]
690 /// 9 Lanstar [TU]
691 /// 10 Autonet Short Address [MXB1]
692 /// 11 LocalTalk [JKR1]
693 /// 12 LocalNet (IBM* PCNet or SYTEK* LocalNET) [JXM]
694 /// 13 Ultra link [RXD2]
695 /// 14 SMDS [GXC1]
696 /// 15 Frame Relay [AGM]
697 /// 16 Asynchronous Transmission Mode (ATM) [JXB2]
698 /// 17 HDLC [JBP]
699 /// 18 Fibre Channel [Yakov Rekhter]
700 /// 19 Asynchronous Transmission Mode (ATM) [Mark Laubach]
701 /// 20 Serial Line [JBP]
702 /// 21 Asynchronous Transmission Mode (ATM) [MXB1]
703 ///
704 /// * Other names and brands may be claimed as the property of others.
705 ///
706 #define PXE_IFTYPE_ETHERNET 0x01
707 #define PXE_IFTYPE_TOKENRING 0x04
708 #define PXE_IFTYPE_FIBRE_CHANNEL 0x12
709
710 typedef struct s_pxe_hw_undi {
711 PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE.
712 PXE_UINT8 Len; ///< sizeof(PXE_HW_UNDI).
713 PXE_UINT8 Fudge; ///< makes 8-bit cksum equal zero.
714 PXE_UINT8 Rev; ///< PXE_ROMID_REV.
715 PXE_UINT8 IFcnt; ///< physical connector count lower byte.
716 PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER.
717 PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER.
718 PXE_UINT8 IFcntExt; ///< physical connector count upper byte.
719 PXE_UINT8 reserved; ///< zero, not used.
720 PXE_UINT32 Implementation; ///< implementation flags.
721 ///< reserved ///< vendor use.
722 ///< UINT32 Status; ///< status port.
723 ///< UINT32 Command; ///< command port.
724 ///< UINT64 CDBaddr; ///< CDB address port.
725 ///<
726 } PXE_HW_UNDI;
727
728 ///
729 /// Status port bit definitions.
730 ///
731
732 ///
733 /// UNDI operation state.
734 ///
735 #define PXE_HWSTAT_STATE_MASK 0xC0000000
736 #define PXE_HWSTAT_BUSY 0xC0000000
737 #define PXE_HWSTAT_INITIALIZED 0x80000000
738 #define PXE_HWSTAT_STARTED 0x40000000
739 #define PXE_HWSTAT_STOPPED 0x00000000
740
741 ///
742 /// If set, last command failed.
743 ///
744 #define PXE_HWSTAT_COMMAND_FAILED 0x20000000
745
746 ///
747 /// If set, identifies enabled receive filters.
748 ///
749 #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000
750 #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800
751 #define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400
752 #define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200
753 #define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100
754
755 ///
756 /// If set, identifies enabled external interrupts.
757 ///
758 #define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080
759 #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040
760 #define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020
761 #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010
762
763 ///
764 /// If set, identifies pending interrupts.
765 ///
766 #define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008
767 #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004
768 #define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002
769 #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001
770
771 ///
772 /// Command port definitions.
773 ///
774
775 ///
776 /// If set, CDB identified in CDBaddr port is given to UNDI.
777 /// If not set, other bits in this word will be processed.
778 ///
779 #define PXE_HWCMD_ISSUE_COMMAND 0x80000000
780 #define PXE_HWCMD_INTS_AND_FILTS 0x00000000
781
782 ///
783 /// Use these to enable/disable receive filters.
784 ///
785 #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000
786 #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800
787 #define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400
788 #define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200
789 #define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100
790
791 ///
792 /// Use these to enable/disable external interrupts.
793 ///
794 #define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080
795 #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040
796 #define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020
797 #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010
798
799 ///
800 /// Use these to clear pending external interrupts.
801 ///
802 #define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008
803 #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004
804 #define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002
805 #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001
806
807 typedef struct s_pxe_sw_undi {
808 PXE_UINT32 Signature; ///< PXE_ROMID_SIGNATURE.
809 PXE_UINT8 Len; ///< sizeof(PXE_SW_UNDI).
810 PXE_UINT8 Fudge; ///< makes 8-bit cksum zero.
811 PXE_UINT8 Rev; ///< PXE_ROMID_REV.
812 PXE_UINT8 IFcnt; ///< physical connector count lower byte.
813 PXE_UINT8 MajorVer; ///< PXE_ROMID_MAJORVER.
814 PXE_UINT8 MinorVer; ///< PXE_ROMID_MINORVER.
815 PXE_UINT8 IFcntExt; ///< physical connector count upper byte.
816 PXE_UINT8 reserved1; ///< zero, not used.
817 PXE_UINT32 Implementation; ///< Implementation flags.
818 PXE_UINT64 EntryPoint; ///< API entry point.
819 PXE_UINT8 reserved2[3]; ///< zero, not used.
820 PXE_UINT8 BusCnt; ///< number of bustypes supported.
821 PXE_UINT32 BusType[1]; ///< list of supported bustypes.
822 } PXE_SW_UNDI;
823
824 typedef union u_pxe_undi {
825 PXE_HW_UNDI hw;
826 PXE_SW_UNDI sw;
827 } PXE_UNDI;
828
829 ///
830 /// Signature of !PXE structure.
831 ///
832 #define PXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E')
833
834 ///
835 /// !PXE structure format revision
836 /// .
837 #define PXE_ROMID_REV 0x02
838
839 ///
840 /// UNDI command interface revision. These are the values that get sent
841 /// in option 94 (Client Network Interface Identifier) in the DHCP Discover
842 /// and PXE Boot Server Request packets.
843 ///
844 #define PXE_ROMID_MAJORVER 0x03
845 #define PXE_ROMID_MINORVER 0x01
846
847 ///
848 /// Implementation flags.
849 ///
850 #define PXE_ROMID_IMP_HW_UNDI 0x80000000
851 #define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000
852 #define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000
853 #define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000
854 #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000
855 #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000
856 #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000
857 #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00
858 #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00
859 #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800
860 #define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400
861 #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000
862 #define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200
863 #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100
864 #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080
865 #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040
866 #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020
867 #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010
868 #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008
869 #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004
870 #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002
871 #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001
872
873 typedef struct s_pxe_cdb {
874 PXE_OPCODE OpCode;
875 PXE_OPFLAGS OpFlags;
876 PXE_UINT16 CPBsize;
877 PXE_UINT16 DBsize;
878 PXE_UINT64 CPBaddr;
879 PXE_UINT64 DBaddr;
880 PXE_STATCODE StatCode;
881 PXE_STATFLAGS StatFlags;
882 PXE_UINT16 IFnum;
883 PXE_CONTROL Control;
884 } PXE_CDB;
885
886 typedef union u_pxe_ip_addr {
887 PXE_IPV6 IPv6;
888 PXE_IPV4 IPv4;
889 } PXE_IP_ADDR;
890
891 typedef union pxe_device {
892 ///
893 /// PCI and PC Card NICs are both identified using bus, device
894 /// and function numbers. For PC Card, this may require PC
895 /// Card services to be loaded in the BIOS or preboot
896 /// environment.
897 ///
898 struct {
899 ///
900 /// See S/W UNDI ROMID structure definition for PCI and
901 /// PCC BusType definitions.
902 ///
903 PXE_UINT32 BusType;
904
905 ///
906 /// Bus, device & function numbers that locate this device.
907 ///
908 PXE_UINT16 Bus;
909 PXE_UINT8 Device;
910 PXE_UINT8 Function;
911 } PCI, PCC;
912 } PXE_DEVICE;
913
914 ///
915 /// cpb and db definitions
916 ///
917 #define MAX_PCI_CONFIG_LEN 64 ///< # of dwords.
918 #define MAX_EEPROM_LEN 128 ///< # of dwords.
919 #define MAX_XMIT_BUFFERS 32 ///< recycling Q length for xmit_done.
920 #define MAX_MCAST_ADDRESS_CNT 8
921
922 typedef struct s_pxe_cpb_start_30 {
923 ///
924 /// PXE_VOID Delay(UINTN microseconds);
925 ///
926 /// UNDI will never request a delay smaller than 10 microseconds
927 /// and will always request delays in increments of 10 microseconds.
928 /// The Delay() CallBack routine must delay between n and n + 10
929 /// microseconds before returning control to the UNDI.
930 ///
931 /// This field cannot be set to zero.
932 ///
933 UINT64 Delay;
934
935 ///
936 /// PXE_VOID Block(UINT32 enable);
937 ///
938 /// UNDI may need to block multi-threaded/multi-processor access to
939 /// critical code sections when programming or accessing the network
940 /// device. To this end, a blocking service is needed by the UNDI.
941 /// When UNDI needs a block, it will call Block() passing a non-zero
942 /// value. When UNDI no longer needs a block, it will call Block()
943 /// with a zero value. When called, if the Block() is already enabled,
944 /// do not return control to the UNDI until the previous Block() is
945 /// disabled.
946 ///
947 /// This field cannot be set to zero.
948 ///
949 UINT64 Block;
950
951 ///
952 /// PXE_VOID Virt2Phys(UINT64 virtual, UINT64 physical_ptr);
953 ///
954 /// UNDI will pass the virtual address of a buffer and the virtual
955 /// address of a 64-bit physical buffer. Convert the virtual address
956 /// to a physical address and write the result to the physical address
957 /// buffer. If virtual and physical addresses are the same, just
958 /// copy the virtual address to the physical address buffer.
959 ///
960 /// This field can be set to zero if virtual and physical addresses
961 /// are equal.
962 ///
963 UINT64 Virt2Phys;
964 ///
965 /// PXE_VOID Mem_IO(UINT8 read_write, UINT8 len, UINT64 port,
966 /// UINT64 buf_addr);
967 ///
968 /// UNDI will read or write the device io space using this call back
969 /// function. It passes the number of bytes as the len parameter and it
970 /// will be either 1,2,4 or 8.
971 ///
972 /// This field can not be set to zero.
973 ///
974 UINT64 Mem_IO;
975 } PXE_CPB_START_30;
976
977 typedef struct s_pxe_cpb_start_31 {
978 ///
979 /// PXE_VOID Delay(UINT64 UnqId, UINTN microseconds);
980 ///
981 /// UNDI will never request a delay smaller than 10 microseconds
982 /// and will always request delays in increments of 10 microseconds.
983 /// The Delay() CallBack routine must delay between n and n + 10
984 /// microseconds before returning control to the UNDI.
985 ///
986 /// This field cannot be set to zero.
987 ///
988 UINT64 Delay;
989
990 ///
991 /// PXE_VOID Block(UINT64 unq_id, UINT32 enable);
992 ///
993 /// UNDI may need to block multi-threaded/multi-processor access to
994 /// critical code sections when programming or accessing the network
995 /// device. To this end, a blocking service is needed by the UNDI.
996 /// When UNDI needs a block, it will call Block() passing a non-zero
997 /// value. When UNDI no longer needs a block, it will call Block()
998 /// with a zero value. When called, if the Block() is already enabled,
999 /// do not return control to the UNDI until the previous Block() is
1000 /// disabled.
1001 ///
1002 /// This field cannot be set to zero.
1003 ///
1004 UINT64 Block;
1005
1006 ///
1007 /// PXE_VOID Virt2Phys(UINT64 UnqId, UINT64 virtual, UINT64 physical_ptr);
1008 ///
1009 /// UNDI will pass the virtual address of a buffer and the virtual
1010 /// address of a 64-bit physical buffer. Convert the virtual address
1011 /// to a physical address and write the result to the physical address
1012 /// buffer. If virtual and physical addresses are the same, just
1013 /// copy the virtual address to the physical address buffer.
1014 ///
1015 /// This field can be set to zero if virtual and physical addresses
1016 /// are equal.
1017 ///
1018 UINT64 Virt2Phys;
1019 ///
1020 /// PXE_VOID Mem_IO(UINT64 UnqId, UINT8 read_write, UINT8 len, UINT64 port,
1021 /// UINT64 buf_addr);
1022 ///
1023 /// UNDI will read or write the device io space using this call back
1024 /// function. It passes the number of bytes as the len parameter and it
1025 /// will be either 1,2,4 or 8.
1026 ///
1027 /// This field can not be set to zero.
1028 ///
1029 UINT64 Mem_IO;
1030 ///
1031 /// PXE_VOID Map_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1032 /// UINT32 Direction, UINT64 mapped_addr);
1033 ///
1034 /// UNDI will pass the virtual address of a buffer, direction of the data
1035 /// flow from/to the mapped buffer (the constants are defined below)
1036 /// and a place holder (pointer) for the mapped address.
1037 /// This call will Map the given address to a physical DMA address and write
1038 /// the result to the mapped_addr pointer. If there is no need to
1039 /// map the given address to a lower address (i.e. the given address is
1040 /// associated with a physical address that is already compatible to be
1041 /// used with the DMA, it converts the given virtual address to it's
1042 /// physical address and write that in the mapped address pointer.
1043 ///
1044 /// This field can be set to zero if there is no mapping service available.
1045 ///
1046 UINT64 Map_Mem;
1047
1048 ///
1049 /// PXE_VOID UnMap_Mem(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,
1050 /// UINT32 Direction, UINT64 mapped_addr);
1051 ///
1052 /// UNDI will pass the virtual and mapped addresses of a buffer.
1053 /// This call will un map the given address.
1054 ///
1055 /// This field can be set to zero if there is no unmapping service available.
1056 ///
1057 UINT64 UnMap_Mem;
1058
1059 ///
1060 /// PXE_VOID Sync_Mem(UINT64 unq_id, UINT64 virtual,
1061 /// UINT32 size, UINT32 Direction, UINT64 mapped_addr);
1062 ///
1063 /// UNDI will pass the virtual and mapped addresses of a buffer.
1064 /// This call will synchronize the contents of both the virtual and mapped.
1065 /// buffers for the given Direction.
1066 ///
1067 /// This field can be set to zero if there is no service available.
1068 ///
1069 UINT64 Sync_Mem;
1070
1071 ///
1072 /// protocol driver can provide anything for this Unique_ID, UNDI remembers
1073 /// that as just a 64bit value associated to the interface specified by
1074 /// the ifnum and gives it back as a parameter to all the call-back routines
1075 /// when calling for that interface!
1076 ///
1077 UINT64 Unique_ID;
1078 } PXE_CPB_START_31;
1079
1080 #define TO_AND_FROM_DEVICE 0
1081 #define FROM_DEVICE 1
1082 #define TO_DEVICE 2
1083
1084 #define PXE_DELAY_MILLISECOND 1000
1085 #define PXE_DELAY_SECOND 1000000
1086 #define PXE_IO_READ 0
1087 #define PXE_IO_WRITE 1
1088 #define PXE_MEM_READ 2
1089 #define PXE_MEM_WRITE 4
1090
1091 typedef struct s_pxe_db_get_init_info {
1092 ///
1093 /// Minimum length of locked memory buffer that must be given to
1094 /// the Initialize command. Giving UNDI more memory will generally
1095 /// give better performance.
1096 ///
1097 /// If MemoryRequired is zero, the UNDI does not need and will not
1098 /// use system memory to receive and transmit packets.
1099 ///
1100 PXE_UINT32 MemoryRequired;
1101
1102 ///
1103 /// Maximum frame data length for Tx/Rx excluding the media header.
1104 ///
1105 PXE_UINT32 FrameDataLen;
1106
1107 ///
1108 /// Supported link speeds are in units of mega bits. Common ethernet
1109 /// values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero
1110 /// filled.
1111 ///
1112 PXE_UINT32 LinkSpeeds[4];
1113
1114 ///
1115 /// Number of non-volatile storage items.
1116 ///
1117 PXE_UINT32 NvCount;
1118
1119 ///
1120 /// Width of non-volatile storage item in bytes. 0, 1, 2 or 4
1121 ///
1122 PXE_UINT16 NvWidth;
1123
1124 ///
1125 /// Media header length. This is the typical media header length for
1126 /// this UNDI. This information is needed when allocating receive
1127 /// and transmit buffers.
1128 ///
1129 PXE_UINT16 MediaHeaderLen;
1130
1131 ///
1132 /// Number of bytes in the NIC hardware (MAC) address.
1133 ///
1134 PXE_UINT16 HWaddrLen;
1135
1136 ///
1137 /// Maximum number of multicast MAC addresses in the multicast
1138 /// MAC address filter list.
1139 ///
1140 PXE_UINT16 MCastFilterCnt;
1141
1142 ///
1143 /// Default number and size of transmit and receive buffers that will
1144 /// be allocated by the UNDI. If MemoryRequired is non-zero, this
1145 /// allocation will come out of the memory buffer given to the Initialize
1146 /// command. If MemoryRequired is zero, this allocation will come out of
1147 /// memory on the NIC.
1148 ///
1149 PXE_UINT16 TxBufCnt;
1150 PXE_UINT16 TxBufSize;
1151 PXE_UINT16 RxBufCnt;
1152 PXE_UINT16 RxBufSize;
1153
1154 ///
1155 /// Hardware interface types defined in the Assigned Numbers RFC
1156 /// and used in DHCP and ARP packets.
1157 /// See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros.
1158 ///
1159 PXE_UINT8 IFtype;
1160
1161 ///
1162 /// Supported duplex. See PXE_DUPLEX_xxxxx #defines below.
1163 ///
1164 PXE_UINT8 SupportedDuplexModes;
1165
1166 ///
1167 /// Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below.
1168 ///
1169 PXE_UINT8 SupportedLoopBackModes;
1170 } PXE_DB_GET_INIT_INFO;
1171
1172 #define PXE_MAX_TXRX_UNIT_ETHER 1500
1173
1174 #define PXE_HWADDR_LEN_ETHER 0x0006
1175 #define PXE_MAC_HEADER_LEN_ETHER 0x000E
1176
1177 #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1
1178 #define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2
1179
1180 #define PXE_LOOPBACK_INTERNAL_SUPPORTED 1
1181 #define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2
1182
1183 typedef struct s_pxe_pci_config_info {
1184 ///
1185 /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1186 /// For PCI bus devices, this field is set to PXE_BUSTYPE_PCI.
1187 ///
1188 UINT32 BusType;
1189
1190 ///
1191 /// This identifies the PCI network device that this UNDI interface.
1192 /// is bound to.
1193 ///
1194 UINT16 Bus;
1195 UINT8 Device;
1196 UINT8 Function;
1197
1198 ///
1199 /// This is a copy of the PCI configuration space for this
1200 /// network device.
1201 ///
1202 union {
1203 UINT8 Byte[256];
1204 UINT16 Word[128];
1205 UINT32 Dword[64];
1206 } Config;
1207 } PXE_PCI_CONFIG_INFO;
1208
1209 typedef struct s_pxe_pcc_config_info {
1210 ///
1211 /// This is the flag field for the PXE_DB_GET_CONFIG_INFO union.
1212 /// For PCC bus devices, this field is set to PXE_BUSTYPE_PCC.
1213 ///
1214 PXE_UINT32 BusType;
1215
1216 ///
1217 /// This identifies the PCC network device that this UNDI interface
1218 /// is bound to.
1219 ///
1220 PXE_UINT16 Bus;
1221 PXE_UINT8 Device;
1222 PXE_UINT8 Function;
1223
1224 ///
1225 /// This is a copy of the PCC configuration space for this
1226 /// network device.
1227 ///
1228 union {
1229 PXE_UINT8 Byte[256];
1230 PXE_UINT16 Word[128];
1231 PXE_UINT32 Dword[64];
1232 } Config;
1233 } PXE_PCC_CONFIG_INFO;
1234
1235 typedef union u_pxe_db_get_config_info {
1236 PXE_PCI_CONFIG_INFO pci;
1237 PXE_PCC_CONFIG_INFO pcc;
1238 } PXE_DB_GET_CONFIG_INFO;
1239
1240 typedef struct s_pxe_cpb_initialize {
1241 ///
1242 /// Address of first (lowest) byte of the memory buffer. This buffer must
1243 /// be in contiguous physical memory and cannot be swapped out. The UNDI
1244 /// will be using this for transmit and receive buffering.
1245 ///
1246 PXE_UINT64 MemoryAddr;
1247
1248 ///
1249 /// MemoryLength must be greater than or equal to MemoryRequired
1250 /// returned by the Get Init Info command.
1251 ///
1252 PXE_UINT32 MemoryLength;
1253
1254 ///
1255 /// Desired link speed in Mbit/sec. Common ethernet values are 10, 100
1256 /// and 1000. Setting a value of zero will auto-detect and/or use the
1257 /// default link speed (operation depends on UNDI/NIC functionality).
1258 ///
1259 PXE_UINT32 LinkSpeed;
1260
1261 ///
1262 /// Suggested number and size of receive and transmit buffers to
1263 /// allocate. If MemoryAddr and MemoryLength are non-zero, this
1264 /// allocation comes out of the supplied memory buffer. If MemoryAddr
1265 /// and MemoryLength are zero, this allocation comes out of memory
1266 /// on the NIC.
1267 ///
1268 /// If these fields are set to zero, the UNDI will allocate buffer
1269 /// counts and sizes as it sees fit.
1270 ///
1271 PXE_UINT16 TxBufCnt;
1272 PXE_UINT16 TxBufSize;
1273 PXE_UINT16 RxBufCnt;
1274 PXE_UINT16 RxBufSize;
1275
1276 ///
1277 /// The following configuration parameters are optional and must be zero
1278 /// to use the default values.
1279 ///
1280 PXE_UINT8 DuplexMode;
1281
1282 PXE_UINT8 LoopBackMode;
1283 } PXE_CPB_INITIALIZE;
1284
1285 #define PXE_DUPLEX_DEFAULT 0x00
1286 #define PXE_FORCE_FULL_DUPLEX 0x01
1287 #define PXE_ENABLE_FULL_DUPLEX 0x02
1288 #define PXE_FORCE_HALF_DUPLEX 0x04
1289 #define PXE_DISABLE_FULL_DUPLEX 0x08
1290
1291 #define LOOPBACK_NORMAL 0
1292 #define LOOPBACK_INTERNAL 1
1293 #define LOOPBACK_EXTERNAL 2
1294
1295 typedef struct s_pxe_db_initialize {
1296 ///
1297 /// Actual amount of memory used from the supplied memory buffer. This
1298 /// may be less that the amount of memory suppllied and may be zero if
1299 /// the UNDI and network device do not use external memory buffers.
1300 ///
1301 /// Memory used by the UNDI and network device is allocated from the
1302 /// lowest memory buffer address.
1303 ///
1304 PXE_UINT32 MemoryUsed;
1305
1306 ///
1307 /// Actual number and size of receive and transmit buffers that were
1308 /// allocated.
1309 ///
1310 PXE_UINT16 TxBufCnt;
1311 PXE_UINT16 TxBufSize;
1312 PXE_UINT16 RxBufCnt;
1313 PXE_UINT16 RxBufSize;
1314 } PXE_DB_INITIALIZE;
1315
1316 typedef struct s_pxe_cpb_receive_filters {
1317 ///
1318 /// List of multicast MAC addresses. This list, if present, will
1319 /// replace the existing multicast MAC address filter list.
1320 ///
1321 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1322 } PXE_CPB_RECEIVE_FILTERS;
1323
1324 typedef struct s_pxe_db_receive_filters {
1325 ///
1326 /// Filtered multicast MAC address list.
1327 ///
1328 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT];
1329 } PXE_DB_RECEIVE_FILTERS;
1330
1331 typedef struct s_pxe_cpb_station_address {
1332 ///
1333 /// If supplied and supported, the current station MAC address
1334 /// will be changed.
1335 ///
1336 PXE_MAC_ADDR StationAddr;
1337 } PXE_CPB_STATION_ADDRESS;
1338
1339 typedef struct s_pxe_dpb_station_address {
1340 ///
1341 /// Current station MAC address.
1342 ///
1343 PXE_MAC_ADDR StationAddr;
1344
1345 ///
1346 /// Station broadcast MAC address.
1347 ///
1348 PXE_MAC_ADDR BroadcastAddr;
1349
1350 ///
1351 /// Permanent station MAC address.
1352 ///
1353 PXE_MAC_ADDR PermanentAddr;
1354 } PXE_DB_STATION_ADDRESS;
1355
1356 typedef struct s_pxe_db_statistics {
1357 ///
1358 /// Bit field identifying what statistic data is collected by the
1359 /// UNDI/NIC.
1360 /// If bit 0x00 is set, Data[0x00] is collected.
1361 /// If bit 0x01 is set, Data[0x01] is collected.
1362 /// If bit 0x20 is set, Data[0x20] is collected.
1363 /// If bit 0x21 is set, Data[0x21] is collected.
1364 /// Etc.
1365 ///
1366 PXE_UINT64 Supported;
1367
1368 ///
1369 /// Statistic data.
1370 ///
1371 PXE_UINT64 Data[64];
1372 } PXE_DB_STATISTICS;
1373
1374 ///
1375 /// Total number of frames received. Includes frames with errors and
1376 /// dropped frames.
1377 ///
1378 #define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00
1379
1380 ///
1381 /// Number of valid frames received and copied into receive buffers.
1382 ///
1383 #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01
1384
1385 ///
1386 /// Number of frames below the minimum length for the media.
1387 /// This would be <64 for ethernet.
1388 ///
1389 #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02
1390
1391 ///
1392 /// Number of frames longer than the maxminum length for the
1393 /// media. This would be >1500 for ethernet.
1394 ///
1395 #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03
1396
1397 ///
1398 /// Valid frames that were dropped because receive buffers were full.
1399 ///
1400 #define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04
1401
1402 ///
1403 /// Number of valid unicast frames received and not dropped.
1404 ///
1405 #define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05
1406
1407 ///
1408 /// Number of valid broadcast frames received and not dropped.
1409 ///
1410 #define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06
1411
1412 ///
1413 /// Number of valid mutlicast frames received and not dropped.
1414 ///
1415 #define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07
1416
1417 ///
1418 /// Number of frames w/ CRC or alignment errors.
1419 ///
1420 #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08
1421
1422 ///
1423 /// Total number of bytes received. Includes frames with errors
1424 /// and dropped frames.
1425 ///
1426 #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09
1427
1428 ///
1429 /// Transmit statistics.
1430 ///
1431 #define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A
1432 #define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B
1433 #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C
1434 #define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D
1435 #define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E
1436 #define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F
1437 #define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10
1438 #define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11
1439 #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12
1440 #define PXE_STATISTICS_TX_TOTAL_BYTES 0x13
1441
1442 ///
1443 /// Number of collisions detection on this subnet.
1444 ///
1445 #define PXE_STATISTICS_COLLISIONS 0x14
1446
1447 ///
1448 /// Number of frames destined for unsupported protocol.
1449 ///
1450 #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15
1451
1452 ///
1453 /// Number of valid frames received that were duplicated.
1454 ///
1455 #define PXE_STATISTICS_RX_DUPLICATED_FRAMES 0x16
1456
1457 ///
1458 /// Number of encrypted frames received that failed to decrypt.
1459 ///
1460 #define PXE_STATISTICS_RX_DECRYPT_ERROR_FRAMES 0x17
1461
1462 ///
1463 /// Number of frames that failed to transmit after exceeding the retry limit.
1464 ///
1465 #define PXE_STATISTICS_TX_ERROR_FRAMES 0x18
1466
1467 ///
1468 /// Number of frames transmitted successfully after more than one attempt.
1469 ///
1470 #define PXE_STATISTICS_TX_RETRY_FRAMES 0x19
1471
1472 typedef struct s_pxe_cpb_mcast_ip_to_mac {
1473 ///
1474 /// Multicast IP address to be converted to multicast MAC address.
1475 ///
1476 PXE_IP_ADDR IP;
1477 } PXE_CPB_MCAST_IP_TO_MAC;
1478
1479 typedef struct s_pxe_db_mcast_ip_to_mac {
1480 ///
1481 /// Multicast MAC address.
1482 ///
1483 PXE_MAC_ADDR MAC;
1484 } PXE_DB_MCAST_IP_TO_MAC;
1485
1486 typedef struct s_pxe_cpb_nvdata_sparse {
1487 ///
1488 /// NvData item list. Only items in this list will be updated.
1489 ///
1490 struct {
1491 ///
1492 /// Non-volatile storage address to be changed.
1493 ///
1494 PXE_UINT32 Addr;
1495
1496 ///
1497 /// Data item to write into above storage address.
1498 ///
1499 union {
1500 PXE_UINT8 Byte;
1501 PXE_UINT16 Word;
1502 PXE_UINT32 Dword;
1503 } Data;
1504 } Item[MAX_EEPROM_LEN];
1505 } PXE_CPB_NVDATA_SPARSE;
1506
1507 ///
1508 /// When using bulk update, the size of the CPB structure must be
1509 /// the same size as the non-volatile NIC storage.
1510 ///
1511 typedef union u_pxe_cpb_nvdata_bulk {
1512 ///
1513 /// Array of byte-wide data items.
1514 ///
1515 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];
1516
1517 ///
1518 /// Array of word-wide data items.
1519 ///
1520 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];
1521
1522 ///
1523 /// Array of dword-wide data items.
1524 ///
1525 PXE_UINT32 Dword[MAX_EEPROM_LEN];
1526 } PXE_CPB_NVDATA_BULK;
1527
1528 typedef struct s_pxe_db_nvdata {
1529 ///
1530 /// Arrays of data items from non-volatile storage.
1531 ///
1532 union {
1533 ///
1534 /// Array of byte-wide data items.
1535 ///
1536 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2];
1537
1538 ///
1539 /// Array of word-wide data items.
1540 ///
1541 PXE_UINT16 Word[MAX_EEPROM_LEN << 1];
1542
1543 ///
1544 /// Array of dword-wide data items.
1545 ///
1546 PXE_UINT32 Dword[MAX_EEPROM_LEN];
1547 } Data;
1548 } PXE_DB_NVDATA;
1549
1550 typedef struct s_pxe_db_get_status {
1551 ///
1552 /// Length of next receive frame (header + data). If this is zero,
1553 /// there is no next receive frame available.
1554 ///
1555 PXE_UINT32 RxFrameLen;
1556
1557 ///
1558 /// Reserved, set to zero.
1559 ///
1560 PXE_UINT32 reserved;
1561
1562 ///
1563 /// Addresses of transmitted buffers that need to be recycled.
1564 ///
1565 PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS];
1566 } PXE_DB_GET_STATUS;
1567
1568 typedef struct s_pxe_cpb_fill_header {
1569 ///
1570 /// Source and destination MAC addresses. These will be copied into
1571 /// the media header without doing byte swapping.
1572 ///
1573 PXE_MAC_ADDR SrcAddr;
1574 PXE_MAC_ADDR DestAddr;
1575
1576 ///
1577 /// Address of first byte of media header. The first byte of packet data
1578 /// follows the last byte of the media header.
1579 ///
1580 PXE_UINT64 MediaHeader;
1581
1582 ///
1583 /// Length of packet data in bytes (not including the media header).
1584 ///
1585 PXE_UINT32 PacketLen;
1586
1587 ///
1588 /// Protocol type. This will be copied into the media header without
1589 /// doing byte swapping. Protocol type numbers can be obtained from
1590 /// the Assigned Numbers RFC 1700.
1591 ///
1592 PXE_UINT16 Protocol;
1593
1594 ///
1595 /// Length of the media header in bytes.
1596 ///
1597 PXE_UINT16 MediaHeaderLen;
1598 } PXE_CPB_FILL_HEADER;
1599
1600 #define PXE_PROTOCOL_ETHERNET_IP 0x0800
1601 #define PXE_PROTOCOL_ETHERNET_ARP 0x0806
1602 #define MAX_XMIT_FRAGMENTS 16
1603
1604 typedef struct s_pxe_cpb_fill_header_fragmented {
1605 ///
1606 /// Source and destination MAC addresses. These will be copied into
1607 /// the media header without doing byte swapping.
1608 ///
1609 PXE_MAC_ADDR SrcAddr;
1610 PXE_MAC_ADDR DestAddr;
1611
1612 ///
1613 /// Length of packet data in bytes (not including the media header).
1614 ///
1615 PXE_UINT32 PacketLen;
1616
1617 ///
1618 /// Protocol type. This will be copied into the media header without
1619 /// doing byte swapping. Protocol type numbers can be obtained from
1620 /// the Assigned Numbers RFC 1700.
1621 ///
1622 PXE_MEDIA_PROTOCOL Protocol;
1623
1624 ///
1625 /// Length of the media header in bytes.
1626 ///
1627 PXE_UINT16 MediaHeaderLen;
1628
1629 ///
1630 /// Number of packet fragment descriptors.
1631 ///
1632 PXE_UINT16 FragCnt;
1633
1634 ///
1635 /// Reserved, must be set to zero.
1636 ///
1637 PXE_UINT16 reserved;
1638
1639 ///
1640 /// Array of packet fragment descriptors. The first byte of the media
1641 /// header is the first byte of the first fragment.
1642 ///
1643 struct {
1644 ///
1645 /// Address of this packet fragment.
1646 ///
1647 PXE_UINT64 FragAddr;
1648
1649 ///
1650 /// Length of this packet fragment.
1651 ///
1652 PXE_UINT32 FragLen;
1653
1654 ///
1655 /// Reserved, must be set to zero.
1656 ///
1657 PXE_UINT32 reserved;
1658 } FragDesc[MAX_XMIT_FRAGMENTS];
1659 } PXE_CPB_FILL_HEADER_FRAGMENTED;
1660
1661 typedef struct s_pxe_cpb_transmit {
1662 ///
1663 /// Address of first byte of frame buffer. This is also the first byte
1664 /// of the media header.
1665 ///
1666 PXE_UINT64 FrameAddr;
1667
1668 ///
1669 /// Length of the data portion of the frame buffer in bytes. Do not
1670 /// include the length of the media header.
1671 ///
1672 PXE_UINT32 DataLen;
1673
1674 ///
1675 /// Length of the media header in bytes.
1676 ///
1677 PXE_UINT16 MediaheaderLen;
1678
1679 ///
1680 /// Reserved, must be zero.
1681 ///
1682 PXE_UINT16 reserved;
1683 } PXE_CPB_TRANSMIT;
1684
1685 typedef struct s_pxe_cpb_transmit_fragments {
1686 ///
1687 /// Length of packet data in bytes (not including the media header).
1688 ///
1689 PXE_UINT32 FrameLen;
1690
1691 ///
1692 /// Length of the media header in bytes.
1693 ///
1694 PXE_UINT16 MediaheaderLen;
1695
1696 ///
1697 /// Number of packet fragment descriptors.
1698 ///
1699 PXE_UINT16 FragCnt;
1700
1701 ///
1702 /// Array of frame fragment descriptors. The first byte of the first
1703 /// fragment is also the first byte of the media header.
1704 ///
1705 struct {
1706 ///
1707 /// Address of this frame fragment.
1708 ///
1709 PXE_UINT64 FragAddr;
1710
1711 ///
1712 /// Length of this frame fragment.
1713 ///
1714 PXE_UINT32 FragLen;
1715
1716 ///
1717 /// Reserved, must be set to zero.
1718 ///
1719 PXE_UINT32 reserved;
1720 } FragDesc[MAX_XMIT_FRAGMENTS];
1721 } PXE_CPB_TRANSMIT_FRAGMENTS;
1722
1723 typedef struct s_pxe_cpb_receive {
1724 ///
1725 /// Address of first byte of receive buffer. This is also the first byte
1726 /// of the frame header.
1727 ///
1728 PXE_UINT64 BufferAddr;
1729
1730 ///
1731 /// Length of receive buffer. This must be large enough to hold the
1732 /// received frame (media header + data). If the length of smaller than
1733 /// the received frame, data will be lost.
1734 ///
1735 PXE_UINT32 BufferLen;
1736
1737 ///
1738 /// Reserved, must be set to zero.
1739 ///
1740 PXE_UINT32 reserved;
1741 } PXE_CPB_RECEIVE;
1742
1743 typedef struct s_pxe_db_receive {
1744 ///
1745 /// Source and destination MAC addresses from media header.
1746 ///
1747 PXE_MAC_ADDR SrcAddr;
1748 PXE_MAC_ADDR DestAddr;
1749
1750 ///
1751 /// Length of received frame. May be larger than receive buffer size.
1752 /// The receive buffer will not be overwritten. This is how to tell
1753 /// if data was lost because the receive buffer was too small.
1754 ///
1755 PXE_UINT32 FrameLen;
1756
1757 ///
1758 /// Protocol type from media header.
1759 ///
1760 PXE_MEDIA_PROTOCOL Protocol;
1761
1762 ///
1763 /// Length of media header in received frame.
1764 ///
1765 PXE_UINT16 MediaHeaderLen;
1766
1767 ///
1768 /// Type of receive frame.
1769 ///
1770 PXE_FRAME_TYPE Type;
1771
1772 ///
1773 /// Reserved, must be zero.
1774 ///
1775 PXE_UINT8 reserved[7];
1776 } PXE_DB_RECEIVE;
1777
1778 #pragma pack()
1779
1780 #endif