Removed duplicate PalCallStatic functions in different libraries. Moved ReadItc and...
[mirror_edk2.git] / MdePkg / Library / BaseCacheMaintenanceLib / IpfCache.c
1 /** @file
2 Cache Maintenance Functions.
3
4 Copyright (c) 2006, Intel Corporation<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15
16 /**
17 Invalidates the entire instruction cache in cache coherency domain of the
18 calling CPU.
19
20 Invalidates the entire instruction cache in cache coherency domain of the
21 calling CPU.
22
23 **/
24 VOID
25 EFIAPI
26 InvalidateInstructionCache (
27 VOID
28 )
29 {
30 PalCallStatic (NULL, 1, 1, 1, 0);
31 }
32
33 /**
34 Invalidates a range of instruction cache lines in the cache coherency domain
35 of the calling CPU.
36
37 Invalidates the instruction cache lines specified by Address and Length. If
38 Address is not aligned on a cache line boundary, then entire instruction
39 cache line containing Address is invalidated. If Address + Length is not
40 aligned on a cache line boundary, then the entire instruction cache line
41 containing Address + Length -1 is invalidated. This function may choose to
42 invalidate the entire instruction cache if that is more efficient than
43 invalidating the specified range. If Length is 0, the no instruction cache
44 lines are invalidated. Address is returned.
45
46 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
47
48 @param Address The base address of the instruction cache lines to
49 invalidate. If the CPU is in a physical addressing mode, then
50 Address is a physical address. If the CPU is in a virtual
51 addressing mode, then Address is a virtual address.
52
53 @param Length The number of bytes to invalidate from the instruction cache.
54
55 @return Address
56
57 **/
58 VOID *
59 EFIAPI
60 InvalidateInstructionCacheRange (
61 IN VOID *Address,
62 IN UINTN Length
63 )
64 {
65 return IpfInvalidateInstructionCacheRange (Address, Length);
66 }
67
68 /**
69 Writes Back and Invalidates the entire data cache in cache coherency domain
70 of the calling CPU.
71
72 Writes Back and Invalidates the entire data cache in cache coherency domain
73 of the calling CPU. This function guarantees that all dirty cache lines are
74 written back to system memory, and also invalidates all the data cache lines
75 in the cache coherency domain of the calling CPU.
76
77 **/
78 VOID
79 EFIAPI
80 WriteBackInvalidateDataCache (
81 VOID
82 )
83 {
84 PalCallStatic (NULL, 1, 2, 1, 0);
85 }
86
87 /**
88 Writes Back and Invalidates a range of data cache lines in the cache
89 coherency domain of the calling CPU.
90
91 Writes Back and Invalidate the data cache lines specified by Address and
92 Length. If Address is not aligned on a cache line boundary, then entire data
93 cache line containing Address is written back and invalidated. If Address +
94 Length is not aligned on a cache line boundary, then the entire data cache
95 line containing Address + Length -1 is written back and invalidated. This
96 function may choose to write back and invalidate the entire data cache if
97 that is more efficient than writing back and invalidating the specified
98 range. If Length is 0, the no data cache lines are written back and
99 invalidated. Address is returned.
100
101 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
102
103 @param Address The base address of the data cache lines to write back and
104 invalidate. If the CPU is in a physical addressing mode, then
105 Address is a physical address. If the CPU is in a virtual
106 addressing mode, then Address is a virtual address.
107 @param Length The number of bytes to write back and invalidate from the
108 data cache.
109
110 @return Address
111
112 **/
113 VOID *
114 EFIAPI
115 WriteBackInvalidateDataCacheRange (
116 IN VOID *Address,
117 IN UINTN Length
118 )
119 {
120 ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
121
122 if (Length > 0) {
123 WriteBackInvalidateDataCache ();
124 }
125 return Address;
126 }
127
128 /**
129 Writes Back the entire data cache in cache coherency domain of the calling
130 CPU.
131
132 Writes Back the entire data cache in cache coherency domain of the calling
133 CPU. This function guarantees that all dirty cache lines are written back to
134 system memory. This function may also invalidate all the data cache lines in
135 the cache coherency domain of the calling CPU.
136
137 **/
138 VOID
139 EFIAPI
140 WriteBackDataCache (
141 VOID
142 )
143 {
144 PalCallStatic (NULL, 1, 2, 0, 0);
145 }
146
147 /**
148 Writes Back a range of data cache lines in the cache coherency domain of the
149 calling CPU.
150
151 Writes Back the data cache lines specified by Address and Length. If Address
152 is not aligned on a cache line boundary, then entire data cache line
153 containing Address is written back. If Address + Length is not aligned on a
154 cache line boundary, then the entire data cache line containing Address +
155 Length -1 is written back. This function may choose to write back the entire
156 data cache if that is more efficient than writing back the specified range.
157 If Length is 0, the no data cache lines are written back. This function may
158 also invalidate all the data cache lines in the specified range of the cache
159 coherency domain of the calling CPU. Address is returned.
160
161 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
162
163 @param Address The base address of the data cache lines to write back. If
164 the CPU is in a physical addressing mode, then Address is a
165 physical address. If the CPU is in a virtual addressing
166 mode, then Address is a virtual address.
167 @param Length The number of bytes to write back from the data cache.
168
169 @return Address
170
171 **/
172 VOID *
173 EFIAPI
174 WriteBackDataCacheRange (
175 IN VOID *Address,
176 IN UINTN Length
177 )
178 {
179 ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
180
181 if (Length > 0) {
182 WriteBackDataCache ();
183 }
184 return Address;
185 }
186
187 /**
188 Invalidates the entire data cache in cache coherency domain of the calling
189 CPU.
190
191 Invalidates the entire data cache in cache coherency domain of the calling
192 CPU. This function must be used with care because dirty cache lines are not
193 written back to system memory. It is typically used for cache diagnostics. If
194 the CPU does not support invalidation of the entire data cache, then a write
195 back and invalidate operation should be performed on the entire data cache.
196
197 **/
198 VOID
199 EFIAPI
200 InvalidateDataCache (
201 VOID
202 )
203 {
204 WriteBackInvalidateDataCache ();
205 }
206
207 /**
208 Invalidates a range of data cache lines in the cache coherency domain of the
209 calling CPU.
210
211 Invalidates the data cache lines specified by Address and Length. If Address
212 is not aligned on a cache line boundary, then entire data cache line
213 containing Address is invalidated. If Address + Length is not aligned on a
214 cache line boundary, then the entire data cache line containing Address +
215 Length -1 is invalidated. This function must never invalidate any cache lines
216 outside the specified range. If Length is 0, the no data cache lines are
217 invalidated. Address is returned. This function must be used with care
218 because dirty cache lines are not written back to system memory. It is
219 typically used for cache diagnostics. If the CPU does not support
220 invalidation of a data cache range, then a write back and invalidate
221 operation should be performed on the data cache range.
222
223 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
224
225 @param Address The base address of the data cache lines to invalidate. If
226 the CPU is in a physical addressing mode, then Address is a
227 physical address. If the CPU is in a virtual addressing mode,
228 then Address is a virtual address.
229 @param Length The number of bytes to invalidate from the data cache.
230
231 @return Address
232
233 **/
234 VOID *
235 EFIAPI
236 InvalidateDataCacheRange (
237 IN VOID *Address,
238 IN UINTN Length
239 )
240 {
241 return WriteBackInvalidateDataCacheRange (Address, Length);
242 }